JPH04236649A - Data transfer device - Google Patents

Abstract

PURPOSE:To transfer data at a high speed even at the time of requiring memory-memory transfer plural times and to effectively use a memory. CONSTITUTION:A transfer source reference address 27, a transfer destination base address Z, an offset X, and a frequency (n) in memory-memory transfer are given from a CPU 21 to a DMAC 26 and are held. The first memory- memory transfer with an offset Xn is executed based on the transfer destination base address Z. Next, an operation part 30 adds the offset Xn to the transfer destination base address Z at each time of the end of memory-memory transfer. The next memory-memory transfer is executed based on the addition result (transfer destination base address Z)+(offset Xn), and hereafter, memory-memory transfer is repeatedly executed n times to continuously fill up the memory space. A counter 29 counts down the frequency (n) in memory-memory transfer at each time of the end of memory-memory transfer, and transfer is terminated when the counter reaches 0.

Description

[Detailed description of the invention]

0001

[Industrial Application Field] The present invention relates to direct memory
The present invention relates to a data transfer device that transfers data between memories in a computer system using an access controller (hereinafter referred to as DMAC).

0002

2. Description of the Related Art In computer systems, the most time-consuming memory access-related processing is often performed on behalf of the DMAC because it exceeds the processing capacity of the central processing unit (hereinafter referred to as CPU).

[0003] Data transfer by the above-mentioned conventional DMAC will be explained below with reference to the drawings. FIG. 5 is a block diagram showing the configuration of a data transfer device which is a conventional computer system having a DMAC. In FIG. 5, a data bus 4, an address bus 5, and a command bus 6 connect a CPU 1, a memory 2, and a DMAC 3, respectively.

FIG. 6 is a conceptual diagram showing the state of the memory space when memory-to-memory transfer is performed using DMAC in the configuration shown in FIG. In FIG. 6, 7 is the entire memory space, A
is a transfer source reference address, B is a transfer destination reference address, and X is an offset indicating the address width to be transferred.

The operation of the above configuration will be explained below. First, the CPU 1 sends the DMAC 3 a transfer source reference address A, a transfer destination reference address B, and an offset X.
are given as parameters using the data bus 4, address bus 5 and command bus 6. When a data transfer request is made to the DMAC3, the DMAC3 requests the bus control right from the CPU1 using the command bus 6, and then the CPU1 passes the bus control right to the DMAC3. After writing the parameters and acquiring bus control through handshake communication, the DMAC 3 transfers the memory block between the addresses added or subtracted X times from the source reference address A to the memory 2 to the destination reference address B. Data is transferred to the memory block between the addresses added or subtracted from X times. After one transfer, DMAC
3 returns the bus control right to the CPU 1 and ends the data transfer.

[0006]

[Problems to be Solved by the Invention] However, in the conventional configuration described above, communication between the CPU 1 and the DMAC 3 is repeated for each memory-to-memory transfer. However, there was a problem in that high-speed data transfer could not be performed due to the high-speed data transfer. At the same time, since the transfer destination reference address B is different for each memory-to-memory transfer, there is a problem in that memory blocks are spaced and memory space is wasted.

The present invention solves the above-mentioned conventional problems, and allows high-speed data transfer even when memory-to-memory transfer is required several times, and also makes it possible to use memory effectively. The purpose is to provide a data transfer device.

[0008]

[Means for Solving the Problems] In order to solve the above problems, a data transfer device of the present invention includes a CPU, a memory connected to the CPU by a data bus, an address bus, and a command bus, and is connected to the memory by a data bus, an address bus, and a command bus, and can access any address in the memory independently of the CPU, and the entire memory space of the memory can be accessed from a predetermined reference address A. X times (offset)
In memory-to-memory transfer in which data is transferred from a memory block between addresses that have been added to or subtracted from another predetermined reference address B to a memory block between addresses that have been added to or subtracted from X times, the predetermined reference addresses A, B
, offset and a DMAC capable of memory-to-memory transfer.

[0009] Furthermore, the data transfer device of the present invention has a CPU
and a memory connected to the CPU by a data bus, an address bus, and a command bus, and a memory connected to the CPU and memory by a data bus, an address bus, and a command bus and independent of the CPU and connected to the memory. Any address can be accessed, and predetermined reference addresses A to X can be accessed for the entire memory space of the memory.
In memory-to-memory transfer in which data is transferred from a memory block between addresses that have been added or subtracted X times (offset) to a memory block between addresses that have been added or subtracted X times from another predetermined reference address B, reference address B The forwarding base address Z is given instead of
Offset X based on this forwarding destination base address Z
execute the first memory-to-memory transfer, and then execute the next memory-to-memory transfer based on the addition result of (the transfer destination base address Z) + (the offset X),
A DMAC that can be controlled to successively fill the memory space by sequentially executing n memory-to-memory transfers based on the addition result obtained by sequentially adding an offset X to the addition result.
It is equipped with the following.

0010

[Operation] According to the structure of claim 1, a plurality of different reference addresses and different offsets are obtained by using n times of predetermined reference addresses A and B set in the DMAC, offset X, and memory-to-memory transfer number parameter n. Since memory-to-memory transfers are performed n times in succession, n times of memory-to-memory transfers can be performed in succession at once, resulting in high-speed memory.
Memory transfer becomes possible.

According to the configuration of claim 2, the DMAC is given a transfer destination base address Z instead of the transfer destination reference address B, and the first memory-to-memory transfer of offset X is performed using this transfer destination base address Z as a reference. Then, the next memory-to-memory transfer is performed based on the addition result of (the transfer destination base address Z) + (the offset Since the memory space is successively filled in by performing n-time memory-to-memory transfers based on , the memory is used effectively and high-speed memory-to-memory transfer is possible.

0012

Embodiments Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing the configuration of a data transfer device according to a first embodiment of the present invention. In FIG. 1, a data bus 13, an address bus 14, and a command bus 15 connect a CPU 11 and a memory 12. Further, the DMAC 16 is connected to the CPU 11 and the memory 12 by a data bus 13, an address bus 14, and a command bus 15, and can access any address in the memory 12 without depending on the CPU 11. DMAC
16 is used to add or subtract the memory blocks between the addresses that have been added or subtracted X times from the transfer source reference address 17 to the entire memory space of the memory 12 and the memory blocks that have been added or subtracted X times from the other transfer destination reference address 18. When performing a memory-to-memory transfer that transfers data to a memory block between addresses, in addition to the parameters of the source reference address 17, destination reference address 18, offset is D
It is given to the MAC 16 from the CPU 11 and is held there. In this case, the DMAC 16 also sets the transfer source reference address 17, the transfer destination reference address 18, and the offset n.
It has a configuration that can be set in batches. The DMAC 16 is configured to perform memory-to-memory transfer n times in succession with a plurality of different reference addresses and a plurality of different offsets with respect to the memory 12. Here, the DMAC 16 is provided with a counter 19, and the counter 19
The number of memory transfers held in memory 6 is expressed as
Each time a memory transfer is completed, it is decremented, that is, subtracted, and the transfer is completed when n=0.

The operation of the above configuration will be explained below. First, for the DMAC 16, the CPU 11 sends a transfer source reference address 17n, a transfer destination reference address 18n, and an offset Xn, a transfer source reference address 17n-1, a transfer destination reference address 18n-1, and an offset Xn-1.
. . . are set up to n=1, and the number of memory-to-memory transfers n is set. Subsequently, when a data transfer request is made to the DMAC 16, the DMAC 16 requests the CPU 11 for bus control rights via the command bus 15, and then the CPU 11 hands over the bus control rights to the DMAC 16. After each parameter write and handshake communication described above, the DMAC 16 transfers data bus 13 and address bus 1.
4 and the command bus 15 to the memory space from the first transfer source reference address 18n and write the data to the transfer destination reference address 19n, perform the above read/write operation for the offset number Xn, and 1 The second memory-to-memory transfer is completed. Subsequently, the value of the counter 19 is subtracted once and the process moves to the next memory-to-memory transfer. In other words, data is read from the transfer source reference address 18n-1, data is written to the transfer destination reference address 19n-1, and the above read/write operation is performed with an offset number of Xn.
-1 is performed, and the second memory-to-memory transfer is completed. When the above operations are executed until n=0, the bus control right is returned to the CPU 11 and the data transfer is completed. Figure 2 shows this situation, in which data is transferred from the source reference address 17n to the destination reference address 18n by offset Xn times in the first transfer, and then from the transfer source reference address 17n-1 in the second transfer. Transfer destination standard address 1
Data is transferred to 8n-1 by offset Xn-1 times. In this way, by providing the DMAC 16 with the transfer source reference address, transfer destination reference address, and offset for n times, and the number of transfers n, it is possible to perform multiple memory-to-memory transfers in succession at high speed. Become.

FIG. 3 is a block diagram showing the configuration of a data transfer device according to a second embodiment of the present invention. In Figure 3, C
The PU 21 and the memory 22 are connected by a data bus 23, an address bus 24, and a command bus 25. Further, the DMAC 26 is connected to the CPU 21 and the memory 22 by a data bus 23, an address bus 24, and a command bus 25, and can access any address in the memory 22 without depending on the CPU 21. The memory block between the addresses added or subtracted X times from the transfer source reference address 27 to the entire memory space of the memory 22 is used as the memory block between the addresses added or subtracted X times from the transfer destination reference address 28 mentioned above. When transferring data from the CPU 21 to the memory that transfers data to the block,
A transfer destination base address Z is given to the MAC 26 instead of the transfer destination reference address 28 and is held. That is, by setting the transfer destination base address Z, all the transfer destination reference addresses 28 become invalid. The first memory-to-memory transfer of offset Xn is performed using this transfer destination base address Z as a reference. The DMAC 26 is provided with an arithmetic unit 30, which holds a transfer destination base address Z, and sequentially adds an offset go. Based on this added (transfer destination base address Z) + (offset Xn), the next memory
Memory transfer is executed, and then memory-to-memory transfer is repeatedly executed n times to fill the memory space continuously. Here, the counter 29 provided in the DMAC 26 is
The number n of memory-to-memory transfers held in the MAC 26 is subtracted each time a memory-to-memory transfer is completed,
The configuration is such that the transfer ends when n=0.

The operation of the above configuration will be explained below. First, among the n memory-to-memory transfers, the first transfer is performed by an offset Xn from the transfer source base address 27n with reference to the transfer destination base address Z, and the second
The calculation unit 30 calculates (transfer destination base address Z) + (
The offset number Xn) is calculated, and transfer is started to an address that is (transfer destination base address Z)+(offset number Xn) ahead. Further, the counter 29 subtracts the number n of memory-to-memory transfers every time one memory-to-memory transfer is completed. In this way, memory-to-memory transfer is performed n times and the process ends. FIG. 4 shows this situation. In the memory-to-memory transfer starting from the transfer source address 27n, data for offset Xn times is transferred to the memory address starting from the transfer destination base address Z.
Furthermore, the memory starting from the transfer source address 27n-1
In the memory transfer, data for offset Xn-1 times is transferred to the memory address starting from (transfer destination base address Z) + (previous offset number Xn). Similarly, (Z+Xn+Xn-1), (Z+Xn+X
n-1 +...),... is repeated n times in sequence. As a result, necessary data can be collected in a continuous memory space at once, and memory can be used effectively.

[0016]

As described above, according to the present invention, in addition to the predetermined reference addresses A, B, offset By performing n consecutive memory-to-memory transfers with different reference addresses and different offsets, n times of memory-to-memory transfers can be performed consecutively at once. This allows high-speed transfer.

A transfer destination base address Z is given instead of the reference address B, and the first memory-to-memory transfer of offset X is executed using this transfer destination base address Z as a reference, and then (the transfer destination base address Z) + (
The next memory-to-memory transfer is executed based on the addition result of the offset By controlling the data to be filled with the data, memory-to-memory transfer can be made faster and the memory can be used more effectively.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of a data transfer device in a first embodiment of the present invention.

FIG. 2 is a conceptual diagram showing a state of memory-to-memory transfer of the memory space in FIG. 1;

FIG. 3 is a block diagram showing the configuration of a data transfer device in a second embodiment of the present invention.

FIG. 4 is a conceptual diagram showing a state of memory-to-memory transfer of the memory space in FIG. 3;

FIG. 5 is a block diagram showing the configuration of a conventional data transfer device.

FIG. 6 is a conceptual diagram showing a state of memory-to-memory transfer of the memory space in FIG. 5;

[Explanation of symbols]

11, 21 CPU 12, 22 Memory 13, 23 Data bus 14, 24 Address bus 15, 25 Command bus 16, 26 DMAC 17, 17n, 17n-1,... Transfer source reference address 18, 18n, 18n-1,... - Transfer destination reference address 19, 29 Counter 27, 27n, 27n-1,... Transfer source reference address 28, 28n, 28n-1,... Transfer destination reference address 30 Arithmetic unit

Claims (2)

[Claims] 1. A central processing unit, a memory connected to the central processing unit by a data bus, an address bus, and a command bus; and a memory connected to the central processing unit and the memory by a data bus, an address bus, and a command bus. It is possible to access any address in the memory without depending on the central processing unit, and X times (
In memory-to-memory transfer in which data is transferred from a memory block between addresses to which X offsets have been added or subtracted from another predetermined reference address B to a memory block between addresses to which X times have been added or subtracted, the predetermined reference address A ,B, Offset Direct memory-to-memory transfer possible
A data transfer device comprising a memory access controller. 2. A central processing unit, a memory connected to the central processing unit by a data bus, an address bus, and a command bus; and a memory connected to the central processing unit and the memory by a data bus, an address bus, and a command bus. It is possible to access any address in the memory without depending on the central processing unit, and X times (
In a memory-to-memory transfer in which data is transferred from a memory block between addresses to which an offset (offset) has been added or subtracted from another predetermined reference address B to a memory block between addresses to which an offset has been added or subtracted X times, the reference address B
A transfer destination base address Z is given instead of , and the first memory-to-memory transfer of offset X is performed using this transfer destination base address Z as a reference, and then Execute the next memory-to-memory transfer based on the addition result of X), and then sequentially execute n memory-to-memory transfers based on the addition result obtained by sequentially adding offset X to the above addition result to make the memory space continuous. Controllable direct filling
A data transfer device comprising a memory access controller.