JPS6122823B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a main memory control device in a data processing device or the like.

BACKGROUND ART Data processing devices such as electronic computers need to process access requests (hereinafter referred to as "requests") from other computing devices at high speed. At this time, guaranteeing the order of storing and fetching into the main memory is an issue that must always be considered.

Conventionally, a circuit that compares a store address and a fetch address is used to detect whether or not there is a conflict between the two addresses (hereinafter referred to as a "conflict"), and to make a request with a lower priority wait and store it in the main memory. The order of access was guaranteed. Therefore, address comparison circuits proportional to the number of stacked addresses are required, resulting in problems such as an increase in the size of the main memory control device and complicated control.

It is an object of the present invention to solve the above-mentioned problems of conventional main memory control devices, and to enable storage requests and fetch requests that are stacked as requests to the main memory by a simple configuration. An object of the present invention is to provide a main memory control device which generates requests to the main memory in the same order.

The above object of the present invention is to provide a main memory control device having a store stack for storing a plurality of store requests and a fetch stack for storing a plurality of fetch requests, by providing independent input/output pointers for each of the fetch requests. A third input/output pointer is provided to control the order of requests within the server, as well as the order of requests including both store requests and fetch requests, so as to guarantee the access order of store requests and fetch requests. This is achieved by a main memory controller that controls the main memory.

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of a main memory control device showing one embodiment of the present invention. In the figure, 1 is a store stack, and in this example, up to three addresses and three store data each are stored. 2 is a fetch stack in which only one address is stored. 3,
4 are the input and output pointers of the store stack, respectively, and updates are performed in the order of 0→1→2→0... Status latches 5 and 6 indicate the busy status of the store stack and fetch stack, respectively.

When a store request is issued from the central processing unit (CPU) 12 through the store line 3A, the address and store data are sent to the store stack indicated by the store input pointer 3 through the address line 1A and store data line 2A. The data is taken in, and the store input pointer 3 is updated by one.

Control units 7, 8, and 9 store the order of generation of store requests and fetch requests from the central processing unit 12, and issue the requests to the main memory 13 in accordance with the order of generation. Here, 8 and 9 are the request input/output pointers for both store and fetch, respectively, and the update is from 0 to 1.
It is performed in the order of →2 →3 →0. Reference numeral 7 indicates a request storage unit for both store and fetch, and if the request is a store, the latch b _i of the request storage unit 7 indicated by the input pointer 8, (i=0,
1, 2, and 3), and if the request is a fetch, they are similarly stored in c _i and the request input pointer 8 is updated by one. The store input pointer 3 is updated only by store requests, whereas the request input pointer 8 is updated by both store and fetch requests.

On the other hand, the request storage unit 7 indicated by the request output pointer 9 of both the store and fetch
The latches b _i and c _i of are output to the request output latch 10, and when a of the request output latch 10 becomes "1", the request line 5A to the main memory 13 becomes "1", and at this time, the b of the request storage section 7 becomes "1". When _i is "1", b of the request output latch becomes "1", and the store order line 6A to the main memory 13 becomes "1". Similarly, when c _i of the request storage section 7 is "1", c of the request output latch 10 is "1".
Therefore, store order line 7 to main memory 13
A becomes "1". Therefore, the store output pointer 4 is updated by one when b of the request output latch 10 becomes "1", whereas the request output pointer 9 is updated by one when b of the request output latch 10 becomes "1".
When either c becomes "1", that is, when a of the request output latch 10 becomes "1", it is updated by one.

Regarding the address to the main memory 13, the store address is outputted to the store address output line 8A by the store output pointer 4, and the fetch address is outputted to the fetch address output line 9A. When either output b or c becomes “1”, the main memory 13
Depending on whether the order is a store or a fetch, the selector 11 selects the line 8A or 9A, and a predetermined address to the address output line 10A is determined. Store data to the main memory 13 is determined by the store output pointer 4 to the store data output line 11A. In this way, main memory 1
It is possible to generate requests to the main memory 13 in the order in which the store requests and fetch requests, which are stacked as requests to 3, are requested.

As described in detail above, according to the present invention, in a main memory control device having a store stack that stores a plurality of store requests and a fetch stack that stores a plurality of fetch requests, independent input/output pointers can be used. A third input/output pointer is provided to control the order of requests within each request, and also to control the order of requests including both store requests and fetch requests. Since the control is performed to guarantee the order, there is no need for a large number of comparison circuits to examine whether there is a conflict between the store address and fetch address as in the past.
With a simple configuration, store requests and fetch requests that are stacked as requests to main memory can be generated to the main memory in the order in which they are requested.
It has a remarkable practical effect.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a main memory control device showing one embodiment of the present invention. 1: Store stack, 2: Fetish stack,
3: Store input pointer, 4: Store output stack, 5: Store stack busy status display latch,
6: Fetish stack busy status display latch,
7: Request storage unit, 8: Store, Fetch request input pointer, 9: Store, Fetch request output pointer, 10: Request output latch, 11: Selector, 12: Central processing unit, 1
3: Main memory.

Claims (1)

[Claims] 1. In a main memory control device having a store stack that stores a plurality of store requests and a fetch stack that stores a plurality of fetch requests, independent input/output pointers are provided to control the order of requests within each of the requests. In addition, a third input/output pointer is provided to control the order of requests including both store requests and fetch requests, and the access order of store requests and fetch requests is controlled so as to be guaranteed. main memory controller.