JPH04333206A - Laminated ceramic capacitor - Google Patents

Laminated ceramic capacitor

Info

Publication number
JPH04333206A
JPH04333206A JP3131925A JP13192591A JPH04333206A JP H04333206 A JPH04333206 A JP H04333206A JP 3131925 A JP3131925 A JP 3131925A JP 13192591 A JP13192591 A JP 13192591A JP H04333206 A JPH04333206 A JP H04333206A
Authority
JP
Japan
Prior art keywords
bare chip
band
capacitor
ceramic capacitor
multilayer ceramic
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3131925A
Other languages
Japanese (ja)
Inventor
Kaoru Nishizawa
薫 西澤
Hisashi Yamaguchi
尚志 山口
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Materials Corp
Original Assignee
Mitsubishi Materials Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Materials Corp filed Critical Mitsubishi Materials Corp
Priority to JP3131925A priority Critical patent/JPH04333206A/en
Publication of JPH04333206A publication Critical patent/JPH04333206A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/0213Electrical arrangements not otherwise provided for
    • H05K1/0254High voltage adaptations; Electrical insulation details; Overvoltage or electrostatic discharge protection ; Arrangements for regulating voltages or for using plural voltages
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341Surface mounted components
    • H05K3/3431Leadless components

Landscapes

  • Ceramic Capacitors (AREA)
  • Fixed Capacitors And Capacitor Manufacturing Machines (AREA)

Abstract

PURPOSE:To prevent creeping discharge at low cost and to easily mount the title capacitor on a circuit substrate without generation of cracks in the internal part and also without requiring many man-hours. CONSTITUTION:A band 15, consisting of an organic insulator, is provided on the surface of the bare chip located between terminal electrodes of the laminated ceramic capacitor 10 on which a plurality of inner electrodes 14 are opposingly provided in the bare chip 11 and also a pair of terminal electrodes 12a and 12b, which are electrically connected to an internal electrode 14, are provided on both terminal parts 11a and 11b of the bare chip. Even when high AC voltage is applied to the capacitor 10, a current is hardly allowed to flow from the terminal electrode on one side to the other terminal electrode along the surface of the bare chip by the presence of the band 15.

Description

【発明の詳細な説明】[Detailed description of the invention]

【0001】0001

【産業上の利用分野】本発明は表面実装型の中高圧用積
層セラミックコンデンサに関する。更に詳しくは積層セ
ラミックコンデンサの沿面放電を防止するための外面構
造に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a surface-mounted multilayer ceramic capacitor for medium and high voltages. More specifically, the present invention relates to an outer surface structure for preventing creeping discharge of a multilayer ceramic capacitor.

【0002】0002

【従来の技術】積層セラミックコンデンサは、内部電極
とセラミック誘電体とを交互に積層することにより複数
の内部電極同士が対向するベアチップを形成し、このベ
アチップの端部に内部電極が取出され、この取出された
部分を含むベアチップの端部を包込むように覆って外部
接続用の端子電極を形成して作られる。一方、近年積層
セラミックコンデンサの技術開発が進み、従来はタンタ
ルコンデンサや電解コンデンサが用いられた分野にまで
積層セラミックコンデンサが使用され始めている。例え
ばスイッチング電源の平滑用コンデンサ等が挙げられる
。このような用途ではコンデンサは大容量で高耐圧であ
ることが要求され、しかも交流での耐電圧特性が重要と
なっている。
[Prior Art] Multilayer ceramic capacitors form a bare chip in which a plurality of internal electrodes face each other by alternately laminating internal electrodes and ceramic dielectrics, and the internal electrodes are extracted from the ends of this bare chip. It is made by covering the end of the bare chip, including the extracted portion, to form terminal electrodes for external connection. On the other hand, the technological development of multilayer ceramic capacitors has progressed in recent years, and multilayer ceramic capacitors are beginning to be used in fields where tantalum capacitors and electrolytic capacitors have traditionally been used. Examples include smoothing capacitors for switching power supplies. In such applications, capacitors are required to have large capacity and high voltage resistance, and voltage resistance characteristics under alternating current are important.

【0003】特に、この種の積層セラミックコンデンサ
は空気中で高電圧が印加された場合、沿面放電と呼ばれ
る現象が起き易い。これは端子電極間でコロナ放電が起
き、ベアチップ表面に沿って電流が流れる現象である。 この現象は交流で特に顕著に起き、500Vrms程度
で発生するため、電源用途などでは大きな問題となる。 コロナ発生電圧以上の電圧を印加すると、コロナは大き
くなり、最終的には一対の端子電極間で激しく放電し、
絶縁不良又は誘電体層の絶縁破壊を引起こす恐れがあっ
た。従来、この沿面放電を防止するために、コンデンサ
を回路基板に実装してはんだ付けした後で、コンデンサ
表面に絶縁性のオイルを塗布したり、回路全体を樹脂で
封止する絶縁処理がなされていた。また別の沿面放電の
防止方法として、コンデンサの両端の端子電極にそれぞ
れリード線をはんだ付けし、各リード線をエポキシ樹脂
でコーティングしてラジアルリード品の形態にしてから
回路基板にはんだ付けしていた。
In particular, this type of multilayer ceramic capacitor is susceptible to a phenomenon called creeping discharge when a high voltage is applied in the air. This is a phenomenon in which corona discharge occurs between terminal electrodes and current flows along the bare chip surface. This phenomenon occurs particularly markedly with alternating current, and occurs at about 500 Vrms, and therefore becomes a big problem in power supply applications. When a voltage higher than the corona generation voltage is applied, the corona becomes larger and eventually violently discharges between a pair of terminal electrodes.
There was a risk of insulation failure or dielectric breakdown of the dielectric layer. Conventionally, in order to prevent this creeping discharge, after the capacitor has been mounted on a circuit board and soldered, insulation treatment has been performed, such as applying insulating oil to the capacitor surface or sealing the entire circuit with resin. Ta. Another method for preventing creeping discharge is to solder lead wires to the terminal electrodes at both ends of the capacitor, coat each lead wire with epoxy resin to form a radial lead product, and then solder it to the circuit board. Ta.

【0004】0004

【発明が解決しようとする課題】しかし、従来の沿面放
電を防止する前者の方法では、実装した回路基板毎にオ
イルを塗布したり、樹脂で封止しなければならず、その
ために多大の工数を要し、製造コストを高価なものにす
る問題点があった。また後者の方法では、リード線をコ
ーティングしたエポキシ樹脂が硬化するときに収縮して
コンデンサ内部にキュアクラックが入り易く、また製造
コストも高くなる不具合があった。本発明の目的は、多
大の工数を要することなく、また内部にクラックを発生
することもなく、低コストで沿面放電を防止し、容易に
回路基板に実装し得る積層セラミックコンデンサを提供
することにある。
[Problem to be Solved by the Invention] However, in the former method of preventing creeping discharge, it is necessary to apply oil or seal with resin to each mounted circuit board, which requires a large amount of man-hours. There was a problem in that the manufacturing cost was high. Further, in the latter method, when the epoxy resin coating the lead wires is cured, it shrinks and curing cracks are likely to occur inside the capacitor, and the manufacturing cost is also increased. An object of the present invention is to provide a multilayer ceramic capacitor that prevents creeping discharge at low cost without requiring a large number of man-hours, without causing internal cracks, and which can be easily mounted on a circuit board. be.

【0005】[0005]

【課題を解決するための手段】本発明者らは、端子電極
間のベアチップ表面に沿って発生するコロナ放電の障害
物をベアチップの表面に設ければ沿面放電を防止できる
ことを見出し、本発明に到達した。即ち、本発明は、図
1に示すようにベアチップ11の内部に複数の内部電極
14が互いに対向して設けられ、かつベアチップの両端
部11a,11bに内部電極14に電気的に接続された
一対の端子電極12a,12bが設けられた積層セラミ
ックコンデンサ10の改良である。その特徴ある構成は
、端子電極12a,12b間のベアチップ11の表面に
有機絶縁物よりなる帯15を巡らせたことにある。
[Means for Solving the Problems] The present inventors have discovered that creeping discharge can be prevented by providing an obstacle for corona discharge that occurs along the bare chip surface between terminal electrodes on the bare chip surface, and the present invention has been made based on the present invention. Reached. That is, in the present invention, as shown in FIG. 1, a plurality of internal electrodes 14 are provided inside a bare chip 11 facing each other, and a pair of internal electrodes 14 are electrically connected to both ends 11a and 11b of the bare chip. This is an improvement of a multilayer ceramic capacitor 10 provided with terminal electrodes 12a and 12b. Its characteristic structure lies in that a band 15 made of an organic insulator is wrapped around the surface of the bare chip 11 between the terminal electrodes 12a and 12b.

【0006】以下、本発明を詳述する。図1及び図2に
示すように、積層セラミックコンデンサ10は表面実装
型のチップコンデンサである。コンデンサ10はベアチ
ップ11の両端部11a,11bに一対の端子電極12
a,12bを備える。ベアチップ11は層表面に内部電
極14が印刷形成された複数のセラミック誘電体層を積
層することにより内部電極同士が対向するように形成さ
れる。内部電極14はベアチップの両端部11a,11
bに取出されて端子電極12a,12bに電気的に接続
される。ベアチップ11を構成するセラミック誘電体層
はチタン酸バリウム系、鉛ペロブスカイト系その他の誘
電体により構成され、内部電極14はPt,Ag/Pd
等の貴金属、或いはNi,Fe,Co,Cu,等の卑金
属のペーストを誘電体層の表面に印刷して形成され、ま
た端子電極はAg,Pd,Pt,Cuを1種又は2種以
上を含むペーストをベアチップ端面に塗布し焼付けて形
成される。
The present invention will be explained in detail below. As shown in FIGS. 1 and 2, the multilayer ceramic capacitor 10 is a surface-mounted chip capacitor. The capacitor 10 has a pair of terminal electrodes 12 at both ends 11a and 11b of the bare chip 11.
a, 12b. The bare chip 11 is formed by laminating a plurality of ceramic dielectric layers each having internal electrodes 14 printed on their surfaces so that the internal electrodes face each other. The internal electrodes 14 are located at both ends 11a, 11 of the bare chip.
b and is electrically connected to terminal electrodes 12a and 12b. The ceramic dielectric layer constituting the bare chip 11 is made of barium titanate, lead perovskite, or other dielectric, and the internal electrodes 14 are made of Pt, Ag/Pd.
The terminal electrodes are formed by printing a paste of noble metals such as Ni, Fe, Co, Cu, etc. or base metals such as Ni, Fe, Co, Cu, etc. on the surface of the dielectric layer. It is formed by applying a paste containing it to the end surface of a bare chip and baking it.

【0007】端子電極12a,12b間のベアチップ1
1の表面には有機絶縁物よりなる帯15が巡らされる。 この帯15の位置はベアチップ11の中央部表面が好ま
しい。有機絶縁物としては、耐熱性を有し、ベアチップ
との密着性が良く、印刷やコーティングにより容易に帯
を形成できる絶縁性有機物であれば、特に制限はなく、
市販のものを使用することができる。例示すれば、シア
ノアクリレート、ポリウレタン、エポキシ樹脂、フェノ
ール樹脂、イソシアネート等の接着剤、エステル系樹脂
とフェノール系樹脂とを混合したソルダーレジスト等が
挙げられる。帯15の幅はコンデンサ10の長さの少な
くとも10%であることが好ましい。これより帯の幅が
狭いと沿面放電の防止効果が不十分になる。帯15はベ
アチップ11に端子電極12a,12bを形成した後、
印刷又は刷毛塗りにより有機絶縁物をベアチップ表面に
塗布し、乾燥して形成される。
Bare chip 1 between terminal electrodes 12a and 12b
A band 15 made of an organic insulator is wrapped around the surface of the substrate 1 . The band 15 is preferably located on the central surface of the bare chip 11. There are no particular restrictions on the organic insulator as long as it is heat resistant, has good adhesion to the bare chip, and can be easily formed into a band by printing or coating.
Commercially available products can be used. Examples include adhesives such as cyanoacrylate, polyurethane, epoxy resin, phenol resin, and isocyanate, and solder resists made by mixing ester resin and phenol resin. Preferably, the width of band 15 is at least 10% of the length of capacitor 10. If the width of the band is narrower than this, the effect of preventing creeping discharge will be insufficient. After forming the terminal electrodes 12a and 12b on the bare chip 11, the band 15 is
It is formed by applying an organic insulator to the bare chip surface by printing or brushing and drying it.

【0008】[0008]

【作用】積層セラミックコンデンサ10に高い交流電圧
を印加しても、ベアチップ11の表面に有機絶縁物より
なる帯15が巡らされているため、この帯15の存在に
よりベアチップ表面に沿って一方の端子電極から他方の
端子電極に電流が流れにくくなる。
[Operation] Even if a high AC voltage is applied to the multilayer ceramic capacitor 10, since the band 15 made of an organic insulator is wrapped around the surface of the bare chip 11, the presence of this band 15 allows one terminal to be connected along the surface of the bare chip. It becomes difficult for current to flow from one electrode to the other terminal electrode.

【0009】[0009]

【発明の効果】以上述べたように、従来、実装した回路
基板毎にコンデンサに対してオイル塗布や樹脂による封
止処理を行い、或いはコンデンサをラジアルリード品の
形態にしたため、多大の工数を要しコスト高になってい
たものが、本発明によれば、ベアチップの表面に有機絶
縁物の帯を巡らせるだけ僅かな手間で安価に沿面放電を
防止することができる。特に、本発明の積層セラミック
コンデンサには、ラジラルリード品のようなキュアクラ
ックが発生する恐れもない。
[Effects of the Invention] As described above, in the past, capacitors were coated with oil or sealed with resin for each circuit board mounted, or capacitors were formed into radial lead products, which required a large amount of man-hours. However, according to the present invention, creeping discharge can be prevented at low cost and with little effort by simply wrapping an organic insulating band around the surface of a bare chip. In particular, in the multilayer ceramic capacitor of the present invention, there is no risk of curing cracks occurring as in radial lead products.

【0010】0010

【実施例】次に本発明の実施例を比較例とともに説明す
る。 <実施例1>積層セラミックコンデンサとして、定格直
流電圧500Vで静電容量220μFの特性を有する長
さ4.5mm、幅3.2mm、厚さ1.0mmの積層セ
ラミックチップコンデンサ(品番C70R2H222K
、三菱マテリアル(株)製)を用いた。上記積層セラミ
ックチップコンデンサは、鉛ペロブスカイト系のセラミ
ック誘電体にAg/Pd(Ag70/Pd30)の内部
電極を有し、端子電極としてガラスフリットを含んだA
gペーストの焼付け電極層を有する。この例では有機絶
縁物として、エポキシアクリレートを主成分とする無臭
性ソルダーレジスト(品番:S−30、太陽インキ製造
(株)製)を用いた。このレジストをベアチップの表面
中央部に塗布し、150℃で20分間乾燥して幅1mm
で厚さ0.3mmの有機絶縁物の帯を巡らせた。
EXAMPLES Next, examples of the present invention will be explained together with comparative examples. <Example 1> As a multilayer ceramic capacitor, a multilayer ceramic chip capacitor (product number C70R2H222K) with a length of 4.5 mm, a width of 3.2 mm, and a thickness of 1.0 mm has the characteristics of a capacitance of 220 μF at a rated DC voltage of 500 V.
, manufactured by Mitsubishi Materials Co., Ltd.) was used. The above multilayer ceramic chip capacitor has internal electrodes of Ag/Pd (Ag70/Pd30) in a lead perovskite ceramic dielectric, and an A
It has a baked electrode layer of g paste. In this example, an odorless solder resist (product number: S-30, manufactured by Taiyo Ink Manufacturing Co., Ltd.) containing epoxy acrylate as a main component was used as the organic insulator. Apply this resist to the center of the surface of the bare chip and dry it at 150°C for 20 minutes to make a width of 1 mm.
A band of organic insulator with a thickness of 0.3 mm was wrapped around it.

【0011】<実施例2>実施例1と同一の積層セラミ
ックコンデンサを用い、有機絶縁物として、粘着剤の主
成分がシリコーンアクリル系である耐熱性マスキング粘
着テープ(品番:No.260、千住金属(株)製)を
用いた。この粘着テープをベアチップの表面中央部に巻
付け、150℃で90分間乾燥して幅2mmで厚さ0.
6mmの有機絶縁物の帯を巡らせた。 <比較例1>実施例1と同一の積層セラミックコンデン
サを用い、有機絶縁物として、クロロプレンゴム接着剤
(品番:速乾ボンドG17、コニシ(株)製)を用いた
。 このゴム接着剤をベアチップの表面中央部に塗布し、1
50℃で20分間乾燥して幅2mmで厚さ0.8mmの
有機絶縁物の帯を巡らせた。 <比較例2>有機絶縁物の帯を形成しない以外は実施例
1と同じセラミックコンデンサを用いた。
<Example 2> The same multilayer ceramic capacitor as in Example 1 was used, and a heat-resistant masking adhesive tape (product number: No. 260, manufactured by Senju Metal Co., Ltd.) whose main component was silicone acrylic adhesive as an organic insulator was used. Co., Ltd.) was used. This adhesive tape was wrapped around the center of the surface of the bare chip and dried at 150°C for 90 minutes to a width of 2mm and a thickness of 0.5mm.
A 6 mm organic insulating band was wrapped around it. <Comparative Example 1> The same multilayer ceramic capacitor as in Example 1 was used, and a chloroprene rubber adhesive (product number: Quick-dry Bond G17, manufactured by Konishi Co., Ltd.) was used as the organic insulator. Apply this rubber adhesive to the center of the surface of the bare chip,
After drying at 50° C. for 20 minutes, a band of organic insulator with a width of 2 mm and a thickness of 0.8 mm was wrapped around it. <Comparative Example 2> The same ceramic capacitor as in Example 1 was used except that the organic insulating band was not formed.

【0012】<試験方法>実施例1,2及び比較例1,
2のセラミックコンデンサについて、諸特性を次の方法
により測定した。括弧内の数値nは試験した試料数であ
る。 (a) 静電容量(nF)及び誘電正接(%)(n=3
0)LCRメータ(ヒューレットパッカード社製 42
84型)を用いて、1kHz、1Vrmsで測定した。 (b) 絶縁抵抗(Ω)(n=15) 高抵抗計(ヒューレットパッカード社製4329A型)
を用いて、1000Vの直流電圧を5秒間印加した後、
25秒経過後の抵抗を測定した。 (c) 帯の耐熱性(n=10) H63A共晶はんだが250℃の温度で溶解するはんだ
槽の中に、ピンセットで試料を掴んで10秒間浸漬して
、試料の有機絶縁物からなる帯の耐熱性を調べた。 (d) 直流絶縁破壊試験(n=10)空気中又はシリ
コーン油中において直流電圧をカットオフ電流10mA
で、昇圧速度50V/secにより印加し、試料が沿面
放電を開始する電圧又は破壊を開始する電圧を測定した
。上記(a)〜(c)の結果を表1に、上記(d)の結
果を表2にそれぞれ示す。
<Test method> Examples 1 and 2 and comparative example 1,
Various characteristics of the ceramic capacitor No. 2 were measured using the following methods. The number n in parentheses is the number of samples tested. (a) Capacitance (nF) and dielectric loss tangent (%) (n=3
0) LCR meter (manufactured by Hewlett-Packard Company 42)
84 type) at 1 kHz and 1 Vrms. (b) Insulation resistance (Ω) (n=15) High resistance meter (Model 4329A manufactured by Hewlett-Packard)
After applying a DC voltage of 1000V for 5 seconds using
The resistance was measured after 25 seconds had elapsed. (c) Heat resistance of the strip (n=10) The sample was held with tweezers and immersed for 10 seconds in a solder bath where H63A eutectic solder melts at a temperature of 250°C. The heat resistance of the material was investigated. (d) DC dielectric breakdown test (n = 10) Cut off the DC voltage in air or silicone oil with a current of 10 mA.
The voltage was applied at a boost rate of 50 V/sec, and the voltage at which the sample started creeping discharge or breakdown was measured. The results of (a) to (c) above are shown in Table 1, and the results of (d) above are shown in Table 2.

【0013】[0013]

【表1】[Table 1]

【0014】[0014]

【表2】[Table 2]

【0015】<試験結果と評価>表1より、実施例1,
2及び比較例1,2とも静電容量及び誘電正接について
はほぼ同等の値を示した。帯を有しない比較例2は空気
中で沿面放電が生じたため、その絶縁抵抗をシリコーン
油中で測定した。実施例1,2及び比較例1は帯を有す
るために、空気中でも沿面放電は発生せず、そのときの
絶縁抵抗値はシリコーン油中の比較例2の絶縁抵抗値と
同じレベルであった。比較例1の帯は耐熱性に乏しく、
その耐熱性試験で全体の60%に当る6個の試料の帯が
溶解してしまった。これに対して実施例1,2の試料で
は1個の帯も溶解しなかった。表2において、破壊モー
ドAは誘電体破壊を、また破壊モードBは沿面放電を意
味する。表2より、帯を有する実施例1,2及び比較例
1は積層セラミックコンデンサ自体が破壊する限界電圧
まで昇圧可能であった。これに対して比較例2は帯を有
しないために上記限界電圧より低い電圧で沿面放電が発
生した。以上のことから、実施例1,2は比較例1,2
に比べて耐熱性があって、しかも極めて高い沿面放電防
止性能を有することが判った。
<Test results and evaluation> From Table 1, Example 1,
2 and Comparative Examples 1 and 2 showed almost the same values in terms of capacitance and dielectric loss tangent. In Comparative Example 2, which did not have a band, creeping discharge occurred in the air, so its insulation resistance was measured in silicone oil. Since Examples 1 and 2 and Comparative Example 1 had bands, creeping discharge did not occur even in the air, and the insulation resistance value at that time was at the same level as the insulation resistance value of Comparative Example 2 in silicone oil. The band of Comparative Example 1 had poor heat resistance;
During the heat resistance test, six sample bands, or 60% of the total, melted. In contrast, not a single band was dissolved in the samples of Examples 1 and 2. In Table 2, breakdown mode A means dielectric breakdown, and breakdown mode B means creeping discharge. From Table 2, in Examples 1 and 2 and Comparative Example 1 having bands, it was possible to boost the voltage to the limit voltage at which the multilayer ceramic capacitor itself was destroyed. On the other hand, since Comparative Example 2 did not have a band, creeping discharge occurred at a voltage lower than the above-mentioned limit voltage. From the above, Examples 1 and 2 are Comparative Examples 1 and 2
It was found that this material has higher heat resistance than that of the conventional method, and also has extremely high creeping discharge prevention performance.

【図面の簡単な説明】[Brief explanation of drawings]

【図1】本発明の積層セラミックコンデンサの断面図。FIG. 1 is a sectional view of a multilayer ceramic capacitor of the present invention.

【図2】その斜視図。FIG. 2 is a perspective view thereof.

【符号の説明】[Explanation of symbols]

10  積層セラミックコンデンサ 11  ベアチップ 11a,11b  ベアチップの端部 12a,12b  一対の端子電極 14  内部電極 15  帯 10 Multilayer ceramic capacitor 11 Bare chip 11a, 11b End of bare chip 12a, 12b A pair of terminal electrodes 14 Internal electrode 15 Obi

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】  ベアチップ(11)の内部に複数の内
部電極(14)が互いに対向して設けられ、かつ前記ベ
アチップの両端部(11a,11b)に前記内部電極(
14)に電気的に接続された一対の端子電極(12a,
12b)が設けられた積層セラミックコンデンサ(10
)において、前記端子電極(12a,12b)間のベア
チップ(11)の表面に有機絶縁物よりなる帯(15)
を巡らせたことを特徴とする積層セラミックコンデンサ
1. A plurality of internal electrodes (14) are provided inside a bare chip (11) facing each other, and the internal electrodes (14) are provided at both ends (11a, 11b) of the bare chip.
A pair of terminal electrodes (12a, 14) electrically connected to
A multilayer ceramic capacitor (10
), a band (15) made of an organic insulator is provided on the surface of the bare chip (11) between the terminal electrodes (12a, 12b).
A multilayer ceramic capacitor characterized by a circuit of .
【請求項2】  帯(15)がコンデンサ(10)の長
さの少なくとも10%の幅を有する請求項1記載の積層
セラミックコンデンサ。
2. A multilayer ceramic capacitor according to claim 1, wherein the band (15) has a width of at least 10% of the length of the capacitor (10).
JP3131925A 1991-05-08 1991-05-08 Laminated ceramic capacitor Pending JPH04333206A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3131925A JPH04333206A (en) 1991-05-08 1991-05-08 Laminated ceramic capacitor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3131925A JPH04333206A (en) 1991-05-08 1991-05-08 Laminated ceramic capacitor

Publications (1)

Publication Number Publication Date
JPH04333206A true JPH04333206A (en) 1992-11-20

Family

ID=15069412

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3131925A Pending JPH04333206A (en) 1991-05-08 1991-05-08 Laminated ceramic capacitor

Country Status (1)

Country Link
JP (1) JPH04333206A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003023259A (en) * 2001-07-10 2003-01-24 Hamamatsu Photonics Kk Laminate and its surface processing method
JP2008060214A (en) * 2006-08-30 2008-03-13 Murata Mfg Co Ltd Mounting structure of laminated ceramic electronic component
US20130063864A1 (en) * 2011-09-09 2013-03-14 Hon Hai Precision Industry Co., Ltd. Multi-layer ceramic electronic component with solder blocking layer
JP2015076591A (en) * 2013-10-11 2015-04-20 Tdk株式会社 Feedthrough capacitor
JP2020071923A (en) * 2018-10-29 2020-05-07 株式会社村田製作所 Electronic component

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61162036U (en) * 1985-03-28 1986-10-07
JPS6276504U (en) * 1985-11-01 1987-05-16
JPS6371524U (en) * 1986-10-28 1988-05-13

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61162036U (en) * 1985-03-28 1986-10-07
JPS6276504U (en) * 1985-11-01 1987-05-16
JPS6371524U (en) * 1986-10-28 1988-05-13

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003023259A (en) * 2001-07-10 2003-01-24 Hamamatsu Photonics Kk Laminate and its surface processing method
JP2008060214A (en) * 2006-08-30 2008-03-13 Murata Mfg Co Ltd Mounting structure of laminated ceramic electronic component
US20130063864A1 (en) * 2011-09-09 2013-03-14 Hon Hai Precision Industry Co., Ltd. Multi-layer ceramic electronic component with solder blocking layer
JP2015076591A (en) * 2013-10-11 2015-04-20 Tdk株式会社 Feedthrough capacitor
JP2020071923A (en) * 2018-10-29 2020-05-07 株式会社村田製作所 Electronic component

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