JPH04332131A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH04332131A JPH04332131A JP10227491A JP10227491A JPH04332131A JP H04332131 A JPH04332131 A JP H04332131A JP 10227491 A JP10227491 A JP 10227491A JP 10227491 A JP10227491 A JP 10227491A JP H04332131 A JPH04332131 A JP H04332131A
- Authority
- JP
- Japan
- Prior art keywords
- wiring
- uneven surface
- crystal
- crystalline
- angle formed
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 7
- 239000013078 crystal Substances 0.000 claims abstract description 35
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 15
- 239000002184 metal Substances 0.000 claims abstract description 10
- 229910052751 metal Inorganic materials 0.000 claims abstract description 10
- 229910052814 silicon oxide Inorganic materials 0.000 claims abstract description 7
- 239000000758 substrate Substances 0.000 claims abstract description 7
- 229910052681 coesite Inorganic materials 0.000 abstract description 4
- 229910052906 cristobalite Inorganic materials 0.000 abstract description 4
- 239000000377 silicon dioxide Substances 0.000 abstract description 4
- 235000012239 silicon dioxide Nutrition 0.000 abstract description 4
- 229910052682 stishovite Inorganic materials 0.000 abstract description 4
- 229910052905 tridymite Inorganic materials 0.000 abstract description 4
- 239000007787 solid Substances 0.000 abstract description 2
- 239000010408 film Substances 0.000 description 7
- 239000010409 thin film Substances 0.000 description 3
- 238000000034 method Methods 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 229910000838 Al alloy Inorganic materials 0.000 description 1
- 238000005275 alloying Methods 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000010894 electron beam technology Methods 0.000 description 1
- 230000003993 interaction Effects 0.000 description 1
- 230000001678 irradiating effect Effects 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【0001】0001
【産業上の利用分野】本発明は半導体装置に関し、特に
多結晶薄膜からなる配線の構造に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor devices, and more particularly to the structure of wiring made of polycrystalline thin films.
【0002】0002
【従来の技術】従来、半導体装置の微細配線として、絶
縁層上に多結晶薄膜を形成したのちパターニングする方
法が提案され試みられている。2. Description of the Related Art Hitherto, a method has been proposed and attempted in which a polycrystalline thin film is formed on an insulating layer and then patterned for fine wiring in a semiconductor device.
【0003】0003
【発明が解決しようとする課題】しかしながら、形成さ
れる配線直下の層が平板である場合、その上に形成した
多結晶薄膜の配線は、アイイーイーイー・インターナシ
ョナルリライアビリティフィジックスシンポジウム(I
EEE International Relia
bilty Physics Symposium
)(1986)会議録253頁にハートマン・ヒーバー
(HartmannHieber)らにより報告されて
いるように、配線直下の層に垂直な方向にその結晶粒の
ある方向が揃う傾向がある。しかし結晶粒間の相互作用
のために結晶粒の方向は完全には揃わないし、結晶粒界
が特定の結晶面になることもない。そのため従来の方法
で作製した、配線幅が結晶粒と同程度の大きさになった
配線は、引っ張りあるいは圧縮応力に関して降伏応力の
値が小さいため断線等を生ずるという欠点がある。[Problems to be Solved by the Invention] However, when the layer directly below the wiring to be formed is a flat plate, the polycrystalline thin film wiring formed thereon is
EEE International Relia
bilty physics symposium
) (1986), p. 253 of the conference proceedings, as reported by Hartmann Hieber et al., the direction of the crystal grains tends to be aligned in the direction perpendicular to the layer immediately below the wiring. However, due to the interaction between the crystal grains, the directions of the crystal grains are not perfectly aligned, and the grain boundaries do not become specific crystal planes. For this reason, wires manufactured by conventional methods, whose width is approximately the same size as crystal grains, have a drawback in that they have a small yield stress value with respect to tensile or compressive stress, resulting in wire breakage and the like.
【0004】0004
【課題を解決するための手段】本発明の半導体装置は、
半導体基板上に形成された酸化シリコン膜と、この酸化
シリコン膜の表面に形成され面と面のなす角が金属結晶
の結晶面のなす角と同一の角度を有する凹凸面と、この
凹凸面上に形成された金属結晶からなる配線とを含むも
のである。[Means for Solving the Problems] A semiconductor device of the present invention includes:
A silicon oxide film formed on a semiconductor substrate, an uneven surface formed on the surface of this silicon oxide film whose angle between the surfaces is the same as an angle formed by a crystal plane of a metal crystal, and a surface on this uneven surface. This includes wiring made of metal crystals formed in
【0005】[0005]
【作用】一般的な性質として、結晶粒のある特定の結晶
面の方向が、基板に垂直な方向になるので、基板に凹凸
がある場合には、凹凸のそれぞれの面に垂直に結晶粒の
ある結晶面の方向が向くことになる。この凹凸の大きさ
を結晶粒の大きさ程度にすれば、配線の幅が結晶粒の大
きさと同程度の場合、凹凸面の一つ一つに結晶粒が一個
だけ成長するようになる。この凹凸面と面とのなす角を
ある特定の結晶面と面とのなす角に一致させておけば、
その上に成長している結晶粒は、ある特定の結晶面で隣
接する結晶粒とくっつくことになる。[Operation] As a general property, the direction of a specific crystal plane of a crystal grain is perpendicular to the substrate, so if the substrate has unevenness, the direction of the crystal grain is perpendicular to each surface of the unevenness. The direction of a certain crystal plane will be oriented. If the size of this unevenness is made to be about the size of a crystal grain, only one crystal grain will grow on each uneven surface if the width of the wiring is about the same as the size of the crystal grain. If the angle between this uneven surface and the surface matches the angle between a certain crystal plane and the surface,
The crystal grains growing on it will stick together with neighboring crystal grains at certain crystal planes.
【0006】[0006]
【実施例】以下、本発明を図面を用いて説明する。図1
は本発明の一実施例の断面図である。DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be explained below with reference to the drawings. Figure 1
1 is a sectional view of one embodiment of the present invention.
【0007】熱酸化により厚さ約0.5μmのSiO2
膜2を形成したSi基板1上に、スパッタリング法に
よりA1配線1を形成した例について述べる。SiO2
膜2は凹凸面を有しており、この凹凸面の一つの面の
一辺の長さは1μmである。面と面とのなす角はAl結
晶粒の[111]結晶面のなす角の2倍である141.
058度にしてある。この凹凸は、幅1μmのパターン
を有するTa板をマスクとして1kWの電子ビームを斜
めに照射することにより形成する。次でスパッタリング
法でAlのべた膜を蒸着した後、ウェットまたはドライ
エッチング法によるAl配線のパターンニングと400
℃30分のアロイとを行うと、結晶粒が成長し、図2に
示されるような、Al配線1中の結晶粒4の結晶面の方
位関係が実現され、〔111)〕結晶面に関連した結晶
面で隣の結晶粒と接続される。従って結晶粒界の結合性
が強固なAl配線を形成することができる。[0007] SiO2 with a thickness of about 0.5 μm was formed by thermal oxidation.
An example will be described in which an A1 wiring 1 is formed by sputtering on a Si substrate 1 on which a film 2 is formed. SiO2
The film 2 has an uneven surface, and the length of one side of one of the uneven surfaces is 1 μm. The angle between the planes is twice the angle formed by the [111] crystal plane of the Al crystal grain, 141.
It is set to 058 degrees. The unevenness is formed by obliquely irradiating a 1 kW electron beam using a Ta plate having a pattern of 1 μm width as a mask. Next, after depositing a solid Al film by sputtering, patterning of Al wiring by wet or dry etching was performed.
When alloying is carried out for 30 minutes at ℃, the crystal grains grow, and the orientation relationship of the crystal planes of the crystal grains 4 in the Al wiring 1 is realized as shown in FIG. It is connected to neighboring crystal grains through the crystal planes. Therefore, an Al wiring with strong grain boundary bonding can be formed.
【0008】このように構成された本実施例によるAl
配線は、粒界が凹凸の谷または山に一致するようになり
、また、特定の結晶面で粒界が結合するようになる。
この方法を用いればAl配線の場合、500℃、100
時間程度のアニールにより従来例では切断したものが切
断しなくなった。[0008] The Al according to this embodiment configured as described above
In the wiring, the grain boundaries coincide with the valleys or peaks of the unevenness, and the grain boundaries combine at specific crystal planes. Using this method, in the case of Al wiring, 500°C, 100°C
After annealing for about an hour, the parts that were cut in the conventional example no longer cut.
【0009】尚、上記実施例においては、配線を形成す
る金属としてAlを用いた場合について説明したが、S
iやCuを含むAl合金やWを用いることができる。[0009] In the above embodiment, the case where Al was used as the metal forming the wiring was explained, but S
An Al alloy containing i and Cu or W can be used.
【0010】0010
【発明の効果】以上説明したように本発明によれば、配
線を構成する金属結晶の粒界が酸化シリコン膜表面の凹
凸の谷または山に一致するようになるため、断線の生じ
にくい結合性の強固な金属配線を有する半導体装置が得
られる。As explained above, according to the present invention, the grain boundaries of the metal crystals constituting the wiring coincide with the valleys or peaks of the unevenness on the surface of the silicon oxide film. A semiconductor device having strong metal wiring can be obtained.
【図1】本発明の一実施例を示す断面図。FIG. 1 is a sectional view showing one embodiment of the present invention.
【図2】Al配線中の結晶粒の方位関係を示す図。FIG. 2 is a diagram showing the orientation relationship of crystal grains in Al wiring.
1 Al配線 2 SiO2 膜 3 Si基板 4 Al結晶粒 1 Al wiring 2 SiO2 film 3 Si substrate 4 Al crystal grains
Claims (1)
ン膜と、この酸化シリコン膜の表面に形成され面と面の
なす角が金属結晶の結晶面のなす角と同一の角度を有す
る凹凸面と、この凹凸面上に形成された金属結晶からな
る配線とを含むことを特徴とする半導体装置。1. A silicon oxide film formed on a semiconductor substrate, and an uneven surface formed on the surface of the silicon oxide film, the angle between the surfaces being the same as the angle formed by the crystal plane of a metal crystal. , and wiring made of metal crystal formed on the uneven surface.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP10227491A JPH04332131A (en) | 1991-05-08 | 1991-05-08 | Semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP10227491A JPH04332131A (en) | 1991-05-08 | 1991-05-08 | Semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH04332131A true JPH04332131A (en) | 1992-11-19 |
Family
ID=14323027
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP10227491A Pending JPH04332131A (en) | 1991-05-08 | 1991-05-08 | Semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH04332131A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2006175582A (en) * | 2004-11-26 | 2006-07-06 | Fujikura Ltd | Nano-structure and manufacturing method thereof |
US8163084B2 (en) | 2004-11-26 | 2012-04-24 | Fujikura Ltd. | Nanostructure and manufacturing method for same |
WO2023085110A1 (en) * | 2021-11-10 | 2023-05-19 | 株式会社村田製作所 | Module |
-
1991
- 1991-05-08 JP JP10227491A patent/JPH04332131A/en active Pending
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2006175582A (en) * | 2004-11-26 | 2006-07-06 | Fujikura Ltd | Nano-structure and manufacturing method thereof |
US8163084B2 (en) | 2004-11-26 | 2012-04-24 | Fujikura Ltd. | Nanostructure and manufacturing method for same |
WO2023085110A1 (en) * | 2021-11-10 | 2023-05-19 | 株式会社村田製作所 | Module |
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