JPH02260456A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

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Publication number
JPH02260456A
JPH02260456A JP8032489A JP8032489A JPH02260456A JP H02260456 A JPH02260456 A JP H02260456A JP 8032489 A JP8032489 A JP 8032489A JP 8032489 A JP8032489 A JP 8032489A JP H02260456 A JPH02260456 A JP H02260456A
Authority
JP
Japan
Prior art keywords
film
silicon film
polycrystalline silicon
insulating film
mos transistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8032489A
Other languages
Japanese (ja)
Inventor
Atsuo Wada
敦夫 和田
Yutaka Ito
豊 伊藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP8032489A priority Critical patent/JPH02260456A/en
Publication of JPH02260456A publication Critical patent/JPH02260456A/en
Pending legal-status Critical Current

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  • Thin Film Transistor (AREA)
  • Recrystallisation Techniques (AREA)

Abstract

PURPOSE:To reduce the number of processes and to reduce an irregularity in an electric characteristic of a MOS transistor by a method wherein a second polycrystalline silicon film is recrystallized and transformed into a second silicon film, it is used as a gate electrode and a thermal SiO2 film at its substratum is used as a gate insulating film. CONSTITUTION:A second polycrystalline silicon film 5 is formed, via a thermal SiO2 film 4, on an island composed of a first polycrystalline silicon film 3 which has been formed on an insulating film 2. After that, the first polycrystalline silicon film and the second polycrystalline silicon film 3, 5 are irradiated with an energy beam 6, are recrystallized at the same time and are transformed into a first silicon film and a second silicon film 7, 8. one part of the second silicon film 8 is used as a gate electrode 9, and the thermal SiO2 film 4 is used as a gate insulating film 10. Thereby, it is possible to reduce the number of processes used to form a MOS transistor; in addition, it is possible to reduce an irregularity in a film thickness of the gate insulating film 10 and to reduce an irregularity in an electric characteristic.

Description

【発明の詳細な説明】 産業上の利用分野 本発明は半導体装置の製造方法に関するものである。[Detailed description of the invention] Industrial applications The present invention relates to a method of manufacturing a semiconductor device.

従来の技術 絶縁膜上に結晶性の良いシリコン膜を形成し、このシリ
コン膜に半導体装置を形成する従来の方法としては、例
えば第6回折機能素子技術シンポジウム予稿(1986
年)第216頁から第229頁に発表されている。
Conventional technology A conventional method of forming a silicon film with good crystallinity on an insulating film and forming a semiconductor device on this silicon film includes, for example, the 6th Diffraction Functional Element Technology Symposium Proceedings (1986
2013), pages 216 to 229.

第2図はこの従来の半導体装置の製造方法を示すもので
あり、13は半導体基板、14はcvn等により半導体
基板13の上に絶縁膜14上に、順に第1の多結晶シリ
コン膜16を0.6μs、5i02膜16を0.2μm
、第2の多結晶シリコン膜17をo、epm、最上層に
5i02膜18を0.26 plM設けた多層構造を形
成する(第2図a)。次にこの多層構造に対しレーザ光
19を照射し、前期筒1の多結晶シリコン膜16と第2
の多結晶シリコン膜21を形成する(第2図b)。この
再結晶化過程に於いて、第2図aの第1の多結晶シリコ
ン膜16は、第2の多結晶シリコン膜17からの熱伝導
により溶融する。この時第2の多結晶シリコ/膜17は
レーザ光のゆらぎに対する緩衝層とL2て働き、第1の
多結晶シリコン膜16へのレーザ光16のゆらぎの影響
を低減し、第1の多結晶シリコン膜16は安定度の高い
結晶成長が行なわれ、結晶性の良い第1のシリコン膜2
0を得ることができる。
FIG. 2 shows this conventional method for manufacturing a semiconductor device, in which 13 is a semiconductor substrate, and 14 is a first polycrystalline silicon film 16 which is sequentially formed on an insulating film 14 on the semiconductor substrate 13 using CVN or the like. 0.6μs, 5i02 film 16 0.2μm
A multilayer structure is formed in which the second polycrystalline silicon film 17 is o, epm, and the 5i02 film 18 is provided at the top layer at a thickness of 0.26 plM (FIG. 2a). Next, this multilayer structure is irradiated with a laser beam 19, and the polycrystalline silicon film 16 of the first cylinder 1 and the second
A polycrystalline silicon film 21 is formed (FIG. 2b). During this recrystallization process, the first polycrystalline silicon film 16 shown in FIG. 2a is melted by heat conduction from the second polycrystalline silicon film 17. At this time, the second polycrystalline silicon film 17 acts as a buffer layer L2 against the fluctuation of the laser beam, reduces the influence of the fluctuation of the laser beam 16 on the first polycrystalline silicon film 16, and The silicon film 16 undergoes highly stable crystal growth and is the first silicon film 2 with good crystallinity.
You can get 0.

以」二の再結晶化工程を終了した後、5i02膜16゜
第2のシリコン膜21.SiO2膜18を剥離する。
After completing the second recrystallization step, the 5i02 film 16° and the second silicon film 21. The SiO2 film 18 is peeled off.

表面に露出した第1のシリコン膜20を活性層とし、標
準的なMOSトランジスタの形成方法に従い、ゲート絶
縁膜22.ゲート電極23.ソース領域24.ドレイン
領域25を設け、絶縁膜14上にMOS)う/ジスタを
形成する。以上が従来のMOS型半導体装置の製造方法
である。
The first silicon film 20 exposed at the surface is used as an active layer, and a gate insulating film 22. Gate electrode 23. Source area 24. A drain region 25 is provided, and a MOS transistor is formed on the insulating film 14. The above is the conventional method for manufacturing a MOS type semiconductor device.

発明が解決しようとする課題 しかしながら上記のような製造方法では、MOSトラン
ジスタの活性層と成る第1のシリコン膜20を得る為に
、5102膜16.第2の多結晶Si膜21 、  f
si02膜18を形成する工程に加え逆にそれぞれの膜
を除去するという冗長な工程が必要となり、絶縁膜14
上へのMOS)ランジスタ形成に於ける一連の工程数を
極めて増大させてしまうという問題点を有していた。
Problems to be Solved by the Invention However, in the above manufacturing method, in order to obtain the first silicon film 20 that will become the active layer of the MOS transistor, the 5102 film 16. Second polycrystalline Si film 21, f
In addition to the process of forming the Si02 film 18, a redundant process of removing each film is required, and the insulating film 14
This method has the problem of significantly increasing the number of steps required to form a MOS transistor on top.

また、MOSトランジスタのゲート絶縁膜には、通常熱
5i02膜が用いられるが、第2図Cに於けるゲート絶
縁膜22を熱酸化の5i02膜で形成した場合、その膜
厚はゲート絶縁膜22直下領域に於ける第1のシリコン
膜20の面方位に依存する。
Furthermore, although a thermally oxidized 5i02 film is normally used for the gate insulating film of a MOS transistor, if the gate insulating film 22 in FIG. It depends on the plane orientation of the first silicon film 20 in the region immediately below.

一般に、第1のシリコン膜20表面の面方位は、場所に
よって異なる為、この面方位のバラツキに起因して同一
面上に形成した個々のMOSトランジスタのゲート絶縁
膜の膜厚にバラツキを生じさせる。その結果、個々のM
OS )ランジスタのしきい値等、電気特性にバラツキ
を引き起すという問題点を有していた。
Generally, the surface orientation of the first silicon film 20 varies depending on the location, and this variation in surface orientation causes variations in the thickness of the gate insulating film of each MOS transistor formed on the same surface. . As a result, individual M
OS) had the problem of causing variations in electrical characteristics such as the threshold voltage of transistors.

本発明はかかる点に鑑み、絶縁膜上に結晶性の良いシリ
コン膜を形成するという従来の技術の利点を保ちつつ、
絶縁膜上へのMOS )ランジスタ形成に於ける一連の
工程数を減少させること、さらに同一面上に形成した個
々の前記MO8)ランジスタのゲート絶縁膜の膜厚のバ
ラツキを低減させ、個々のMOSトランジスタの電気特
性のバラツキを低減させることの以上2点を備えた半導
体装置の製造方法を提供することを目的とする。
In view of this point, the present invention maintains the advantages of the conventional technology of forming a silicon film with good crystallinity on an insulating film, while
To reduce the number of steps in forming a MOS (MOS) transistor on an insulating film, and to reduce variations in the thickness of the gate insulating film of each MO8) transistor formed on the same surface. It is an object of the present invention to provide a method for manufacturing a semiconductor device that achieves the above two points of reducing variations in electrical characteristics of transistors.

課題を解決するための手段 本発明は上述の課題を解決する為、絶縁膜トに設けられ
た第1の多結晶シリコン膜よりなる島の上に熱5i02
膜を介して第2の多結晶シリコン膜を形成した後、エネ
ルギービーム照射によって第1及び第2の多結晶シリコ
ン膜を同時に再結晶化せしめて第1と第2のシリコン膜
と成し、第2のシリコン膜の一部をゲート電極に、前記
熱5102換をゲート絶縁膜として用いることにより絶
縁膜上にMOSトランジスタを形成する半導体装置の製
造方法を用いる。
Means for Solving the Problems In order to solve the above-mentioned problems, the present invention applies heat 5i02 to an island made of a first polycrystalline silicon film provided on an insulating film.
After forming a second polycrystalline silicon film through the film, the first and second polycrystalline silicon films are simultaneously recrystallized by energy beam irradiation to form first and second silicon films, and A method of manufacturing a semiconductor device is used in which a part of the silicon film No. 2 is used as a gate electrode and the heat 5102 is used as a gate insulating film to form a MOS transistor on the insulating film.

作用 本発明は前記した手段により、絶縁膜上の多結晶シリコ
ン膜の再結晶化工程に於いてレーザ光のゆらぎに対する
緩衝層としてのみ用いた第2の多結晶シリコン膜は、再
結晶化されて第2のシリコン膜となった後、ゲー 計電
極として利用(,2、さらにその下地の熱5io2膜を
ゲート絶縁膜として利用する為、従来例で示したごとく
、再結晶化工程後第2のシリコン膜21 、5in2膜
16及び18を除去した後、新たにゲート絶縁膜22及
びゲートを極23を形成する場合に比べ、絶縁膜上への
MOS )ランジスタ形成に於ける一連の工程数を著し
く減少させる。さらに前記した手段により、第1の多結
晶シリコン膜を被覆した熱5i02 Mは多結晶シリコ
ン膜表面を熱酸化して形成されるが、一般に多結晶シリ
コン膜は(111)面心(110)面をもっだ粒径0゜
03〜0.3μmの結晶粒が一様に分布して構成されて
いる為、その熱酸化膜の膜厚の面白バラツキは従来例で
示したように再結晶化した第1のシリコン膜20表面を
熱酸化して形成されるゲート絶縁膜22の膜厚のバラツ
キよりも低減され、前記第1の多結晶シリコン膜を熱酸
化して形成される熱5i02膜をゲート絶縁膜として用
いることにより、電気特性のバラツキの少ないMOS 
)ランジスタが絶縁膜上に形成される。
Effect of the present invention By using the above-described means, the second polycrystalline silicon film used only as a buffer layer against fluctuations of laser light in the recrystallization process of the polycrystalline silicon film on the insulating film is recrystallized. After forming the second silicon film, it is used as a gate electrode (2, and in order to further use the underlying thermal 5io2 film as a gate insulating film, as shown in the conventional example, the second silicon film is used after the recrystallization process. Compared to the case where a new gate insulating film 22 and gate electrode 23 are formed after removing the silicon film 21 and the 5in2 films 16 and 18, the number of steps in forming a MOS transistor on the insulating film is significantly reduced. reduce Furthermore, by the means described above, the heat 5i02 M that coats the first polycrystalline silicon film is formed by thermally oxidizing the surface of the polycrystalline silicon film, but generally polycrystalline silicon films are (111) face centered (110) face centered. Since it is composed of crystal grains with a grain size of 0.03 to 0.3 μm distributed uniformly, the variation in the thickness of the thermal oxide film is due to recrystallization as shown in the conventional example. The variation in the thickness of the gate insulating film 22 formed by thermally oxidizing the surface of the first silicon film 20 is reduced, and the thermal 5i02 film formed by thermally oxidizing the first polycrystalline silicon film is MOS with less variation in electrical characteristics by being used as an insulating film
) A transistor is formed on the insulating film.

実施例 第1図は本発明の一実施例における半導体装置の製造方
法を示したものである。第1図aに於いて1はシリコン
半導体基板であり、1層目の半導体素子が形成されてい
てもよい。2はCvD等により形成された8102等の
絶縁膜で1μmである。
Embodiment FIG. 1 shows a method of manufacturing a semiconductor device according to an embodiment of the present invention. In FIG. 1a, 1 is a silicon semiconductor substrate, on which a first layer of semiconductor elements may be formed. 2 is an insulating film such as 8102 formed by CvD or the like and has a thickness of 1 μm.

3は島状に加工された膜厚O,Sμmの多結晶シリコン
膜であり、P型の不純物が注入されである。
3 is a polycrystalline silicon film processed into an island shape with a film thickness of O.S.mu.m, into which P-type impurities are implanted.

次に多結晶シリコン膜3の表面を熱酸化し、膜厚0.0
3μ臘の熱酸化の8102膜4で被膜し、さらに多結晶
シリコン膜6をO,S2層の膜厚で堆積させ、多結晶シ
リコン膜3.熱酸化5102膜4.多結晶シリコン膜6
から成る多層構造を形成する(第2図b)。多結晶シリ
コン膜3は、(111)面及び(110)面をもった粒
径0.03〜0.3μ論の結晶が一様に分布して構成し
ているため、これを熱酸化して形成した熱5102膜4
の膜厚のウェハ面内バラツキは、再結晶化した単結晶シ
リコン表面を熱酸化した8i02膜に比べて少なく、良
質なものとなる。
Next, the surface of the polycrystalline silicon film 3 is thermally oxidized to have a film thickness of 0.0
A thermally oxidized 8102 film 4 of 3μ thick is coated, and a polycrystalline silicon film 6 is further deposited to a thickness of O and S2 layers to form a polycrystalline silicon film 3. Thermal oxidation 5102 film 4. Polycrystalline silicon film 6
(Fig. 2b). The polycrystalline silicon film 3 is composed of crystals having (111) planes and (110) planes with a grain size of 0.03 to 0.3 μm distributed uniformly, and is therefore thermally oxidized. Formed heat 5102 film 4
The variation in film thickness within the wafer surface is smaller than that of an 8i02 film formed by thermally oxidizing a recrystallized single crystal silicon surface, resulting in a high quality film.

この多層構造にレーザ光6を照射し、多結晶シリコン膜
3と多結晶シリコン膜6を同時に再結晶化する。この時
多結晶シリコン膜3は多結晶シリコン膜6からの熱伝導
により溶融するが、多結晶シリコン膜6がレーザ光6の
ゆらぎに対する緩衝層として働くため、多結晶シリコン
膜3は安定の高い結晶成長が行なわれる。以上の再結晶
化過程を経て、シリコン膜7及びシリコン膜8が形成さ
れる(第2図O)。以降、シリコン膜8.熱酸化8i(
)、膜4を選択的に除去し、シリコン膜7を活性層、シ
リコン膜8をゲート電極材料、熱酸化5102膜4をゲ
ート絶縁膜材料とし、標準的なNdのMOS)ランジス
タの形成方法に従い、ゲート絶縁膜10.ゲート電極9
.n+のソース領域11゜n のドレイン領域12を設
け、絶縁膜2上1cNchのMOS )ランジスタを形
成する(第2図d)。
This multilayer structure is irradiated with laser light 6 to simultaneously recrystallize polycrystalline silicon film 3 and polycrystalline silicon film 6. At this time, the polycrystalline silicon film 3 melts due to heat conduction from the polycrystalline silicon film 6, but since the polycrystalline silicon film 6 acts as a buffer layer against fluctuations in the laser beam 6, the polycrystalline silicon film 3 becomes a highly stable crystal. Growth takes place. Through the above recrystallization process, silicon film 7 and silicon film 8 are formed (FIG. 2O). Hereafter, silicon film 8. Thermal oxidation 8i (
), the film 4 is selectively removed, the silicon film 7 is used as an active layer, the silicon film 8 is used as a gate electrode material, and the thermally oxidized 5102 film 4 is used as a gate insulating film material, according to a standard Nd MOS transistor formation method. , gate insulating film 10. Gate electrode 9
.. An n+ source region 11°n and a drain region 12 are provided, and a 1 cNch MOS transistor is formed on the insulating film 2 (FIG. 2d).

以上のように本実施例によれば、レーザ光のゆらぎに対
する緩衝層として用いた多結晶シリコン膜3を再結晶化
したシリコン膜8をゲート電極材料に、さらkその下地
の熱酸化5io2膜4をゲート絶縁膜材料として利用す
るため、絶縁膜上へのMOS )ランジスタ形成に於い
て従来に比べその工程数を著しく減少させることができ
る。また、Si O2膜4は多結晶シリコン膜3を熱酸
化して形成しているため、多結晶シリコン膜3の結晶粒
の一様性より、熱酸化5i021[14の膜厚のウェハ
面内バラツキは従来よりも小さくなる。その結果、熱酸
化8i02膜4をゲート絶縁膜材料として用いた各MO
5)ランジスタのゲート容量のウェハ面内バラツキは従
来よりも低減化され、従来に比べ電気特性のバラツキの
少ないMOS )ランジスタを絶縁膜上に形成すること
ができる。
As described above, according to this embodiment, the silicon film 8 obtained by recrystallizing the polycrystalline silicon film 3 used as a buffer layer against fluctuations of laser light is used as the gate electrode material, and the thermally oxidized 5io2 film 4 underlying the silicon film 8 is used as the gate electrode material. Since MOS transistors are used as the gate insulating film material, the number of steps in forming a MOS transistor on the insulating film can be significantly reduced compared to the conventional method. In addition, since the SiO2 film 4 is formed by thermally oxidizing the polycrystalline silicon film 3, the uniformity of the crystal grains of the polycrystalline silicon film 3 may cause variations in the film thickness of the thermally oxidized film 5i021[14] within the wafer surface. is smaller than before. As a result, each MO using the thermally oxidized 8i02 film 4 as the gate insulating film material
5) Variation in the gate capacitance of transistors within the wafer surface is reduced compared to the conventional method, and a MOS transistor with less variation in electrical characteristics compared to the conventional method can be formed on an insulating film.

なお、第1図の実施例はNchのMOS )ランジスタ
の形成方法であるが、PchのMOS)ランジスタとし
てもよい。
Although the embodiment shown in FIG. 1 is a method for forming an Nch MOS transistor, a Pch MOS transistor may also be formed.

発明の詳細 な説明したように、本発明によれば、従来に比べ絶縁膜
上へのMOS)ランジスタ形成の工程数を著しく減少さ
せることができ、さらにゲート絶縁膜の膜厚のバラツキ
を低減することによシミ気特性のバラツキの小さいMO
S )ランジスタを絶縁膜上へ形成することができ、積
層構造の高性能の半導体装置の実現に大きく寄与するも
のであ。
As described in detail, according to the present invention, the number of steps for forming a MOS transistor on an insulating film can be significantly reduced compared to the conventional method, and variations in the thickness of the gate insulating film can be reduced. Especially MO with small variation in stain resistance properties.
S) A transistor can be formed on an insulating film, which greatly contributes to the realization of a high-performance semiconductor device with a stacked structure.

る。Ru.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の一実施例の半導体装置の製造方法を示
した図、第2図は従来の半導体装置の製造方法を示した
図である。 1・・・・・・半導体基板、2・・・・・・絶縁膜、3
・・・・・・多結晶シリコン族、4・・・・・・熱51
02膜、6・・曲多結晶シリコン膜、6・聞・レーザ光
、7・・・・・・シリコン膜、8・・・・・・シリコン
膜、9・・・・・・ゲート絶縁膜、10・・・・・・ゲ
ート電極、11・・・・・・ソース領域、12・・・・
・・ドレイン領域。 代理人の氏名 弁理士 粟 野 重 孝 #1が1名l
・−半S俸基板 2・・・$1!略票 s、s−4シ弧11警シゾコン暎 J112  囚 13・・−手4俸羞坂 /4−一絶痔侯 lこ17・・・、卆阿9翫シソコン瑣 /6./1h−3u)zFi$
FIG. 1 is a diagram showing a method for manufacturing a semiconductor device according to an embodiment of the present invention, and FIG. 2 is a diagram showing a conventional method for manufacturing a semiconductor device. 1... Semiconductor substrate, 2... Insulating film, 3
...Polycrystalline silicon family, 4...Heat 51
02 film, 6... curved polycrystalline silicon film, 6... laser light, 7... silicon film, 8... silicon film, 9... gate insulating film, 10... Gate electrode, 11... Source region, 12...
...Drain region. Name of agent: Patent attorney Shigetaka Awano #1 is one person
・-Half S salary board 2...$1! Abbreviation s, s-4 arc 11 police officer shizokon 挎J112 prisoner 13...-hand 4 yen saka/4-ichizetsu hemorrhoid hou lko 17..., book 9 kan shizokon dwarf/6. /1h-3u)zFi$

Claims (1)

【特許請求の範囲】[Claims] 半導体基板上に設けた絶縁膜上に、第1の多結晶シリコ
ン膜よりなる島を形成し、前記島の表面を所望の膜厚の
熱酸化膜で被覆し、前記熱酸化膜上に第2の多結晶シリ
コン膜を堆積させた後、エネルギービームにより、前記
第1及び第2の多結晶シリコン膜を同時に再結晶化せし
め第1のシリコン膜と第2のシリコン膜と成し、前記第
2のシリコン膜の一部領域をゲート電極とし、前記熱酸
化膜をゲート絶縁膜とし、前記第1のシリコン膜よりな
る島にソース領域、ドレイン領域を設けることにより、
前記絶縁膜上にMOSトランジスタを形成することを特
徴とする半導体装置の製造方法。
An island made of a first polycrystalline silicon film is formed on an insulating film provided on a semiconductor substrate, the surface of the island is covered with a thermal oxide film having a desired thickness, and a second polycrystalline silicon film is formed on the thermal oxide film. After depositing the polycrystalline silicon film, the first and second polycrystalline silicon films are simultaneously recrystallized by an energy beam to form a first silicon film and a second silicon film, and the second polycrystalline silicon film is deposited. By using a partial region of the silicon film as a gate electrode, using the thermal oxide film as a gate insulating film, and providing a source region and a drain region on the island made of the first silicon film,
A method of manufacturing a semiconductor device, comprising forming a MOS transistor on the insulating film.
JP8032489A 1989-03-30 1989-03-30 Manufacture of semiconductor device Pending JPH02260456A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8032489A JPH02260456A (en) 1989-03-30 1989-03-30 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8032489A JPH02260456A (en) 1989-03-30 1989-03-30 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPH02260456A true JPH02260456A (en) 1990-10-23

Family

ID=13715080

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8032489A Pending JPH02260456A (en) 1989-03-30 1989-03-30 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPH02260456A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007258234A (en) * 2006-03-20 2007-10-04 Nara Institute Of Science & Technology Semiconductor element, manufacturing method thereof thin film transistor, and laser annealing device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007258234A (en) * 2006-03-20 2007-10-04 Nara Institute Of Science & Technology Semiconductor element, manufacturing method thereof thin film transistor, and laser annealing device

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