JPS58171852A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS58171852A JPS58171852A JP5379882A JP5379882A JPS58171852A JP S58171852 A JPS58171852 A JP S58171852A JP 5379882 A JP5379882 A JP 5379882A JP 5379882 A JP5379882 A JP 5379882A JP S58171852 A JPS58171852 A JP S58171852A
- Authority
- JP
- Japan
- Prior art keywords
- electrode
- oxidized
- thickness
- coated
- easier
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title description 3
- 238000004519 manufacturing process Methods 0.000 title description 2
- 238000000034 method Methods 0.000 claims abstract description 7
- 230000015572 biosynthetic process Effects 0.000 claims 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims 1
- 229910052721 tungsten Inorganic materials 0.000 claims 1
- 239000010937 tungsten Substances 0.000 claims 1
- 239000000463 material Substances 0.000 abstract description 8
- 230000003647 oxidation Effects 0.000 abstract description 4
- 238000007254 oxidation reaction Methods 0.000 abstract description 4
- 230000010354 integration Effects 0.000 abstract description 2
- 150000002500 ions Chemical class 0.000 abstract description 2
- 238000010438 heat treatment Methods 0.000 description 5
- 235000012431 wafers Nutrition 0.000 description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- XEEYBQQBJWHFJM-UHFFFAOYSA-N Iron Chemical compound [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 description 2
- 239000010410 layer Substances 0.000 description 2
- 239000002253 acid Substances 0.000 description 1
- 235000021028 berry Nutrition 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 230000005465 channeling Effects 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 229910052742 iron Inorganic materials 0.000 description 1
- 230000015654 memory Effects 0.000 description 1
- 238000001420 photoelectron spectroscopy Methods 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 229910052723 transition metal Inorganic materials 0.000 description 1
- 150000003624 transition metals Chemical class 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/495—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a simple metal, e.g. W, Mo
- H01L29/4958—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a simple metal, e.g. W, Mo with a multiple layer structure
Abstract
Description
【発明の詳細な説明】
本発明は、従来のポリ３ｔ（多結晶シリコン）に比し抵
抗が非常に低い電極、配線材料を用いた半導体装置の製
造方法に係シ、特に、電極、配線材料の耐酸化性を向上
させる方法に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device using an electrode and wiring material that has extremely low resistance compared to conventional poly 3T (polycrystalline silicon), and in particular, to The present invention relates to a method for improving the oxidation resistance of.
従来、ＭＯ８メモリ等の半導体装置の電極、配線材料と
しては、主として、ボＩＪ ８ ｉが用いられてきた。Conventionally, IJ 8 i has been mainly used as an electrode and wiring material for semiconductor devices such as MO8 memories.
ところが、その比抵抗が１０８＃Ω・備もらって高いこ
とから、高集積比と高速化が困−となってき九。However, its high specific resistance of 108 #Ω has made it difficult to achieve a high integration ratio and high speed.
ポリＳｉよシ比抵抗が低い材料としてｗｔ−ｆうと色、
Ｗは酸化しやすいので、ポリＳｉプロセスとの互換性が
ない。本発明の目的はＷの耐酸化性を向上させることで
ある。As a material with lower resistivity than poly-Si, wt-F and color are used.
Since W is easily oxidized, it is not compatible with poly-Si processes. An object of the present invention is to improve the oxidation resistance of W.
・ 電極、配線材料として、比抵抗が低いＷを用い、
その表面をＷよシ酸化しやすい材料（たとえばｃｒ＃ｖ
ｌｓｉ、Ａｚ＃Ｎｂ＃’ｒａ＃’ｒ：、ｚｒｌＨｆ＃
Ｌ、１１１ Ｔｈ＃ Ｕｓ Ｃｅ１ｌ Ｙ＃ ８Ｃ＃
Ｅｒなど）で被虐する。その厚さとしては、単分子層チ
それ以上必要である。これによ、？Ｗが保護される化の
部分（もし全部酸化されていなければ）によりＷを保護
する。・Using W with low resistivity as the electrode and wiring material,
The surface is made of materials that are more easily oxidized than W (for example, cr#v
lsi,Az#Nb#'ra#'r:,zrlHf#
L, 111 Th# Us Ce1l Y# 8C#
(Er, etc.) The thickness needs to be equal to or greater than a monolayer. What about this? W is protected by the oxidized portion (if not all oxidized).
実施例１
熱酸化したＳｉウェーハ上に厚さ０．３μｍのＷを蒸層
し、その上に前記の元素（ｃｒｅｖｅｓｔ冨
弄）をスパッタ法によシ厚さ１０−１〜数１Ｏｆ１ｍ程
度蒸着した。これらのウェーハを１〜１００９ｐｍのＯ
ｓ （やＨ２Ｏ）を不純物として含む雰囲気中で子層
以下の場合には保鏝効果は不十分であった。Example 1 W was deposited to a thickness of 0.3 μm on a thermally oxidized Si wafer, and the above element (crevest concentration) was deposited thereon to a thickness of about 10−1 to several 10 μm by sputtering. . These wafers were exposed to 1-1009 pm O
In an atmosphere containing s (or H2O) as an impurity, the protective effect was insufficient in the case of a sublayer or lower.
実施例２
熱酸化したＳｉウェーハに厚さα３μｍのＷを蒸着し、
それを数ｐｐｍの０雪を含むＮ１−中で加熱するとき、
Ｗ表面から約５鱈離して、ふつ酸洗浄で酸化膜を除去し
たばかりの３ｉウエーノ・を設置しておいた。このよう
にして１００ＱＣ３０ｍｉｎ。Example 2 W was deposited to a thickness of α3 μm on a thermally oxidized Si wafer,
When it is heated in N1 containing several ppm of 0 snow,
A 3i ueno was placed about 5 mm away from the W surface, the oxide film of which had just been removed by acid cleaning. In this way, 100QC30min.
熱処理を施しても、Ｗ（Ｄ＠化は認められなかつ友（Ｘ
線光電子分光で）、一方、ふつ酸洗浄したＳｉウェーハ
を用いない場合には、Ｗが酸化され九（Ｘｍ光電子分光
で）。Even after heat treatment, W(D@ conversion was not observed and no (X
On the other hand, when the acid-cleaned Si wafer is not used, W is oxidized (by Xm photoelectron spectroscopy).
実施例３
通常のプロセスによシ、第１図に示すようなＭＯ８構造
を形成した。８ｉ０１１の上に厚さ４０ｎｍｏ８ｉ２と
厚さ０．３ａｍのＷ３からなるゲート電極を形成し九。Example 3 A MO8 structure as shown in FIG. 1 was formed using a conventional process. A gate electrode made of 8i2 with a thickness of 40 nm and W3 with a thickness of 0.3 am was formed on the 8i011.
この電極をマスクにして８０ヤネリングによシ正常な素
子特性が得られなかったが、本例のＭＯ８）ランジスノ
では正常な特性が得られた。なお、Ｓｉを被虐して加熱
しても、Ｗの抵抗の増大は認められず、約１Ω／口以上
のシート抵抗が得られた。Although normal device characteristics could not be obtained by 80 layer ringing using this electrode as a mask, normal device characteristics were obtained by MO8) Ranjisno in this example. Note that even when Si was subjected to heat treatment, no increase in the resistance of W was observed, and a sheet resistance of about 1 Ω/hole or more was obtained.
以上、ＷＩ！極、配線の耐酸化性を向上させる方法につ
いて説明した。夷画例３を除いてはウェーハ全面に蒸着
されたものを熱処理したが、電極、配線形成後の熱処理
でも幼果があった（実施例３）。That’s it, WI! A method for improving the oxidation resistance of electrodes and wiring has been explained. Except for Example 3, the wafer was deposited on the entire surface and then heat-treated, but even after the heat treatment after forming the electrodes and wiring, there were some small berries (Example 3).
この場合には、電極、配線形成後にＳｉのような元素を
ごく薄く（約５ｎｍ）化学蒸着すると、電極、配線の表
面だけでなく、側面も保護できるのでなおよい。このＳ
ｉｄ熱処理中にすべて酸化物になるので、短絡の心配は
ない。In this case, it is better to chemically vapor deposit an element such as Si in a very thin layer (approximately 5 nm) after forming the electrodes and wiring, since this can protect not only the surfaces of the electrodes and wiring but also the side surfaces. This S
Since it all becomes oxide during the id heat treatment, there is no need to worry about short circuits.
被虐する元素の結晶構造や原子の大きさがＷとは異なる
ときには、この電極をイオン打込時のマが酸化されて、
それが非晶質であれば、チャネリング阻止能はさらＫよ
くなる（例えば、ｓ”Ｏｓ＞。When the crystal structure and atomic size of the element to be attacked are different from that of W, the iron during ion implantation of this electrode may be oxidized.
If it is amorphous, the channeling blocking ability will be even better (eg, s”Os>.
また、ＷはＭＯのような他の遷移金属よシ耐熱性があり
、ｓ：＋ｓｉｏ、とも反応しにくいので、加熱処理によ
る素子特性の劣化も少ない。Further, since W has higher heat resistance than other transition metals such as MO and is less likely to react with s:+sio, there is less deterioration of device characteristics due to heat treatment.
・・・Ｗ、 ４・・・ｓｉ、ｓ・・・イオン打込与され
るＡＩイオン。
第１頁の続き
所内
研究所内
■出 願 人 日本電信電話公社...W, 4...si, s...AI ions to be implanted. Continued from page 1 Inside the laboratory ■Applicant Nippon Telegraph and Telephone Public Corporation
Claims (1)
上で、その酸化物生成エネルギーがＷの法。A method in which the thickness of a monomolecular layer or more is formed on the surface of W (tungsten), and the oxide formation energy is W.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5379882A JPS58171852A (en) | 1982-04-02 | 1982-04-02 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5379882A JPS58171852A (en) | 1982-04-02 | 1982-04-02 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS58171852A true JPS58171852A (en) | 1983-10-08 |
Family
ID=12952829
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5379882A Pending JPS58171852A (en) | 1982-04-02 | 1982-04-02 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58171852A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2621738A1 (en) * | 1987-10-08 | 1989-04-14 | Mingam Herve | ISOLATED METALLIC GRID FIELD EFFECT TRANSISTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5156181A (en) * | 1974-11-13 | 1976-05-17 | Tokyo Shibaura Electric Co | ZETSUENGEETOGATADENKAIKOKATORANJISUTANO SEIZOHOHO |
-
1982
- 1982-04-02 JP JP5379882A patent/JPS58171852A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5156181A (en) * | 1974-11-13 | 1976-05-17 | Tokyo Shibaura Electric Co | ZETSUENGEETOGATADENKAIKOKATORANJISUTANO SEIZOHOHO |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2621738A1 (en) * | 1987-10-08 | 1989-04-14 | Mingam Herve | ISOLATED METALLIC GRID FIELD EFFECT TRANSISTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME |
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