JPH10223559A - Manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method for manufacturing a semiconductor device, wherein the reaction of conversion from C49 titanium/silicide into C54 titanium/silicide is readily promoted, even when the width and the thickness of an electrode is reduced. SOLUTION: A titanium layer is formed on a gate electrode 4G, a source region 6 and a drain region 7, followed by a heat treatment to form C49 titanium/silicide layers 4S1 , 6S1 and 7S1 . Subsequently, ion implantation is executed on the C49 titanium/silicide layers 4S1 , 6S1 and 7S1 with an energy which is insufficient to reach the gate electrode 4G, the source region 6 or the drain region 7 to introduce defects therein. Then, by performing heat treatment, the C49 titanium/silicide layers 4S1 , 6S1 and 7S1 are converted into C54 titanium/ silicide layers 4S2 , 6S2 and 7S2 .

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method of manufacturing a semiconductor device including a step of forming a low-resistance titanium silicide layer on a silicon substrate or a polycrystalline silicon layer.

In general, as semiconductor devices such as integrated circuits become more sophisticated, low-resistance electrodes are required, and titanium silicide electrodes have been developed in order to deal with this.
The disadvantages of the conventional method of manufacturing it have to be solved.

[0003]

2. Description of the Related Art Conventionally, a technique for forming a silicide electrode using titanium is known as a technique for forming a low-resistance electrode. However, as the degree of integration of an integrated circuit increases, the electrode dimensions become smaller and the source becomes smaller. The width of the electrode and drain electrode is 1
[Μm] or less, and with the miniaturization of integrated circuit patterns, the diffusion of impurities has become extremely shallow.

In order to improve the performance of an integrated circuit, the resistivity of the electrode must be maintained at the same level as that of the prior art with respect to the above-mentioned fine dimension and shallow impurity diffusion layer.

As described above, when the impurity diffusion layer becomes shallower, the silicide layer becomes thinner as the impurity diffusion layer becomes shallower. Therefore, the reduction in the width and the thickness of the electrode contributes to the increase in the resistivity of the silicide electrode. I have.

Normally, a titanium silicide electrode has C4
It is known that when the structural phase transition from the 9 crystal structure to the C54 crystal structure has a high resistance, the resistance decreases, but the structural phase transition is hindered by the reduction in the width and thickness of the electrode. .

The main reason is that the grain boundary region is reduced when the grain size of the titanium silicide having the C49 crystal structure is large, and the generation of nuclei in the titanium silicide having the C54 crystal structure which is considered to be generated from the grain boundary region. It is understood that the frequency is reduced.

It is known that in order to promote the phase transition from the C49 crystal structure to the C54 crystal structure in titanium silicide, a stress is applied to the titanium silicide layer so as to apply compressive strain (if necessary, "Japanese Patent Laid-Open No. 8-139
No. 056).

In the invention disclosed in the above publication, a material film having a smaller thermal expansion coefficient than that of the substrate is deposited on the back surface of the substrate to apply stress to the substrate, and the whole is heated to warp the substrate. Is occurring.

[0010]

As means for promoting the phase transition from the C49 crystal structure to the C54 crystal structure in titanium silicide, according to the invention disclosed in the above-mentioned publication, compared with a normal process, Since a step of forming a film on the back surface of the substrate and a step of removing the formed film are required, an increase in the number of steps is inevitable.

In particular, when removing the film from the back surface of the substrate, it is necessary to perform processing so as not to damage the source, drain and gate portions formed on the surface of the substrate, and a complicated operation is required. No doubt.

Usually, since the back surface of the substrate is polished on the substrate after the wiring process, each element portion on the surface of the substrate is covered with a cover film, and there is almost no damage. In the invention disclosed in the above-mentioned publication, although not specified, in order to grind the back surface, it is necessary to cover the front surface with a cover film, remove it again, remove it, and then continue the remaining processes such as a wiring process. .

Although the above-mentioned process can be performed at a laboratory level, it is not feasible to implement the process on an actual production line.

As described above, the problem of lowering the resistivity of the titanium silicide electrode has not been solved yet. When the width or thickness of the electrode is reduced, it is still difficult to promote the phase transition of the crystal structure. Have difficulty.

The present invention makes it easy to promote the reaction from C49 titanium silicide to C54 titanium silicide even when the width and thickness of the electrode are reduced.

[0016]

SUMMARY OF THE INVENTION Generally, C49 titanium
The main reason that the structural phase transition from silicide to C54 titanium silicide is difficult to occur is that the grain size of C49 titanium silicide is large, the grain boundary region is reduced, and nucleation of C54 titanium silicide generated from the grain boundary region. It has already been mentioned that the frequency is reduced.

It is known that nuclei of C54 titanium silicide occur at a large frequency at the grain boundary of polycrystalline C49 titanium silicide, particularly at the triple point of the grain boundary where three crystal grains are close to each other. .

When a titanium layer is formed on silicon whose crystallinity is maintained up to the surface, the titanium layer is influenced by the crystal structure of the silicon surface and tends to be a crystal having a uniform crystal orientation. Since the constants are different, a single crystal cannot be obtained by complete epitaxial growth, but the crystal grain size of the titanium layer should be large.

In the present invention, it is fundamental that ions are implanted into the C49 titanium silicide layer at an acceleration energy that does not reach the silicon substrate to give defects to the C49 titanium silicide layer.

In such a case, the crystallinity of the C49 titanium silicide layer is disturbed, and the grain size of the C49 titanium silicide layer becomes small, so that the region of the grain boundary becomes relatively large as compared with the crystal region. .

Therefore, the C49 titanium silicide contains C
54 Titanium silicide nucleation frequency increased, C49
The structural phase transition from titanium silicide to C54 titanium silicide is likely to occur.

As a result, it is possible to reduce the resistance of titanium silicide under the miniaturized dimensions.

The ion implantation method applied in the present invention is an ordinary ion implantation method, a technique widely used in the field of semiconductors, and there is no problem in its application in the process. Further, it is clear that the sheet resistance is simpler than that of a known technique in which a compressive strain is applied to a titanium silicide layer, and the sheet resistance can be made substantially the same.

As described above, in the method of manufacturing a semiconductor device according to the present invention, (1) a titanium layer (eg, titanium layer 9) is formed on silicon (eg, gate electrode 4G, source region 6, drain region 7, etc.). ) And then heat-treated to form a C49 titanium silicide layer (for example, C49 titanium silicide layer 4).
S ₁ , 6S ₁ , 7S _1, etc.), and then C49 titanium.
Implanting ions into the silicide layer to introduce defects, and then heating to remove the C49 titanium silicide layer
Forming a titanium 54 silicide layer (for example, C54 titanium silicide layer 4S ₂ , 6S ₂ , 7S _2, etc.), or

(2) The method according to (1), wherein a C49 titanium silicide layer is formed on silicon and ions are implanted without removing an unreacted titanium layer.

(3) The method according to (1), wherein a C49 titanium silicide layer is formed on silicon to remove an unreacted titanium layer and then implant ions.

(4) In the above (2), when the ion species is T
or any one selected from i, Ge, Si, As, Ar, or

(5) In the above (3), the ion species is G
e, any one selected from Si, As, and Ar, or

(6) The method according to any one of (1) to (5), wherein ions are implanted after forming a TiN film on the C49 titanium silicide layer.

By adopting the above-mentioned means, even when the width and thickness of the electrode are reduced, it is easy to promote the reaction from C49 titanium silicide to C54 titanium silicide. With the size and the shallow impurity diffusion layer, the resistivity of the electrode in an integrated circuit with high performance can be maintained at the same level as the conventional one.

[0031]

FIG. 1 to FIG. 4 are cutaway side views showing a main part of a semiconductor device in a process step for explaining a first embodiment of the present invention, and FIG. FIG. 4 is a diagram showing a Ge distribution profile when Ge ions are implanted into a C49 titanium silicide layer, and will be described below with reference to these drawings.

FIG. 1 (A) 1- (1) Local oxidation of s
By applying the ilicon (LOCOS) method,
In the field of the p-Si substrate 1, the thickness is, for example, 250 [n].
m] of the insulating film 2 made of SiO ₂ .

1- (2) Si ₃ used for covering the active region when performing selective oxidation
After removing the oxidation-resistant mask film such as N _4, by applying a thermal oxidation method, the thickness of the S
A gate insulating film 3 made of iO ₂ is formed.

1- (3) Chemical vapor deposition
By applying the position (CVD) method,
For example, phosphorus (P) is added to 10 ²⁰ [cm ⁻³ ] or more, for example, 1 × 10
Containing about ²¹ [cm ^-3 ] and having a thickness of, for example, 180
An impurity-containing polycrystalline Si film 4 of [nm] is formed.

1- (4) Impurity-containing polycrystalline Si
The surface of the film 4 is oxidized to a thickness of, for example, 50 nm
An insulating film 5 made of O ₂ is formed.

Referring to FIG. 1B, 1- (5) A resist film having a gate electrode pattern is formed by applying a resist process in the lithography technique.

1- (6) Reactive ion etching (reactive ion)
By applying the etching (RIE) method,
S using a resist film having a gate electrode pattern as a mask
The insulating film 5 made of iO ₂ and the polycrystalline Si film 4 are etched to form a gate electrode 4G.

1- (7) With the resist film having the gate electrode pattern left as it is, by applying the ion implantation method, the acceleration energy is set to, for example, 40 keV and the dose is set to, for example, 2 × 10
As ions are implanted at ¹⁵ [cm ^-2 ].

1- (8) Impurity activation heat treatment at a temperature of, for example, 850 ° C. and a time of, for example, 10 [minutes] is performed to form an n ⁺ source region 6 and an n ⁺ drain region 7.

Referring to FIG. 2A, 2- (1) a thickness of, for example, 2
An insulating film 8 made of 00 [nm] SiO ₂ is formed.

Referring to FIG. 2B, 2- (2) anisotropic etching of the insulating film 8 is performed by applying the RIE method to form a side wall 8S covering the side surfaces of the insulating film 5 and the gate electrode 4G. Form. The etching technique applied here is not limited to the RIE method, and may be, for example, a sputtering method.
An etching method may be used.

3 (A) 3- (1) After the surface is cleaned by performing an acid treatment, it is immersed in an etching solution composed of diluted hydrofluoric acid to form an insulating film 5 on the gate electrode 4G.
The insulating film 3 on the source region 6 and the drain region 7 is removed.

3- (2) The thickness is, for example, 20 by applying the vacuum evaporation method.
The titanium layer 9 of [nm] is formed. Note that the film formation method applied here may be a sputtering method other than the vacuum evaporation method.

FIG. 3 (B) 3- (3) In a nitrogen atmosphere, the temperature is set to 400 [° C.]-700.
[° C.], for example, 600 ° C., and heat treatment for 30 seconds is performed, and a high-resistance C49 titanium silicide layer 4S ₁ , 6S ₁ , 7S is formed on each surface of the gate electrode 4G, the source region 6, and the drain region 7. ₁ is generated.

3- (4) The unreacted titanium layer 9 is removed by a usual acid treatment, for example, immersion in an acid solution of ammonia water: hydrogen peroxide solution: water = 1: 1: 2.

FIG. 4A 4- (1) By applying the ion implantation method, the ion acceleration energy is set to, for example, 60 keV and the dose is set to, for example, 5 × 1.
0 ¹⁴ [cm ^-2 ], C49 titanium silicide layer 4S
_1, and the implantation of Ge to 6S _1, 7S _1.

Defects are given to the C49 titanium silicide layers 4S ₁ , 6S ₁ , and 7S ₁ by the implantation of Ge, so that the crystallinity is disturbed and the crystal grain size is reduced.
Grain boundaries, which are the sources of 54 titanium silicide nuclei, increase.

In this case, Ge ion implantation is performed as follows.
It is important to prevent e from reaching the gate electrode 4G, the source region 6, and the drain region 7. In this embodiment, when ion implantation is performed under the above conditions, it can be seen in FIG. It becomes such a profile. The horizontal axis in FIG. 5 is the depth in the substrate direction with 0 as the surface, and the vertical axis shows the number of ions.

4 (B) 4- (2) In an argon atmosphere, the temperature was set between 600 ° C. and 90 ° C.
0 [° C], for example, 700 [° C], time 30 [seconds]
Is performed to cause a structural phase transition of the high-resistance C49 titanium silicide layers 4S ₁ , 6S ₁ , and 7S _1, and to form low-resistance C54 titanium silicide layers 4S ₂ , 6S ₂ ,
And 7S _2.

4- (3) After that, by applying the ordinary technique, the entire PS
Forming a G (phosphosilicate glass) film, forming an electrode contact window, forming an aluminum wiring, forming a protective film made of PSG, forming an opening for a bonding pad, etc.
The transistor is completed.

In the above-described embodiment, the thickness of the titanium layer 9 is set to 20 [nm]. However, an appropriate thickness may be selected according to the required thickness of the titanium silicide layer.

The present invention is not limited to the above embodiment,
Many other modifications can be implemented.

In the above embodiment, in the step 3- (4), the ion implantation is performed after the unreacted titanium layer 9 is removed. This is because there is no possibility that titanium of the above will be mixed into the C49 titanium silicide layer.

However, the ion implantation may be performed without removing the unreacted titanium layer 9. In such a case, the unreacted titanium layer becomes a barrier, and the contamination of impurities can be prevented. However, unreacted titanium that has been subjected to ion collisions is mixed into the C49 titanium silicide layer,
The composition may be changed.

In the above-described embodiment, Ge is implanted into the C49 titanium silicide layer. However, Ge can be replaced with, for example, Ti, Si, As, or Ar. C49 titanium silicide layer
There is an advantage that the reaction at the time of forming a titanium 54 silicide layer is not affected, and it is preferable to select an ion species as needed.

In the case where a means for implanting ions after removing the unreacted titanium layer is employed, if Ti is used as the implanted ions, the composition of the C49 titanium silicide layer changes. If not, T
It is better to avoid using i.

In the heat treatment step after ion implantation, titanium
If the surface of the silicide layer is likely to be oxidized, it is effective to form a TiN film having a thickness of, for example, 30 [nm] by applying a sputtering method, for example, before ion implantation.

[0058]

In the method of manufacturing a semiconductor device according to the present invention, a titanium layer is formed on silicon and then heat-treated to form a C49 titanium silicide layer. Ions are implanted into the silicide layer to introduce defects, and heated to C49 titanium.
The silicide layer is a C54 titanium silicide layer.

By adopting the above means, even when the width and thickness of the electrode are reduced, it is easy to promote the reaction from C49 titanium silicide to C54 titanium silicide. With the size and the shallow impurity diffusion layer, the resistivity of the electrode in an integrated circuit with high performance can be maintained at the same level as the conventional one.

[Brief description of the drawings]

FIG. 1 is a cutaway side view showing a main part of a semiconductor device in a process key point for explaining a first embodiment of the present invention;

FIG. 2 is a fragmentary side view showing a semiconductor device at a key step for explaining the first embodiment of the present invention;

FIG. 3 is a fragmentary sectional side view showing a semiconductor device in a process essential point for explaining the first embodiment of the present invention;

FIG. 4 is a fragmentary side view showing a semiconductor device at a key point in the process for describing Embodiment 1 of the present invention;

FIG. 5 is a diagram showing a Ge distribution profile when Ge ions are implanted into a C49 titanium silicide layer.

[Explanation of symbols]

Reference Signs List 1 p-Si substrate 2 insulating film 3 gate insulating film 4 polycrystalline Si film containing impurities 4 G gate electrode 4 S ₁ C49 titanium silicide layer 4 S ₂ C54 titanium silicide layer 5 insulating film 6 n ⁺ source region 6 S ₁ C49 titanium silicide Layer 6S ₂ C54 titanium silicide layer 7 n ⁺ drain region 7S ₁ C49 titanium silicide layer 7S ₂ C54 titanium silicide layer 8 Insulating film 8S Side wall

Claims (6)

[Claims] A step of forming a titanium layer on silicon and then performing a heat treatment to form a C49 titanium silicide layer; and then implanting ions into the C49 titanium silicide layer with energy that does not reach the silicon. Introducing a defect, and then heating the C49 titanium silicide layer to C54
Forming a titanium silicide layer. 2. The method of manufacturing a semiconductor device according to claim 1, wherein a C49 titanium silicide layer is formed on silicon and ions are implanted without removing an unreacted titanium layer. 3. The method of manufacturing a semiconductor device according to claim 1, wherein a C49 titanium silicide layer is formed on silicon to remove an unreacted titanium layer and then implant ions. 4. The method according to claim 1, wherein the ion species is Ti, Ge, Si, As, Ar.
3. The method according to claim 2, wherein the selected one is selected from the group consisting of:
The manufacturing method of the semiconductor device described in the above. 5. The method according to claim 3, wherein the ion species is any one selected from Ge, Si, As, and Ar. 6. The method of manufacturing a semiconductor device according to claim 1, wherein a TiN film is formed on the C49 titanium silicide layer and then ions are implanted.