JPS59111321A - Compound semiconductor thin-film structure and its manufacture - Google Patents

Compound semiconductor thin-film structure and its manufacture

Info

Publication number
JPS59111321A
JPS59111321A JP57221282A JP22128282A JPS59111321A JP S59111321 A JPS59111321 A JP S59111321A JP 57221282 A JP57221282 A JP 57221282A JP 22128282 A JP22128282 A JP 22128282A JP S59111321 A JPS59111321 A JP S59111321A
Authority
JP
Japan
Prior art keywords
compound semiconductor
semiconductor thin
thin film
substrate
film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP57221282A
Other languages
Japanese (ja)
Inventor
Keiji Kuboyama
久保山 啓治
Takeki Matsui
雄毅 松居
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Asahi Kasei Corp
Asahi Chemical Industry Co Ltd
Original Assignee
Asahi Chemical Industry Co Ltd
Asahi Kasei Kogyo KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Asahi Chemical Industry Co Ltd, Asahi Kasei Kogyo KK filed Critical Asahi Chemical Industry Co Ltd
Priority to JP57221282A priority Critical patent/JPS59111321A/en
Publication of JPS59111321A publication Critical patent/JPS59111321A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • H01L21/2003Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy characterised by the substrate
    • H01L21/2007Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Formation Of Insulating Films (AREA)
  • Hall/Mr Elements (AREA)

Abstract

PURPOSE:To improve reliability and heat-resisting property, and to process elements of various forms by laminating a compound semiconductor thin-film on a substrate through an adhesive resin layer and a glass layer, a thermal expansion coefficient thereof at the normal temperature is kept within a specific range. CONSTITUTION:The titled structure is manufactured by executing a process in which the compound semiconductor thin-film is grown on the substrate for growing a crystal of a selectively removable compound semiconductor, a process in which the glass layer, the thermal expansion coefficient thereof at the normal temperature is kpt within a range of 30X10<-7>/K-70X10<-7>/K, is formed on the compound semiconductor thin-film, a process in which the glass layer is bonded with a base body by an adhesive resin and a process in which the substrate for growing the crystal of the compound semiconductor is removed selectively. A substrate, through which the crystal of the compound semiconductor thin-film is grown excellently and the compound semiconductor thin-film is not attached strongly or the compound semiconductor thin- film is dissolved in a solution, into which the thin-film is not dissolved, and which is crystallized, is preferable as the substrate for growing the crystal of the selectively removable compound semiconductor, and mica, etc. are cited. A substance such as GaP, particularly, one of the low melting point, is effective as the compound semiconductor.

Description

【発明の詳細な説明】 本発明は信頼性の高い化合物半導体薄膜構造体及びその
製造方法に関するものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a highly reliable compound semiconductor thin film structure and a method for manufacturing the same.

従来、化合物半導体薄膜構造体を製造する方法としては
、大別して以下に示す3方法が知られている。すなわち
、まず第一の方法として、Orドープの半絶縁性GaA
sやサファイアなどの結晶性に優れ、しかも操作性の良
好な基板上に蒸着J?FMBKやOVDなどにより化合
物半導体薄膜を形成して構造体とする方法である。しか
しながら、この方法は化合物半導体薄膜を形成する直前
にしばしばはん雑な表面処理を必要とする上に、格子定
数を整合させるために基板の種類が限定され、しかもこ
の種の基板は往々にして高価であるという欠点を有して
いる。
BACKGROUND ART Conventionally, the following three methods are known as methods for manufacturing compound semiconductor thin film structures. That is, as a first method, Or-doped semi-insulating GaA
Vapor deposited on substrates with excellent crystallinity such as S and sapphire and good operability? This is a method of forming a compound semiconductor thin film using FMBK, OVD, etc. to form a structure. However, this method often requires complicated surface treatment immediately before forming the compound semiconductor thin film, and the types of substrates that can be used are limited in order to match the lattice constants. It has the disadvantage of being expensive.

第二の方法は、カラスなどの非結晶性基板上に、蒸着や
CVDなどの方法により化合物半導体薄膜を形成して構
造体とする方法がある。しかしながら、この方法におい
ては、非結晶性基板上に形成さnる化合物半導体薄膜が
一般には結晶性が良くないので、この結晶性を向上させ
るためにはん雑な後処理を必要とするという欠点がある
A second method is to form a compound semiconductor thin film on an amorphous substrate such as glass by a method such as vapor deposition or CVD to form a structure. However, this method has the disadvantage that the compound semiconductor thin film formed on the amorphous substrate generally does not have good crystallinity, and requires complicated post-processing to improve the crystallinity. There is.

さらに第三の方法は、雲母、塩化す) IJウム、臭化
カリウムなどの化合物半導体に対して選択除去可能な結
晶性基板上に、蒸着やMBE+C!VDなどの方法によ
って化合物半導体薄膜を形成したのち、該化合物半導体
薄膜をエポキシ樹脂などの接着剤を用いて基体に接着し
、次に前記結晶性基板を物理的若しくは化学的に除去す
ることにより構造体を製造する方法である(特公昭51
−45234公報など)。しかしながら、この方法(い
わゆる転写法)においては、得られた構造体がエポキシ
樹脂やフェノール樹脂などの有機接着層を有するために
信頼性、特に耐熱性や耐湿性に劣るという欠点を有して
いる。
A third method is to use evaporation or MBE+C! on a crystalline substrate that can selectively remove compound semiconductors such as mica, chloride, IJ, potassium bromide, etc. After forming a compound semiconductor thin film by a method such as VD, bonding the compound semiconductor thin film to a substrate using an adhesive such as an epoxy resin, and then physically or chemically removing the crystalline substrate to form a structure. It is a method of manufacturing the body (Special Publication Act 1977).
-45234 publication, etc.). However, this method (so-called transfer method) has the disadvantage that reliability, especially heat resistance and moisture resistance, is poor because the resulting structure has an organic adhesive layer such as epoxy resin or phenol resin. .

本発明者らは、このような欠点を克服し、信頼性の高い
構造体を得る方法について鋭意検討を重ねた結果、転写
法では、構造体の製造において結晶成長用基板と基体と
を分離できるだめに、結晶性に優れた薄膜と多岐にわた
る基体とを組合わせうる点に着目し、熱膨張係数が化合
物半導体薄膜に整合したガラス層を該薄膜と接着樹脂層
との間に設けることによって、その目的を達成しうるこ
とを見出し、この知見に基ついて本発明を完成するに至
った。
The inventors of the present invention have conducted intensive studies on how to overcome these drawbacks and obtain a highly reliable structure. As a result, the transfer method has found that the crystal growth substrate and the base body can be separated in the production of the structure. Instead, we focused on the fact that a thin film with excellent crystallinity could be combined with a wide variety of substrates, and by providing a glass layer whose coefficient of thermal expansion matched that of the compound semiconductor thin film between the thin film and the adhesive resin layer, The inventors have discovered that the object can be achieved, and have completed the present invention based on this knowledge.

すなわち、本発明は、基板上て接着樹脂層及び常1mに
おける熱膨張係数が30X10  /に〜70×10−
7/にの範囲内にあるガラス層を介して化合物半導体薄
膜を積層したことを特徴とする化合物半導体薄膜構造体
を提供するものである。
That is, in the present invention, the adhesive resin layer on the substrate has a thermal expansion coefficient of 30×10 / to 70×10 −
The object of the present invention is to provide a compound semiconductor thin film structure characterized in that compound semiconductor thin films are laminated via glass layers within a range of 7/.

本発明の構造体においては、カラス層としてその熱膨張
係数が化合物半導体薄膜の熱膨張係数に整合したものを
選択し7て設けることによって、初めて有機接着樹脂層
を有する構ノ告体の信頼性が飛躍的に向上させることが
できる。両者の熱膨張係数が整合していないと、高温処
理時に薄ノ漠がはがれたり、あるいは加熱力O湿時に薄
膜にしわが生じたシする。
In the structure of the present invention, by selecting and providing the glass layer whose thermal expansion coefficient matches that of the compound semiconductor thin film, the reliability of the structure having the organic adhesive resin layer can be improved. can be dramatically improved. If the thermal expansion coefficients of the two do not match, the thin layer may peel off during high temperature treatment, or wrinkles may occur in the thin film when the heating power is too high.

本発明の構造体は、例えば選択除去可能な化合物半導体
の結晶成長用基板上に化合物半導体薄膜を成長させる工
程と、該化合物半導体薄膜−ヒに常温における熱膨張係
数が30X10  /に〜70×10−77にの範囲内
にあるガラス層を形成させる工程と、該ガラス層を接着
樹脂により基体に接着する工程と、前記化合物半導体の
結晶成長用基板を選択除去する工程とを行うことによっ
て製造することができる。
The structure of the present invention includes a process of growing a compound semiconductor thin film on a selectively removable compound semiconductor crystal growth substrate, and a process in which the compound semiconductor thin film has a thermal expansion coefficient of 30 x 10 / to 70 x 10 at room temperature. -77, a step of adhering the glass layer to a substrate with an adhesive resin, and a step of selectively removing the substrate for crystal growth of the compound semiconductor. be able to.

次に、添付図面によって本発明の実施態様の概略を説明
すると、第1図は選択除去可能な化合物半導体の結晶成
長用基板上に成長させられた化合物半導体薄膜を示して
おシ、図中符号1が結晶成長用基板、2が化合物半導体
薄膜である。第2図はさらにガラス層3を形成した状態
を示してお9、第3図はガラス層3を樹脂層4を介して
基体5に接着させた際の状態を示している。次に第4図
は第3図で示される構造体から結晶成長用基板1を選択
除去して得られた本発明の化合物半導体薄膜構造体の構
成を示している。
Next, an outline of an embodiment of the present invention will be explained with reference to the accompanying drawings. FIG. 1 shows a compound semiconductor thin film grown on a selectively removable compound semiconductor crystal growth substrate. 1 is a crystal growth substrate, and 2 is a compound semiconductor thin film. FIG. 2 shows a state in which a glass layer 3 is further formed, and FIG. 3 shows a state in which the glass layer 3 is adhered to a base body 5 via a resin layer 4. Next, FIG. 4 shows the structure of a compound semiconductor thin film structure of the present invention obtained by selectively removing the crystal growth substrate 1 from the structure shown in FIG.

前記方法に用いる選択除去可能な化合物半導体の結晶成
長用基板は、化合物半導体薄膜の結晶をよく成長させ、
しかも該化合物半導体薄膜が強く付着しないものやある
いは該化合物半導体薄膜を溶解しない溶液に溶解するも
のなどであって、かつ結晶性であることが好ましい。こ
のようなものとしては、例えば雲母、グラファイト、塩
化ナトリウム、塩化カリウム、臭化カリウム、ヨウ化ナ
トリウム、ミョウバンなどが挙げられる。
The selectively removable compound semiconductor crystal growth substrate used in the method allows the compound semiconductor thin film crystal to grow well;
Moreover, it is preferable that the compound semiconductor thin film is not strongly adhered to or that can be dissolved in a solution that does not dissolve the compound semiconductor thin film, and that it is crystalline. Examples of such materials include mica, graphite, sodium chloride, potassium chloride, potassium bromide, sodium iodide, alum, and the like.

また、本発明に用いる化合物半導体としては、例えばG
aP 、 GaAs 、 Garb、Ink、 InA
s、InSb及びIn   GaxP、In   Ga
x As s 工n1x1−X           
  l −XGaXSb% oa、−xAzxpt G
a、−xAtXAB、 Ga、 −XAtxSb、 G
aAs、 −xPx、 GaAs、−xSbx、 Ga
rb、−xPx、 工nAs   Px、  InAs
、−xSbx、  ■nSb、−XPx −X などが挙げられ、これらの中で特に融点の低いGaEI
b、InAs、 InSb及びIn、 −x GaxS
b、工nA s r xSbx、InSb、 −xPx
などが有効である。
Further, as the compound semiconductor used in the present invention, for example, G
aP, GaAs, Garb, Ink, InA
s, InSb and In GaxP, In Ga
x As s ENG n1x1-X
l -XGaXSb% oa, -xAzxpt G
a, -xAtXAB, Ga, -XAtxSb, G
aAs, -xPx, GaAs, -xSbx, Ga
rb, -xPx, InAs Px, InAs
, -xSbx, ■nSb, -XPx -X, etc. Among these, GaEI, which has a particularly low melting point,
b, InAs, InSb and In, -x GaxS
b, Engineering nA s r xSbx, InSb, -xPx
etc. are valid.

前記の化合物半導体の結晶成長用基板上に化合物半導体
薄膜を形成するためには、通常蒸着(ヒーター加熱、K
B加熱)、MBE、スパッタリング、OVDなどの方法
が用いられる。この際薄膜の厚さは200久〜10μの
範囲が好ましく、さらに転写のしやすさや特性を考慮す
ると500久〜2μの範囲75=好適である。
In order to form a compound semiconductor thin film on the compound semiconductor crystal growth substrate described above, vapor deposition (heater heating, K
Methods such as B heating), MBE, sputtering, and OVD are used. At this time, the thickness of the thin film is preferably in the range of 200 μm to 10 μm, and in consideration of ease of transfer and characteristics, the range 75 = 500 μm to 2 μm is preferable.

本発明における化合物半導体薄膜と接着樹脂層との間如
介在させるガラス層は、電気絶縁性であってその熱膨張
係数が化合物半導体薄膜の熱膨張係数と整合したガラス
組成物から選ぶ必要があるが、本発明においては、ガラ
ス層の常温における熱膨張係数が30 X 10−7/
に〜70X10−7/にの範囲内あればよい。すなわち
、本発明に用いる化合物半導体薄膜の線熱膨張係数は、
室温から500℃の温度範囲で(は前記の範囲に入って
いる。例えばInP (45X 10−7.IK )、
工nsb (50X l O’−7/K )、GaAs
 (60X l O−7/K )などが室温における代
表的な線熱膨張係数をもつものとして挙げられる。
The glass layer interposed between the compound semiconductor thin film and the adhesive resin layer in the present invention must be selected from glass compositions that are electrically insulating and whose coefficient of thermal expansion matches that of the compound semiconductor thin film. , in the present invention, the coefficient of thermal expansion of the glass layer at room temperature is 30 x 10-7/
It is sufficient if it is within the range of ~70 x 10-7/. That is, the linear thermal expansion coefficient of the compound semiconductor thin film used in the present invention is:
In the temperature range from room temperature to 500°C (is within the above range. For example, InP (45X 10-7.IK),
Engineering nsb (50X l O'-7/K), GaAs
(60X l O-7/K) etc. are listed as having a typical coefficient of linear thermal expansion at room temperature.

このガラス層として、常温における熱膨張係数が30 
X 10−7/に〜70 X 10−7/にの範囲を逸
脱したものを用いると、熱処理前後における特性の変化
が小さくならないので、場合によっては熱処理時にはが
れを生じ、極端な場合には接着時にピンホールが多数発
生する。本発明において特に好ましいガラス層としては
、化合物半導体薄膜の熱膨張係数VC対して±l OX
 l O−7/にの熱膨張係数を有するガラス組成物を
用いることが望ましく、このようなガラス組成物として
は、例えばボウケイ酸ガラス類やアルミナケイ酸ガラス
類がある。
This glass layer has a thermal expansion coefficient of 30 at room temperature.
If a material that deviates from the range of X 10-7/ to 70 Many pinholes occur during adhesion. In the present invention, a particularly preferable glass layer has a coefficient of thermal expansion VC of ±l OX of a compound semiconductor thin film.
It is desirable to use a glass composition having a thermal expansion coefficient of 1 O-7/. Examples of such glass compositions include borosilicate glasses and alumina silicate glasses.

本発明において、化合物半導体薄膜と接着樹脂層との間
にガラス層を介在させる第一の理由は、薄膜、樹脂間の
相互拡散を防止するためである。
In the present invention, the first reason for interposing the glass layer between the compound semiconductor thin film and the adhesive resin layer is to prevent mutual diffusion between the thin film and the resin.

例えばカラス層を設けることによって、接着樹脂中の好
ましくない不純物が薄膜中((拡散したり、あるいは薄
膜構成元素か接着樹脂中に拡散して組成が変化したり、
膜厚が減少したジする現象を防ぐことかできる。壕だ、
第二の理由は、熱応力を緩和−fることにある。すなわ
ち、化合物半導体薄膜は40 X 10−7/に〜60
 X l O−7/に程度の熱膨張係数を有するのに対
し、一般に接着樹脂(はその熱膨張係数が1×10−5
/に〜7XIO”/にであって一桁大きいために、三者
が直接接触するとその界面での熱応力はぼり大なものと
なるが、熱膨張係数が化合物半導体薄膜のそれと整合し
たガラス層を三者の間に介在させることによって、前記
の熱応力は緩和される。しかしながら、ガラス層の熱膨
張係数が化合物半導体薄膜のそれと整合していないと、
ガラス層と薄膜との界面に熱応力が発生したり、あるい
は接着性が悪くなってはかれたシして、構造体の耐熱特
性の劣化をひき起す。
For example, by providing a glass layer, undesirable impurities in the adhesive resin may diffuse into the thin film, or elements constituting the thin film may diffuse into the adhesive resin and the composition may change.
It is possible to prevent the phenomenon of peeling caused by a decrease in film thickness. It's a trench.
The second reason is to relax thermal stress. That is, the compound semiconductor thin film is 40 x 10-7/~60
In general, adhesive resins have a thermal expansion coefficient of about 1 x 10-5/
/ ~ 7 The above thermal stress is alleviated by interposing the glass layer between the three.However, if the thermal expansion coefficient of the glass layer does not match that of the compound semiconductor thin film,
Thermal stress may occur at the interface between the glass layer and the thin film, or the adhesion may deteriorate and peel, resulting in deterioration of the heat resistance properties of the structure.

本発明においては、このガラス層の厚みは500又〜5
μmの範囲内にあることが望ましく、その厚みが500
 X未満では本発明の効果がみられず、また5μmを超
えると往々にしてはがれたり、あるいは基板を選択除去
したのちに多数のピンホールが発生したりする。好まし
いガラス層の厚みは1000〜5oooXの範囲である
In the present invention, the thickness of this glass layer is 500 mm to 5 mm.
It is desirable that the thickness be within the range of 500 μm.
If the thickness is less than X, the effect of the present invention will not be seen, and if it exceeds 5 μm, it will often peel off or a large number of pinholes will be generated after the substrate is selectively removed. The preferred thickness of the glass layer is in the range of 1000 to 500X.

このガラス層を化合物半導体薄膜上に形成する方法とし
て、例えばE、B、蒸着、スパッタリング、CvDなど
の方法を用いることができるが、これらの方法のなかで
該薄膜に対して接着性のよいスパッタリングが好ましく
用いられる。しかし、層厚をさほど必要としない場合に
はE、B、蒸着などによっても問題はない。
Methods such as E, B, vapor deposition, sputtering, and CvD can be used to form this glass layer on the compound semiconductor thin film. Among these methods, sputtering, which has good adhesion to the thin film, can be used. is preferably used. However, if the layer thickness is not required so much, E, B, vapor deposition, etc. may be used without any problem.

本発明に用いられる接着樹脂としてはガラス層に対して
接着性かよく、かつ熱変形温度が比較的高いものがよく
、このような樹脂としては、例えばエポキ7樹脂、ポリ
イミド樹脂、ポリアミドイミド樹脂などを挙けることが
できる。また、これらの樹脂は、化合物半導体薄膜に対
してドーピンク効果のある不純物や反応性のあるフィラ
ーなどを不必要に含有していないものが好ましい。
The adhesive resin used in the present invention preferably has good adhesion to the glass layer and has a relatively high heat distortion temperature. Examples of such resin include epoxy 7 resin, polyimide resin, polyamideimide resin, etc. can be mentioned. Further, these resins preferably do not unnecessarily contain impurities that have a doping effect on the compound semiconductor thin film, reactive fillers, and the like.

次に、本発明において用いられる基体(は、接着樹脂の
(灰化時、素子1ヒ時及び素子化後の処理に耐えるもの
であればよいか、特に化学的に安定で、かつ−100℃
から400℃の温度範囲において熱変形しないものが好
捷しい。このようなものとしては貴金属やセラミックな
どの無機材料、例えば金、銀、白金、パーマロイ、セン
タースト、アルミナ、フェライト、窒化ケイ素、石英、
サファイア、ホウケイ酸ガラス、アルミナケイ酸ガラス
などが挙げられる。
Next, the substrate used in the present invention may be any material as long as it can withstand the treatment of the adhesive resin (at the time of ashing, the time of device heating, and the processing after device formation), and is particularly chemically stable and at -100°C.
Preferably, the material does not undergo thermal deformation in the temperature range from 400°C to 400°C. These include precious metals and inorganic materials such as ceramics, such as gold, silver, platinum, permalloy, centerst, alumina, ferrite, silicon nitride, quartz,
Examples include sapphire, borosilicate glass, and alumina silicate glass.

本発明の構造体からの結晶成長用基板の除去は、用いる
基板の種類によって異なるが、物理的若しくは化学的方
法によって行われる。例えば基板として雲母を用いる場
合は、基体に接着された化合物半導体薄膜から基板を機
械的に剥離することができ、塩化ナトリウムを用いる場
合には水を使用して塩化ナトリウムのみを溶解させるこ
とができる。
Removal of the crystal growth substrate from the structure of the present invention is performed by a physical or chemical method, although it varies depending on the type of substrate used. For example, when mica is used as the substrate, the substrate can be mechanically peeled off from the compound semiconductor thin film adhered to the substrate, and when sodium chloride is used, only the sodium chloride can be dissolved using water. .

本発明の構造体は、優れた信頼性を有し、特に従来のも
のに比べて耐熱性の向上が著しい。したがって素子とし
て用いる場合、260℃、5 secのハンダディップ
や300℃の温度における/・ンダリフローのような処
理なども施すことができる。
The structure of the present invention has excellent reliability, and in particular has remarkable improvement in heat resistance compared to conventional structures. Therefore, when used as an element, treatments such as solder dipping at 260° C. for 5 seconds and/or soldering at a temperature of 300° C. can be performed.

また、本発明の構造体は、種々の形態の素子に加工しつ
る。すなわち、磁電変換素子(ホール素子、ホールヘッ
ド、磁気抵抗効果素子など)や接合型トランジスタ、電
界効果型トランジスタ、静電3導型トランジスタ、圧電
素子、発光素子、受光素子、感湿素子、感湿素子、さら
にこれらを集積してIC(集積回路)とすることも可能
である。
Further, the structure of the present invention can be processed into various types of elements. That is, magnetoelectric conversion elements (Hall elements, Hall heads, magnetoresistive elements, etc.), junction transistors, field effect transistors, electrostatic three-conductor transistors, piezoelectric elements, light emitting elements, light receiving elements, moisture sensing elements, humidity sensing It is also possible to integrate the elements into an IC (integrated circuit).

次に実施例によって本発明をさらに詳細に説明する。Next, the present invention will be explained in more detail with reference to Examples.

実施例1 結晶成長用基板として雲母を、また化合物半導体薄膜作
成装置としては2つのボートを有する真空蒸着装置を使
用し、工nとSbの蒸着を行った。
Example 1 Mica was used as a substrate for crystal growth, and a vacuum evaporation apparatus having two boats was used as a compound semiconductor thin film forming apparatus to perform vapor deposition of Sb and Sb.

この際、基板温度を440℃、真空度をi、5xio−
6TOrrとし、30分で1μとなるようにして、In
S b系複合結晶薄膜を製造した。
At this time, the substrate temperature was set to 440°C, the degree of vacuum was set to i, and 5xio-
6 TOrr and 1μ in 30 minutes, In
A Sb-based composite crystal thin film was manufactured.

さらに、この薄膜上にコーニング社製7059ガラス(
オウケイ酸ガラス、線熱膨張係数47X10−7iK>
*−スパッタリングして4200X厚のガラス層を形成
した。
Furthermore, on this thin film, Corning 7059 glass (
Osilicate glass, coefficient of linear thermal expansion 47X10-7iK>
*- Sputtered to form a 4200X thick glass layer.

次にエポギン樹脂(日本ベル7ソクス社製、XM188
0)を用いて、ガラス層を介した工nsb系薄膜を0 
、5 mm厚のフェライト板に接着したのち、雲母を機
械的に剥離してInSb系薄膜構造体を得た。
Next, Epogin resin (manufactured by Japan Bell 7 Sox Co., Ltd., XM188
0) to form a nsb-based thin film through a glass layer.
After adhering to a 5 mm thick ferrite plate, the mica was mechanically peeled off to obtain an InSb-based thin film structure.

この構造体にフォトリソグラフィーなどの手法を用いて
パターニングし、第5図に示す形状に加工したのち、こ
の薄膜の電気特性を測定したところ、ホール係数210
CJ/ C、電子移動度19,800cm/ V−13
であった。
After patterning this structure using techniques such as photolithography and processing it into the shape shown in Figure 5, we measured the electrical properties of this thin film and found that the Hall coefficient was 210.
CJ/C, electron mobility 19,800cm/V-13
Met.

この構造体に窒素雰囲気下で350℃、30分間の処理
を施し、ホール係数と電子移動度の変化率を求めたとこ
ろ、それぞれ+1.0%、−低5係であった。
This structure was treated in a nitrogen atmosphere at 350° C. for 30 minutes, and the change rates of the Hall coefficient and electron mobility were determined to be +1.0% and −5%, respectively.

比較例1 ガラス層を設けないこと以外は実施例1と同様にしてI
nSb系薄膜構造体を作成1−1窒素雰囲気下で350
℃、30分間の処理前後における特性変化率を調べたと
ころ、ホール係数の変化率は11,5係、電子移動度の
変化率は−5,6%であった。
Comparative Example 1 I was prepared in the same manner as in Example 1 except that the glass layer was not provided.
Creation of nSb-based thin film structure 1-1 350℃ under nitrogen atmosphere
When the rate of change in properties before and after treatment at 30°C was examined, the rate of change in Hall coefficient was 11.5%, and the rate of change in electron mobility was -5.6%.

実施例2 7059ガラヌをE、B、蒸着して1700ス厚のガラ
ス層を形成する以外は、実施例1と同様にして薄膜構造
体を作成した。この構造体を用いてホール素子400個
を作り、260℃ハンダティップ5 secのテストを
行って、定電圧感度の前後変化を求めたところ、平均−
0,1係で標準偏差2.6%であった。
Example 2 A thin film structure was produced in the same manner as in Example 1, except that 7059 galanu was vapor-deposited using E and B to form a glass layer with a thickness of 1700 mm. Using this structure, we made 400 Hall elements and conducted a solder tip test at 260°C for 5 seconds to determine the change in constant voltage sensitivity before and after, and found that the average -
The standard deviation for the 0.1 ratio was 2.6%.

また、比較のため、ガラス層を形成しない構造体を用い
て同様のテストを行い、定電圧感度の前後変化を求めた
ところ、平均−2,4%で標準偏差は3.3係であった
For comparison, a similar test was conducted using a structure without a glass layer, and the change in constant voltage sensitivity was found to be -2.4% on average, with a standard deviation of 3.3%. .

実施例3 実施例1と同様にしてInSb系薄膜を形成しまたのち
、コーニング社製1723カラス(アルミナケイ酸、4
2 X 10”−7/K)をスパッタリングして280
0X厚のガラス層を形成した。次に接着樹脂として四国
化成社製FC・・−ドXV 1161を、基体としてア
ルミナを用いて工nsb系薄膜構造体を作成した。
Example 3 An InSb-based thin film was formed in the same manner as in Example 1, and then 1723 Karas (alumina silicate, 4
2 x 10"-7/K) by sputtering to 280
A 0X thick glass layer was formed. Next, an NSB-based thin film structure was prepared using FC.

この構造体を第5図のパターンに加工して特性を求めた
ところ、ホール係数307 cnl/ O、電子移動度
27 、600 crl/ V、Sてあった。
When this structure was processed into the pattern shown in FIG. 5 and its characteristics were determined, the Hall coefficient was 307 cnl/O, and the electron mobility was 27, 600 crl/V, S.

また、この構造体を350℃て30分問屋素雰囲気下で
処理したのち、その特性を求めたところ、ホール係数3
08 ctd/ O1電子移動度27,600C疏/V
、Sであった。
In addition, after processing this structure in a wholesale atmosphere at 350°C for 30 minutes, we determined its characteristics, and found that the Hall coefficient was 3.
08 ctd/ O1 electron mobility 27,600 C/V
, S.

実施例4 蒸着基板として雲母を、装置として3つのボートを有す
る真空蒸着装置を使用して釦、sb及び八8の蒸着を行
った。こ、の際基板温度を40分間で400℃から55
0℃まで昇温し、1.2μm厚のIn’sbo、、 A
so、、薄膜を得た。
Example 4 Mica was used as the deposition substrate and a vacuum deposition apparatus having three boats was used to deposit buttons, sb, and 88. During this time, the substrate temperature was increased from 400°C to 55°C in 40 minutes.
In'sbo, heated to 0°C and 1.2 μm thick, A
So, a thin film was obtained.

この薄膜に、コーニング社製7052.1723.77
40ガラスを、それぞn 2500 X厚にスパッタリ
ングし、接着樹脂として四国化成社製FC・・−ドXV
 1161  を用いてフェライト板に接着した3種の
In5bAs系薄膜構造体を製造した。
This thin film was coated with Corning's 7052.1723.77.
40 glass was sputtered to a thickness of 2,500 x each, and FC...-do XV manufactured by Shikoku Kasei Co., Ltd. was used as the adhesive resin.
Three types of In5bAs-based thin film structures bonded to ferrite plates were manufactured using 1161.

この構造体それぞれの耐熱特性を、窒素雰囲気下380
℃で30分間処理して求めた。その結果を第1表に示す
The heat resistance characteristics of each of these structures were evaluated at 380 °C under a nitrogen atmosphere.
It was determined by processing at ℃ for 30 minutes. The results are shown in Table 1.

第1表 比較例2 ガラスとしてコーニング社製6720.7900を用い
る以外は、実施例4と同様にして薄膜構造体を製造し、
このものの耐熱特性を求めた。その結果を第2表に示す
Table 1 Comparative Example 2 A thin film structure was produced in the same manner as in Example 4 except that Corning 6720.7900 was used as the glass,
The heat resistance properties of this material were determined. The results are shown in Table 2.

第    2    表 実施例5 結晶成長用基板として塩化す) IJウムを用い、実施
例1と同様の方法を用いてIn5b系複合結晶薄膜を製
造した。この塩化ナトリウム上に形成されたInSb系
複合結晶薄膜の上に実施例1と同様にコーニング社!L
’osc+ガラスをスパッタリングして5200X厚の
ガラス層を形成し、次いて0.5馴厚のフェライト板上
に旭化成仕製AER331を用いて転写したのち、水を
用いて塩化ナトリウムを除去した。この構造体をホール
素子に加工したの、ち100個の感度を測定したところ
、39〜53mV / 5mAx IK、Gauss 
 であった。この素子の耐湿試験を温度65℃、湿度9
7%で12時間と25℃、65%で12時間の乾湿サイ
クルを15回繰り返す条件下で行ったところ、その中の
91個の感度変化率が2%以内におさまった。
Table 2 Example 5 An In5b composite crystal thin film was produced in the same manner as in Example 1 using IJ (chloride) as a substrate for crystal growth. Corning Co., Ltd. as in Example 1 was applied on the InSb composite crystal thin film formed on the sodium chloride. L
'OSC+ glass was sputtered to form a glass layer with a thickness of 5200X, and then transferred onto a 0.5X ferrite plate using AER331 manufactured by Asahi Kasei, and the sodium chloride was removed using water. When this structure was processed into a Hall element, the sensitivity of 100 pieces was measured, and it was 39 to 53 mV / 5 mAx IK, Gauss
Met. The humidity test of this element was carried out at a temperature of 65℃ and a humidity of 9.
When a dry/wet cycle of 7% for 12 hours and 25° C. and 65% for 12 hours was repeated 15 times, the sensitivity change rate of 91 of them was within 2%.

比較例3 ガラス層としてコーニング社製7900ガラスを用いる
以外は、実施例5と同様にしてホール素子100個を製
造し、同様の試験を行ったところ、その中の74個の感
度変化率が2%以内におさまっていた。
Comparative Example 3 100 Hall elements were manufactured in the same manner as in Example 5 except that 7900 glass manufactured by Corning Corporation was used as the glass layer, and the same test was conducted, and 74 of them had a sensitivity change rate of 2. It was within %.

実施例6 基板及び装置は実施例4と同様のものを用い、In、G
a及びsbの蒸着を行ってGao、3Ino、7Sb薄
膜を形成した。この際、基板温度は410℃から550
℃までの昇温法に従い、蒸着時間は35分間とし、膜厚
は1.5μmとした。次いてコーニング社製1720ガ
ラス(アルミナケイ酸、熱膨張係数42X10−7/K
)をスパッタリンクして2200X厚のカラス層を形成
したのち、東芝ケミカル社製TVB 2703を用いて
フェライト板に転写した。
Example 6 The same substrate and device as in Example 4 were used, and In, G
Gao, 3Ino, and 7Sb thin films were formed by vapor deposition of a and sb. At this time, the substrate temperature ranges from 410°C to 550°C.
The deposition time was 35 minutes, and the film thickness was 1.5 μm according to the heating method up to ℃. Next, Corning 1720 glass (alumina silicate, thermal expansion coefficient 42X10-7/K
) was sputter-linked to form a glass layer with a thickness of 2200X, and then transferred to a ferrite plate using TVB 2703 manufactured by Toshiba Chemical Corporation.

この構造体を第5図の形状に加工したもの10個(・て
、窒素雰囲気下400℃で30分間の熱処理を施して、
入力抵抗と定電圧感度の変化率を求めたところ、それそ
A−4,8〜5.1%、−4,7〜2.1%であり、4
00℃の処理にもかかわらず、変化率か最大5係程度と
良好な耐熱性を示した。
Ten pieces of this structure were processed into the shape shown in Fig.
When the rate of change of input resistance and constant voltage sensitivity was calculated, they were A-4, 8 to 5.1%, -4, 7 to 2.1%, and 4.
Despite the treatment at 00°C, the rate of change showed good heat resistance with a maximum factor of 5.

比較例4 ガラス層として2600X厚の5102 層をスパンタ
リングによシ形成する以外は、実施例6と同様に実施し
たところ、400℃の熱処理後、電極部に多くのピンホ
ールが発生した。
Comparative Example 4 Example 6 was carried out in the same manner as in Example 6, except that a 2600× thick 5102 layer was formed by sputtering as the glass layer. After heat treatment at 400° C., many pinholes were generated in the electrode portion.

実施例7 基板及び装置は実施例1と同様とし、三温度蒸着法を用
いてInとASの蒸着を行った。得られたInAs系薄
膜は電子移動度4200 cA/ V、Sを有していた
。このInAs系薄膜(熱膨張係数52X10−7/K
 )上に、コーニング社製7056ガラス(ホウケイ酸
、熱膨張係数51 X 10 ’/K )を3800λ
厚にスパツタリシグしたのち、TVB 2703を用い
てアルミナ板に転写した。
Example 7 The substrate and apparatus were the same as in Example 1, and In and AS were deposited using a three-temperature deposition method. The obtained InAs-based thin film had an electron mobility of 4200 cA/V, S. This InAs thin film (thermal expansion coefficient 52X10-7/K
), Corning's 7056 glass (borosilicate, thermal expansion coefficient 51 x 10'/K) was placed at 3800λ
After sputtering thickly, it was transferred to an alumina plate using TVB 2703.

この構造体を第5図に示す形状に加工したのち、窒素雰
囲気下400℃で熱処理して、特性の変化率を求めたと
ころ、入力抵抗+0.2係、正孔移動度0.0係であっ
た◇
After processing this structure into the shape shown in Fig. 5, it was heat-treated at 400°C in a nitrogen atmosphere and the rate of change in characteristics was determined. There was◇

【図面の簡単な説明】[Brief explanation of drawings]

第1図は選択除去可能な化合物半導体の結晶成長用基板
上に化合物半導体薄膜を成長させた状態、第2図はさら
にガラス層を形成した状態、第3図(はガラス層を樹脂
層を介して基体に接着させた状態及び第4図は第3図で
示される構造体から結晶成長用の基板を選択除去して得
られた本発明の化合物半導体薄膜構造体のそれぞれ断面
図であって、図中符号1は結晶成長用基板、2は化合物
半導体薄膜、3はガラス層、4は樹脂層、5は基体てあ
第5図は本発明において構造体の評価に用いたパターン
であって、図中符号a、a’は入力電極、b、b’は出
力電極である。 特許出願人 旭化成工業株式会社 代理人 阿 形  明 第1図 第2図 第3図 第4図 第5図 手続補正書 昭和58年4 月1 日 3 補正をする者 事f4との関係 特許出願人 住 所 大阪府大阪市北区堂島1兵1丁目2番6号代表
渚 宮  崎     輝 46代 理 人 〒104東京都中央区銀座6丁目4番5号土屋ピノし5
階8、補正の内容 ([)明細書第9ページ第15行目の[ooo〜500
0XIを1700〜5000AJに訂正します。 (2)同第17ページ第7行目[5200AJを「12
00A」に訂正します。
Figure 1 shows a compound semiconductor thin film grown on a selectively removable compound semiconductor crystal growth substrate, Figure 2 shows a state in which a glass layer is further formed, and Figure 3 shows a state in which a glass layer is grown through a resin layer. FIG. 4 is a cross-sectional view of the compound semiconductor thin film structure of the present invention obtained by selectively removing the substrate for crystal growth from the structure shown in FIG. In the figure, reference numeral 1 indicates a substrate for crystal growth, 2 indicates a compound semiconductor thin film, 3 indicates a glass layer, 4 indicates a resin layer, and 5 indicates a substrate. In the figure, symbols a and a' are input electrodes, and b and b' are output electrodes. Patent applicant Asahi Kasei Industries Co., Ltd. Agent Akira Agata Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Procedure correction April 1, 1982 3 Relationship with party making the amendment f4 Patent applicant address 1-2-6 Dojima 1-chome, Kita-ku, Osaka-shi, Osaka Representative Nagisa Teru Miyazaki 46th Masato Address 104 Tokyo Tsuchiya Pinoshi 5, 6-4-5 Ginza, Chuo-ku, Tokyo
Floor 8, Contents of amendment ([) [ooo ~ 500] on page 9, line 15 of the specification
Correct 0XI to 1700-5000AJ. (2) Page 17, line 7 [5200AJ is replaced with “12
Corrected to 00A.

Claims (1)

【特許請求の範囲】 1 基板上に、接着樹脂看及び常温における熱膨張係数
が30X10−7/に〜70 X l O−7/にの範
囲内にあるガラス層を介して化合物半導体薄膜を積層し
たことを特徴とする化合物半導体薄膜構造体。 2 選択除去可能な化合物半導体の結晶成長用基板上に
化合物半導体薄膜を成長させる工程と、該化合物半導体
薄膜上に常温における熱膨張係数が30 X 10−7
/に〜70 X 10−7/にの範囲内にあるガラス層
を形成させる工程と、該ガラ3層を接着樹脂により基体
に接着する工程と、前記化合物半導体の結晶成長用基板
を選択除去する工程とを有することを特徴とする、化合
物半導体薄膜構造体の製造方法。
[Claims] 1. A compound semiconductor thin film is laminated on a substrate via an adhesive resin and a glass layer whose thermal expansion coefficient at room temperature is within the range of 30X10-7/ to 70X10-7/. A compound semiconductor thin film structure characterized by: 2. A step of growing a compound semiconductor thin film on a selectively removable compound semiconductor crystal growth substrate, and growing a compound semiconductor thin film on the compound semiconductor thin film with a thermal expansion coefficient of 30 x 10-7 at room temperature.
A step of forming a glass layer within the range of / to 70 x 10-7/, a step of adhering the three glass layers to a substrate with an adhesive resin, and selectively removing the substrate for crystal growth of the compound semiconductor. A method for manufacturing a compound semiconductor thin film structure, comprising the steps of:
JP57221282A 1982-12-17 1982-12-17 Compound semiconductor thin-film structure and its manufacture Pending JPS59111321A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57221282A JPS59111321A (en) 1982-12-17 1982-12-17 Compound semiconductor thin-film structure and its manufacture

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57221282A JPS59111321A (en) 1982-12-17 1982-12-17 Compound semiconductor thin-film structure and its manufacture

Publications (1)

Publication Number Publication Date
JPS59111321A true JPS59111321A (en) 1984-06-27

Family

ID=16764336

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57221282A Pending JPS59111321A (en) 1982-12-17 1982-12-17 Compound semiconductor thin-film structure and its manufacture

Country Status (1)

Country Link
JP (1) JPS59111321A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0371862A2 (en) * 1988-11-29 1990-06-06 The University Of North Carolina At Chapel Hill Method of forming a nonsilicon semiconductor on insulator structure
EP1179842A2 (en) * 1992-01-31 2002-02-13 Canon Kabushiki Kaisha Semiconductor substrate and method for preparing same

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57197884A (en) * 1981-05-29 1982-12-04 Sony Corp Composite substrate

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57197884A (en) * 1981-05-29 1982-12-04 Sony Corp Composite substrate

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0371862A2 (en) * 1988-11-29 1990-06-06 The University Of North Carolina At Chapel Hill Method of forming a nonsilicon semiconductor on insulator structure
EP0371862A3 (en) * 1988-11-29 1990-11-22 The University Of North Carolina At Chapel Hill Method of forming a nonsilicon semiconductor on insulator structure
EP1179842A2 (en) * 1992-01-31 2002-02-13 Canon Kabushiki Kaisha Semiconductor substrate and method for preparing same

Similar Documents

Publication Publication Date Title
JP3047656B2 (en) Method for producing InSb thin film
JPH03133176A (en) Silicon carbide semiconductor device and manufacture thereof
JPS6173345A (en) Semiconductor device
US5512873A (en) Highly-oriented diamond film thermistor
TW202002508A (en) Bonded body and elastic wave element
JPS59111321A (en) Compound semiconductor thin-film structure and its manufacture
JP2002541473A (en) Method of manufacturing thin film piezoresistive sensor
JPH05190877A (en) Manufacture of diode element
JPH0770472B2 (en) Method for manufacturing semiconductor substrate
JP2854038B2 (en) Semiconductor element
JPH0419699B2 (en)
JPS58175833A (en) Manufacture of compound semiconductor thin-film structure
JP3207957B2 (en) Method for forming InSb thin film
JPS58135645A (en) Manufacture of semiconductor device
JPH05218528A (en) Magneto electric conversion element
JPS62234322A (en) Manufacture of semiconductor device
JPH04332131A (en) Semiconductor device
TW202234472A (en) Composite wafer and method for producing same
JP2713744B2 (en) Magnetoelectric conversion element
CN116403886A (en) Two-dimensional material photoelectronic chip and preparation method thereof
JP6082521B2 (en) Semiconductor element
JPH0582989B2 (en)
JP2703231B2 (en) Method for manufacturing silicon semiconductor substrate
JPH0364811B2 (en)
JPS603152A (en) Manufacture of amorphous semiconductor device