JPH0419699B2 - - Google Patents

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Publication number
JPH0419699B2
JPH0419699B2 JP57018374A JP1837482A JPH0419699B2 JP H0419699 B2 JPH0419699 B2 JP H0419699B2 JP 57018374 A JP57018374 A JP 57018374A JP 1837482 A JP1837482 A JP 1837482A JP H0419699 B2 JPH0419699 B2 JP H0419699B2
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JP
Japan
Prior art keywords
compound semiconductor
thin film
substrate
glass
glass layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP57018374A
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Japanese (ja)
Other versions
JPS58135628A (en
Inventor
Keiji Kuboyama
Takeki Matsui
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Asahi Chemical Industry Co Ltd
Original Assignee
Asahi Chemical Industry Co Ltd
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Filing date
Publication date
Application filed by Asahi Chemical Industry Co Ltd filed Critical Asahi Chemical Industry Co Ltd
Priority to JP57018374A priority Critical patent/JPS58135628A/en
Publication of JPS58135628A publication Critical patent/JPS58135628A/en
Publication of JPH0419699B2 publication Critical patent/JPH0419699B2/ja
Granted legal-status Critical Current

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Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • H01L21/2003Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy characterised by the substrate
    • H01L21/2007Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Formation Of Insulating Films (AREA)
  • Hall/Mr Elements (AREA)
  • Recrystallisation Techniques (AREA)

Description

【発明の詳細な説明】[Detailed description of the invention]

本発明は化合物半導体薄膜構造体の製造方法、
さらに詳しくは、信頼性に優れた化合物半導体薄
膜構造体の製造方法に関するものである。 従来、化合物半導体薄膜構造体を製造する方法
としては、大別して以下に示す三つの方法が知ら
れている。すなわち、まず第一の方法として、
Crドーブの半絶縁性GaAsやサフアイアなどの結
晶性に優れ、しかも操作性の良好な基板上に蒸着
やMBEやCVDなどにより化合物半導体薄膜を形
成して構造体とする方法が知られている。しかし
ながら、この方法は化合物半導体薄膜を形成する
直前にしばしばはん雑な表面処理を必要とする上
に、格子定数を整合させるために基板の種類が限
定され、しかもこの種の基板は往々にして高価で
あるなどの欠点を有している。 次に第二の方法として、ガラスなどの非結晶性
基板上に、蒸着やCVDなどの方法により化合物
半導体薄膜を形成して構造体とする方法が知られ
ている。しかしながら、この方法においては、非
結晶性基板上に形成される化合物半導体薄膜が一
般には結晶性が良くないので、この結晶性を向上
させるためにはん雑な後処理を必要とするという
欠点がある。 さらに第三の方法として、雲母、塩化ナトリウ
ム、臭化カリウムなどの化合物半導体に対して選
択除去可能な結晶性基板上に、蒸着やMBEや
CVDなどの方法によつて化合物半導体薄膜を形
成したのち、該化合物半導体薄膜をエポキシ樹脂
などの接着剤を用いて基体に接着し、次に前記結
晶性基板を物理的若しくは化学的に除去すること
により化合物半導体薄膜構造体(以下、CSTSと
略記する)を製造する方法が知られている(特公
昭51−45234公報など)。しかしながら、この方法
(いわゆる転写法)においては、得られた構造体
がエポキシ樹脂やフエノール樹脂などの有機の接
着層を有するために信頼性、特に耐熱性や耐湿性
に劣るという欠点を有している。 本発明者らは、前記した従来方法の欠点を克服
し、簡単な手段で信頼性の高い化合物半導体薄膜
構造体を得ることができる方法を開発すべく鋭意
研究を重ねた結果、いつたん絶縁性の結晶成長用
基板上に成長させた化合物半導体結晶層を永久支
持するための絶縁性基体に転写し、低溶融ガラス
を用いて融着させたのち、結晶成長用基板を除去
することにより、その目的を達成しうることを見
出し、この知見に基づいて本発明をなすに至つ
た。 すなわち、本発明は、絶縁性の結晶成長用基板
上に、化合物半導体結晶を成長させて基板と化合
物半導体結晶薄膜から成る第一複合体とする工
程、永久支持するための絶縁性基体上に該化合物
半導体結晶の融点より低くかつ、その線膨張係数
が基体のそれに対して±10×10-7/℃の範囲にあ
るガラス層を形成させて第二複合体とする工程、
第一複合体と第二複合体とを前者の化合物半導体
結晶薄膜と後者のガラス層とが接触するように密
着させたのち、900℃以下の温度に加熱して両者
を融着させる工程、及び第一複合体の結晶成長用
基板のみを選択的に除去することからなり、前記
永久支持用絶縁性基体と化合物半導体薄膜とが一
体となつた化合物半導体薄膜構造体の製造方法を
提供するものである。 本発明方法においては、先ず化合物半導体結晶
の薄膜を所定の結晶成長用基板上に成形させ、こ
れを低融点ガラス層を介して所定の基板上に転写
することが必要であり、このようにしないと化合
物半導体薄膜をガラス中に拡散させることなく、
円滑に転写させることができない。 次に、添付図面によつて本発明の実施態様の概
略を説明する。第1図A〜Dは本発明方法による
構造体の製造工程の説明図であつて、図中符号1
は化合物半導体の絶縁性の結晶成長用基板、2は
化合物半導体薄膜、3は基体、4は低溶融ガラス
層である。 まず、第1工程として第1図Aに示すように、
選択除去可能な化合物半導体の結晶成長用基板1
の上に所望の化合物半導体薄膜2の結晶を成長さ
せ、一方第2工程として第1図Bに示すように、
適当な基体3上に低溶融ガラス層4が形成され
る。次に第3工程として第1図Cに示すように、
前記の結晶成長用基板上の化合物半導体薄膜2と
基体上の低溶融ガラス層4を密着させたのち、ガ
ラス層を軟化させて接着させ、最後の第4工程と
して、結晶成長用基板1が選択除去されて第1図
Dに示すような構造体が得られる。 このような工程を経て得られた構造体は、基体
上にガラス層を介して化合物半導体薄膜が形成さ
れたものであり、従来の構造体と異なつて有機層
をもたないために極めて信頼性の優れたものであ
る。 本発明方法に用いる結晶成長用基板は、化合物
半導体薄膜の結晶をよく成長させ、しかも該化合
物半導体薄膜が強く付着しないものやあるいは該
化合物半導体薄膜を溶解しない溶液に溶解するも
のなどであつて、かつ結晶性であることが好まし
い。このようなものとしては、例えば雲母、グラ
フアイト、塩化ナトリウム、塩化カリウム、臭化
カリウム、ヨウ化ナトリウム、ミヨウバンなどが
挙げられる。 前記の結晶成長用基板上に化合物半導体薄膜を
形成するために、通常蒸着(ヒーター加熱、EB
加熱)、MBE、スパツタリング、CVDなどの方
法が行われる。この際薄膜の厚さは200Å〜10μ
の範囲が好ましく、さらに転写のしやすさや特性
を考慮すると500Å〜2μの範囲が好適である。 本発明方法において、基体上に化合物半導体の
融点より低い軟化点を有するガラス層を形成する
ために用いるガラスとしては、いわゆる低溶融ガ
ラスが必要であつて、このガラスの軟化点(Ts)
については、該化合物半導体の融点(Tm)より
低ければ特に制限はないが、あまり低すぎると耐
熱性が向上しないため、その軟化点は一般に300
℃以上であつてTmより20℃以上低いものが望ま
しく、さらに好ましくはTmより50℃以上低いも
のである。また、本発明に用いるガラスの熱膨張
率は、使用される基体の熱膨張率に近いことが必
要であつて、基体の熱膨張率と大きく異なると、
化合物半導体薄膜に不必要な歪が加わつたり、あ
るいは基体が破損したりする。したがつてガラス
の線膨張係数は基体の線膨張係数に対して±15×
10-7/℃、好ましくは±10×10-1/℃、好ましく
は±5×10-7/℃の範囲にあるのが望ましい。さ
らに本発明に用いるガラスは、絶縁抵抗の大きな
ものが好ましく、電気的素子として使用する場合
は、通常108Ωcmより抵抗率が大きいことが必要
である。 本発明方法において永久支持するための絶縁性
の基体として用いる材料は、使用されるガラスの
軟化点よりも高いものであればよいが、ガラスの
軟化点から室温に至る温度領域において形状が安
定であるものが好ましい。このようなものとして
は、例えばセラミツクなどの無機材料が挙げら
れ、具体的にはアルミナ、フエライト、窒化ケイ
素、石英、サフアイア、ホウケイ酸ガラスなどが
挙げられる。 本発明方法において基体上にガラス層を形成す
る方法としては、例えばニトロセルロース系のバ
インダーなどに粉状のガラスを分散させたものを
基体上に塗布したのち焼成する方法が代表的なも
のとして挙げられる。この場合、ガラス層厚の均
一化をはかるために、ガラス層厚は50〜500μが
好ましく、さらには100〜300μの範囲にあるのが
好適である。また、場合によつてはラツピングな
どによつてガラス層厚の均一化をはけるとさらに
好ましい。 基体上にガラス層を形成する他の方法として、
蒸着(ヒーター加熱、EB加熱)やスパツタリン
グによる方法がある。蒸着による場合、蒸着され
たガラス層の組成をコントロールする上から、通
常数種のガラス組成物を共蒸着し、膜厚は1000Å
〜10μの範囲が好ましい。またこのガラス層を基
体上と化合物半導体薄膜上の両方に形成して用い
ると、より好ましい結果が得られる。 本発明方法における化合物半導体薄膜とガラス
層の融着方法としては、例えば電気炉や高周波炉
中で加熱する方法が挙げられるが、ガラス層だけ
を高温下においた方がよいことから高周波炉中で
行う方が好ましく、また場合によつてはアルゴン
や窒素などの不活性ガス雰囲気中で行うのがよ
い。接着時の温度はガラスの軟化点以上にする必
要があるが、軟化点に近すぎると接着むらが生じ
やすいため、軟化点より10℃以上高い方が好まし
い。しかし、あまり加熱温度が高すぎたり、ある
いはガラスが軟化している時間が長すぎたりする
と、化合物半導体薄膜がガラス層に拡散してしま
つて当初の目的を達することができない。この拡
散の点から温度の上限や時間の制限は、用いる化
合物半導体の物性によつて異なる。 本発明方法における結晶成長用基板の除去は、
用いる基板の種類によつて異なるが、物理的若し
くは化学的方法によつて行われる。例えば基板と
して雲母を用いる場合は、ガラスによつて基体に
接着された化合物半導体薄膜から基板を機械的に
剥離することができ、塩化ナトリウムを用いる場
合には水を使用して塩化ナトリウムのみを溶解さ
せることができる。 本発明方法によつて製造された構造体は、優れ
た信頼性を有し、特に従来のものに比べて耐熱性
の向上が著しい。例えば従来のエポキシ系の接着
剤を用いた構造体では200℃以上の温度では接着
剤が焼けてしまうために構造体としての機能を失
うが、本発明の低容融ガラスを用いた構造体の場
合は、用いるガラスにもよるが400℃程度の高温
下でも構造体としての機能を失うことはない。 さらに本発明の副次的効果として、工業的生産
性の向上を挙げることができる。すなわち、本発
明により得られる構造体は耐熱性に優れるため、
従来の構造体では不可能であつた高融点ボールハ
ンダを用いたボンデイングが可能である。また従
来の有機接着剤を用いた構造体では、軟質接着層
があるために超音波ボンデイングが不可能であつ
たが、本発明の構造体はガラス層が固くて超音波
ボンデイングを行うことができる。したがつて本
発明の構造体は前記2種類のボンデイングが可能
であるために、いずれの方法をとるにせよ、ボン
デイング工程を自動化しうるので、工業的生産性
を大幅に向上させることができる。 また、本発明方法により製造された構造体は、
種々の形態の素子に加工しうる。すなわち、磁電
変換素子(ホール素子、ホールヘツド、磁気抵抗
効果素子など)や接合型トランジスタ、電界効果
型トランジスタ、静電誘導型トランジスタ、圧電
素子、発光素子、感温素子、感湿素子、さらにこ
れらを集積してIC(集積回路)とすることも可能
である。 次に実施例によつて本発明をさらに詳細に説明
する。 なお、本発明の実施例においては、特公昭51−
45234号公報との対比を主とするため、化合物半
導体薄膜としてInSb系のものを中心に述べるが、
本来本発明はInSb系の薄膜のみに限定されるも
のではなく、例えばInAs、InP、GaAs、GaSb、
GaP若しくは三元素のGaxIn1−xSb、GaxAl1
xAs、InSb1−xAsxなどの薄膜にも適用すること
ができる。 実施例 1 結晶成長用基板として雲母を、また化合物半導
体薄膜作成装置としては2つのボートを有する真
空蒸着装置を使用し、InとSbの蒸着を行つた。
この際、基板温度を440℃、真空度を1.5×
10-6Torrとし、30分で1μとなるようにして、
InSb系複合結晶薄膜を製造した。 一方イワキガラス社製、線膨張率が69×10-7
℃のT191BFをニトロセルロース(旭化成社製H
−20)2%酢酸n−ブチル溶液に分散させ1mm厚
の線膨張率が75×10-7/℃のフエライト板(東北
金属社製3000L)に塗布し、650℃にて焼成した。 以上のようにして得られたInSb系複合結晶薄
膜と低溶融ガラス層とを密着し、100gの重錘を
のせて電気炉中に入れ、電気炉の温度を460℃ま
で昇温した。そして温度を460℃に2分間保つた
のち降温し、80℃になつたところで取り出し、雲
母を機械的に剥離した。 このようにして得られたInSb系CSTSを第2図
のパターンに加工してホール移動度を測定したと
ころ20℃で4400cm2/V・Sであつた。次にこの
CSTSのホール移動度の測定を280℃の高温下で
試みたところ測定できて1700cm2/V・Sであつ
た。 比較例 1 実施例1と同様にしてInSb系複合結晶薄膜を
製造したのち、エポキシ樹脂(日本ペルノツクス
社製ME−264)を用いて1mm厚のフエライト板
に接着し、雲母を機械的に剥離し、第2図のパタ
ーンに加工した。このサンプルのホール移動度の
測定を250℃の高温下で試みたが、膜がぼろぼろ
になり、測定することができなかつた。 実施例 2 結晶成長用基板として塩化ナトリウムを用い、
実施例1と同様の方法を用いてInSb系複合結晶
薄膜を製造した。この塩化ナトリウム上に形成さ
れたInSb系複合結晶薄膜を実施例1と同様に0.5
mm厚のフエライト板上にイワキガラス社製T−
191BFを用いて転写したのち、水を用いて塩化ナ
トリウムを除去した。この構造体をホール素子に
加工したのち100個の感度を測定したところ、40
〜56mV/5mA×1KGaussであつた。この素
子の耐湿試験を温度65℃、湿度97%で12時間と25
℃、65%で12時間の乾湿サイクルを20回繰り返す
条件下で行つたところ、その中の92個が感度に変
化がなかつた。 比較例 2 転写にエポキシ樹脂(旭化成社製AER331)を
用いる他は実施例2と同様にしてホール素子を
100個製造し、同様の試験を行つたところ、その
中の73個が感度に変化がなかつた。 実施例 3 実施例1と同じ装置を使い三温度蒸着法によつ
てInAs薄膜を製造した。この際、結晶成長用基
板として臭化カリウムを用い、基板温度を550℃、
真空度を2×10-6Torrとした。 一方コーニング社製、線膨張率が89×10-7/℃
の1417ガラスを実施例1と同様にして0.5mm厚の
線膨張率が81×10-7/℃のアルミナ板上に780℃
で焼成したのちラツピングを行つた。この際、最
終的なガラス層厚は138〜141μであつた。 以上のようにして得られたInAs薄膜と低溶融
ガラス層とを密着し、100gの重錘をのせて電気
炉中に入れ、雰囲気をアルゴン雰囲気とし、520
℃まで昇温し、ただちに降温した。そして50℃で
取り出し、水を用いて臭化カリウムを除去した。 このようにして得られたInAs系薄膜構造体を
第2図のようにパターニングしてホール移動度を
測定したところ、20℃で3400cm2/V・Sであつ
た。また20℃での入力抵抗は187Ωであつたが、
さらに300℃での高温化でも測定することができ、
その値は122Ωであつた。 実施例4〜6及び比較例3〜5 結晶成長用基板として雲母を用い、実施例1と
同様の方法を用いてInSb系複合結晶薄膜を製造
した。次に0.5mm厚で線膨張率が80×10-7/℃の
フエライト板を基体とし、コーニング社製1417、
7520、8463、イワキガラス社製T−191BF、T−
029、旭硝子社製1200を用いて転写を行い、得ら
れた薄膜構造体の外部評価(目視観察)を行つ
た。その結果を第1表に示す。
The present invention provides a method for manufacturing a compound semiconductor thin film structure,
More specifically, the present invention relates to a method for manufacturing a compound semiconductor thin film structure with excellent reliability. BACKGROUND ART Conventionally, the following three methods are known as methods for manufacturing compound semiconductor thin film structures. That is, as a first method,
A known method is to form a structure by forming a compound semiconductor thin film by vapor deposition, MBE, CVD, etc. on a substrate with excellent crystallinity and good operability, such as Cr-doped semi-insulating GaAs or sapphire. However, this method often requires complicated surface treatment immediately before forming the compound semiconductor thin film, and the types of substrates that can be used are limited in order to match the lattice constants. It has drawbacks such as being expensive. Next, as a second method, a method is known in which a compound semiconductor thin film is formed on an amorphous substrate such as glass by a method such as vapor deposition or CVD to form a structure. However, this method has the disadvantage that the compound semiconductor thin film formed on the amorphous substrate generally does not have good crystallinity, and requires complicated post-processing to improve the crystallinity. be. A third method is to use evaporation, MBE, or
After forming a compound semiconductor thin film by a method such as CVD, adhering the compound semiconductor thin film to a substrate using an adhesive such as an epoxy resin, and then physically or chemically removing the crystalline substrate. A method of manufacturing a compound semiconductor thin film structure (hereinafter abbreviated as CSTS) is known (Japanese Patent Publication No. 51-45234, etc.). However, this method (so-called transfer method) has the disadvantage that the obtained structure has an organic adhesive layer such as epoxy resin or phenol resin, and therefore has poor reliability, especially heat resistance and moisture resistance. There is. The present inventors have conducted extensive research to overcome the drawbacks of the conventional methods described above and to develop a method that can obtain a highly reliable compound semiconductor thin film structure using simple means. The compound semiconductor crystal layer grown on the crystal growth substrate is transferred to an insulating substrate for permanent support, fused using low melting glass, and then the crystal growth substrate is removed. We have found that the object can be achieved, and based on this knowledge, we have completed the present invention. That is, the present invention includes a step of growing a compound semiconductor crystal on an insulating crystal growth substrate to form a first composite consisting of the substrate and a compound semiconductor crystal thin film, and a step of growing the compound semiconductor crystal on an insulating substrate for permanent support. forming a glass layer that is lower than the melting point of the compound semiconductor crystal and whose coefficient of linear expansion is in the range of ±10×10 -7 /°C with respect to that of the substrate to form a second composite;
a step of bringing the first composite body and the second composite body into close contact so that the compound semiconductor crystal thin film of the former is in contact with the glass layer of the latter, and then heating them to a temperature of 900° C. or less to fuse the two; The present invention provides a method for manufacturing a compound semiconductor thin film structure in which the permanently supporting insulating substrate and the compound semiconductor thin film are integrated, the method comprising selectively removing only the crystal growth substrate of the first composite. be. In the method of the present invention, it is necessary to first form a thin film of compound semiconductor crystal on a predetermined crystal growth substrate and then transfer it onto the predetermined substrate via a low melting point glass layer. and without diffusing the compound semiconductor thin film into the glass.
Unable to transfer smoothly. Next, embodiments of the present invention will be outlined with reference to the accompanying drawings. 1A to 1D are explanatory diagrams of the manufacturing process of a structure according to the method of the present invention, and the reference numeral 1 in the figures is
2 is a compound semiconductor insulating crystal growth substrate, 2 is a compound semiconductor thin film, 3 is a substrate, and 4 is a low melting glass layer. First, as the first step, as shown in Figure 1A,
Selectively removable compound semiconductor crystal growth substrate 1
A crystal of a desired compound semiconductor thin film 2 is grown thereon, and as a second step, as shown in FIG. 1B,
A low melting glass layer 4 is formed on a suitable substrate 3. Next, as the third step, as shown in Figure 1C,
After the compound semiconductor thin film 2 on the crystal growth substrate and the low melting glass layer 4 on the base are brought into close contact, the glass layer is softened and bonded, and in the fourth and final step, the crystal growth substrate 1 is selected. Upon removal, a structure as shown in FIG. 1D is obtained. The structure obtained through this process has a compound semiconductor thin film formed on the substrate via a glass layer, and unlike conventional structures, it does not have an organic layer, making it extremely reliable. It is excellent. The crystal growth substrate used in the method of the present invention is one that allows the crystals of the compound semiconductor thin film to grow well, yet does not strongly adhere to the compound semiconductor thin film, or is soluble in a solution that does not dissolve the compound semiconductor thin film, And it is preferable that it is crystalline. Examples of such materials include mica, graphite, sodium chloride, potassium chloride, potassium bromide, sodium iodide, alum, and the like. In order to form a compound semiconductor thin film on the above-mentioned crystal growth substrate, normal vapor deposition (heater heating, EB
Methods such as heating), MBE, sputtering, and CVD are used. At this time, the thickness of the thin film is 200Å to 10μ.
A range of 500 Å to 2 μ is preferable in consideration of ease of transfer and characteristics. In the method of the present invention, a so-called low-melting glass is required as the glass used to form a glass layer having a softening point lower than the melting point of the compound semiconductor on the substrate, and the softening point (Ts) of this glass is
There is no particular restriction as long as it is lower than the melting point (Tm) of the compound semiconductor, but if it is too low, the heat resistance will not improve, so the softening point is generally 300
℃ or more and 20°C or more lower than Tm, more preferably 50°C or more lower than Tm. Further, the coefficient of thermal expansion of the glass used in the present invention needs to be close to the coefficient of thermal expansion of the substrate used, and if it is significantly different from the coefficient of thermal expansion of the substrate,
Unnecessary strain may be applied to the compound semiconductor thin film or the substrate may be damaged. Therefore, the linear expansion coefficient of glass is ±15× the linear expansion coefficient of the base material.
It is desirable that the temperature is in the range of 10 -7 /°C, preferably ±10×10 -1 /°C, preferably ±5×10 -7 /°C. Further, the glass used in the present invention preferably has a high insulation resistance, and when used as an electrical element, it is usually necessary to have a resistivity higher than 10 8 Ωcm. The material used as the insulating substrate for permanent support in the method of the present invention may be one that has a higher softening point than the glass used, but is stable in shape in the temperature range from the softening point of the glass to room temperature. Something is preferable. Examples of such materials include inorganic materials such as ceramics, and specific examples include alumina, ferrite, silicon nitride, quartz, sapphire, and borosilicate glass. In the method of the present invention, a typical method for forming a glass layer on a substrate is a method in which powdered glass is dispersed in a nitrocellulose binder or the like and then coated on the substrate and then fired. It will be done. In this case, in order to make the glass layer thickness uniform, the glass layer thickness is preferably 50 to 500 microns, more preferably 100 to 300 microns. In some cases, it is more preferable to make the glass layer thickness uniform by wrapping or the like. Another method of forming a glass layer on a substrate is
Methods include vapor deposition (heater heating, EB heating) and sputtering. In the case of vapor deposition, in order to control the composition of the deposited glass layer, several types of glass compositions are usually codeposited, and the film thickness is 1000 Å.
A range of ~10μ is preferred. Moreover, more preferable results can be obtained by forming this glass layer on both the substrate and the compound semiconductor thin film. Examples of methods for fusing the compound semiconductor thin film and the glass layer in the method of the present invention include heating in an electric furnace or high-frequency furnace. However, since it is better to keep only the glass layer under high temperature, It is preferable to carry out this process, and in some cases, it is preferable to carry out the process in an atmosphere of an inert gas such as argon or nitrogen. The temperature during bonding needs to be equal to or higher than the softening point of the glass, but if it is too close to the softening point, uneven bonding tends to occur, so it is preferably 10° C. or more higher than the softening point. However, if the heating temperature is too high or the glass is softened for too long, the compound semiconductor thin film will diffuse into the glass layer, making it impossible to achieve the original purpose. From the viewpoint of this diffusion, the upper limit of temperature and time limit vary depending on the physical properties of the compound semiconductor used. Removal of the crystal growth substrate in the method of the present invention is as follows:
This may be done by physical or chemical methods, depending on the type of substrate used. For example, when mica is used as a substrate, the substrate can be mechanically peeled off from a compound semiconductor thin film adhered to the substrate through glass, and when sodium chloride is used, water is used to dissolve only the sodium chloride. can be done. The structure manufactured by the method of the present invention has excellent reliability, and in particular has remarkable improvement in heat resistance compared to conventional structures. For example, structures using conventional epoxy adhesives lose their functionality as a structure because the adhesive burns at temperatures above 200°C, but structures using the low-volume glass of the present invention In this case, it will not lose its function as a structure even at high temperatures of around 400°C, depending on the glass used. Furthermore, an improvement in industrial productivity can be mentioned as a secondary effect of the present invention. That is, since the structure obtained by the present invention has excellent heat resistance,
Bonding using high melting point ball solder, which was impossible with conventional structures, is possible. In addition, with structures using conventional organic adhesives, ultrasonic bonding was impossible due to the presence of a soft adhesive layer, but the structure of the present invention has a hard glass layer and can be subjected to ultrasonic bonding. . Therefore, since the structure of the present invention allows the two types of bonding described above, whichever method is used, the bonding process can be automated, and industrial productivity can be greatly improved. Furthermore, the structure manufactured by the method of the present invention is
It can be processed into elements of various shapes. In other words, magnetoelectric conversion elements (Hall elements, Hall heads, magnetoresistive elements, etc.), junction transistors, field effect transistors, static induction transistors, piezoelectric elements, light emitting elements, temperature sensing elements, moisture sensing elements, and more. It is also possible to integrate it into an IC (integrated circuit). Next, the present invention will be explained in more detail with reference to Examples. In addition, in the embodiment of the present invention,
In order to mainly compare with Publication No. 45234, we will mainly discuss InSb-based compound semiconductor thin films.
Originally, the present invention is not limited to InSb-based thin films, for example, InAs, InP, GaAs, GaSb,
GaP or ternary GaxIn 1 −xSb, GaxAl 1
It can also be applied to thin films such as xAs and InSb 1 −xAsx. Example 1 In and Sb were deposited using mica as a substrate for crystal growth and a vacuum evaporation apparatus having two boats as a compound semiconductor thin film forming apparatus.
At this time, the substrate temperature was set to 440℃, and the degree of vacuum was set to 1.5×.
10 -6 Torr, set to 1μ in 30 minutes,
An InSb-based composite crystal thin film was manufactured. On the other hand, manufactured by Iwaki Glass Co., Ltd., the coefficient of linear expansion is 69×10 -7 /
℃ T191BF with nitrocellulose (Asahi Kasei H)
-20) It was dispersed in a 2% n-butyl acetate solution, applied to a 1 mm thick ferrite plate (3000L manufactured by Tohoku Kinzoku Co., Ltd.) with a coefficient of linear expansion of 75×10 -7 /°C, and fired at 650°C. The InSb-based composite crystal thin film obtained as described above and the low-melting glass layer were brought into close contact with each other and placed in an electric furnace with a 100 g weight placed thereon, and the temperature of the electric furnace was raised to 460°C. The temperature was then maintained at 460°C for 2 minutes, and then lowered, and when it reached 80°C, it was taken out and the mica was mechanically peeled off. The InSb-based CSTS thus obtained was processed into the pattern shown in FIG. 2, and the hole mobility was measured to be 4400 cm 2 /V·S at 20°C. Then this
When the hole mobility of CSTS was attempted to be measured at a high temperature of 280°C, it was found to be 1700 cm 2 /V·S. Comparative Example 1 After producing an InSb composite crystal thin film in the same manner as in Example 1, it was adhered to a 1 mm thick ferrite plate using an epoxy resin (ME-264 manufactured by Nippon Pernox Co., Ltd.), and the mica was mechanically peeled off. , and processed into the pattern shown in Figure 2. An attempt was made to measure the hole mobility of this sample at a high temperature of 250°C, but the film became crumbly and could not be measured. Example 2 Using sodium chloride as a substrate for crystal growth,
An InSb-based composite crystal thin film was manufactured using the same method as in Example 1. The InSb-based composite crystal thin film formed on this sodium chloride was
Iwaki Glass Co., Ltd. T-
After transferring using 191BF, sodium chloride was removed using water. After processing this structure into a Hall element, we measured the sensitivity of 100 elements and found that 40
It was ~56 mV/5 mA x 1K Gauss. The moisture resistance test of this element was carried out at 65℃ and 97% humidity for 12 hours and 25 hours.
When the test was carried out under conditions of 20 repetitions of a 12-hour dry-wet cycle at 65% °C, there was no change in sensitivity in 92 of them. Comparative Example 2 A Hall element was prepared in the same manner as in Example 2, except that epoxy resin (AER331 manufactured by Asahi Kasei Corporation) was used for transfer.
When 100 units were manufactured and a similar test was conducted, 73 of them showed no change in sensitivity. Example 3 Using the same equipment as in Example 1, an InAs thin film was manufactured by a three-temperature evaporation method. At this time, potassium bromide was used as the crystal growth substrate, and the substrate temperature was set at 550℃.
The degree of vacuum was set to 2×10 -6 Torr. On the other hand, manufactured by Corning, the coefficient of linear expansion is 89×10 -7 /℃
The same 1417 glass as in Example 1 was placed on a 0.5 mm thick alumina plate with a coefficient of linear expansion of 81×10 -7 /°C at 780°C.
After firing, wrapping was performed. At this time, the final glass layer thickness was 138-141μ. The InAs thin film obtained as described above and the low-melting glass layer were placed in close contact with each other, placed in an electric furnace with a 100 g weight placed thereon, and the atmosphere was made into an argon atmosphere.
The temperature was raised to ℃ and immediately lowered. Then, it was taken out at 50°C, and potassium bromide was removed using water. The InAs-based thin film structure thus obtained was patterned as shown in FIG. 2, and the hole mobility was measured to be 3400 cm 2 /V·S at 20°C. Also, the input resistance at 20℃ was 187Ω,
Furthermore, it can be measured even at high temperatures of 300℃.
Its value was 122Ω. Examples 4 to 6 and Comparative Examples 3 to 5 InSb-based composite crystal thin films were manufactured in the same manner as in Example 1 using mica as a substrate for crystal growth. Next, a ferrite plate with a thickness of 0.5 mm and a coefficient of linear expansion of 80 × 10 -7 /℃ was used as the base, and
7520, 8463, Iwaki Glass T-191BF, T-
Transfer was performed using 029 and 1200 manufactured by Asahi Glass Co., Ltd., and external evaluation (visual observation) of the obtained thin film structure was performed. The results are shown in Table 1.

【表】 実施例 7 実施例1と同様にして雲母基板上にInSb系複
合結晶薄膜を1μ成長させ、さらにイワキガラス
社製T−191BFをターゲツトとしてスパツタリン
グし、1μの薄膜を形成させた。 一方0.5mm厚の線膨張率が75×10-7/℃のフエ
ライト板をラツピングして表面を平滑にしたの
ち、イワキガラス社製、線膨張率が69×10-7/℃
のT−191BFをターゲツトとしたスパツタリング
を行い、2μの薄膜を形成した。 そして、このように形成されたT−191BF層同
志を密着し、500gの重錘をのせて、窒素雰囲気
の電気炉中で380℃、1分間の条件で転写したの
ち、雲母を剥離したところ、薄膜構造体を得るこ
とができた。この薄膜構造体を第2図のパターン
に加工してホール移動度を測定したところ、20℃
で5100cm2/V・Sといつた機能を有していた。さ
らに280℃の高温下でも1900cm2/V・Sの移動度
を有していた。
[Table] Example 7 An InSb composite crystal thin film of 1 μm was grown on a mica substrate in the same manner as in Example 1, and sputtering was performed using T-191BF manufactured by Iwaki Glass Co., Ltd. as a target to form a 1 μm thin film. On the other hand, after wrapping a 0.5 mm thick ferrite plate with a coefficient of linear expansion of 75×10 -7 /℃ to make the surface smooth, a plate made by Iwaki Glass Co., Ltd. with a coefficient of linear expansion of 69×10 -7 /℃ was wrapped.
Sputtering was performed using T-191BF as a target to form a 2μ thin film. Then, the T-191BF layers formed in this way were placed in close contact with each other, a 500 g weight was placed on them, and the transfer was performed at 380°C for 1 minute in an electric furnace in a nitrogen atmosphere, and then the mica was peeled off. A thin film structure could be obtained. When this thin film structure was processed into the pattern shown in Figure 2 and the hole mobility was measured, it was found that
It had a function of 5100cm 2 /V・S. Furthermore, it had a mobility of 1900 cm 2 /V·S even at a high temperature of 280°C.

【図面の簡単な説明】[Brief explanation of drawings]

第1図A〜Dは、本発明方法による薄膜構造体
の製造工程の説明図であつて、図中符号1は化合
物半導体の結晶成長用基板、2は化合物半導体薄
膜、3は基体、4は低溶融ガラス層である。 第2図は、本発明方法によつて製造された
CSTSの電気特性を測定するために用いたパター
ンであつて、図中符号a,a′は入力電極であり、
b,b′は出力電極である。
1A to 1D are explanatory diagrams of the manufacturing process of a thin film structure according to the method of the present invention, in which reference numeral 1 is a compound semiconductor crystal growth substrate, 2 is a compound semiconductor thin film, 3 is a substrate, and 4 is a substrate for crystal growth of a compound semiconductor. It is a low melting glass layer. Figure 2 shows a sample produced by the method of the present invention.
This is a pattern used to measure the electrical characteristics of CSTS, and symbols a and a' in the figure are input electrodes,
b and b' are output electrodes.

Claims (1)

【特許請求の範囲】[Claims] 1 絶縁性の結晶成長用基板上に、化合物半導体
結晶を成長させて基板と化合物半導体結晶薄膜か
ら成る第一複合体とする工程、永久支持するため
の絶縁性基体上に該化合物半導体結晶の融点より
低くかつ、その線膨張係数が基体のそれに対して
±10×10-7/℃の範囲にあるガラス層を形成させ
て第二複合体とする工程、第一複合体と第二複合
体とを前者の化合物半導体結晶薄膜と後者のガラ
ス層とが接触するように密着させたのち、900℃
以下の温度に加熱して両者を融着させる工程、及
び第一複合体の結晶成長用基板のみを選択的に除
去することからなり、前記永久支持用絶縁性基体
と化合物半導体薄膜とが一体となつた化合物半導
体薄膜構造体の製造方法。
1. A step of growing a compound semiconductor crystal on an insulating substrate for crystal growth to form a first composite consisting of the substrate and a thin film of the compound semiconductor crystal, and growing the compound semiconductor crystal on an insulating substrate for permanent support at the melting point of the compound semiconductor crystal. a step of forming a second composite by forming a glass layer whose linear expansion coefficient is lower than that of the substrate within the range of ±10×10 -7 /°C; the first composite and the second composite; The former compound semiconductor crystal thin film was brought into close contact with the latter glass layer, and then heated at 900°C.
The permanent support insulating substrate and the compound semiconductor thin film are integrated into a A method for manufacturing a compound semiconductor thin film structure.
JP57018374A 1982-02-08 1982-02-08 Manufacture for compound semiconductor of thin film structure Granted JPS58135628A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57018374A JPS58135628A (en) 1982-02-08 1982-02-08 Manufacture for compound semiconductor of thin film structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57018374A JPS58135628A (en) 1982-02-08 1982-02-08 Manufacture for compound semiconductor of thin film structure

Publications (2)

Publication Number Publication Date
JPS58135628A JPS58135628A (en) 1983-08-12
JPH0419699B2 true JPH0419699B2 (en) 1992-03-31

Family

ID=11969931

Family Applications (1)

Application Number Title Priority Date Filing Date
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Country Status (1)

Country Link
JP (1) JPS58135628A (en)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4891329A (en) * 1988-11-29 1990-01-02 University Of North Carolina Method of forming a nonsilicon semiconductor on insulator structure
US7687372B2 (en) * 2005-04-08 2010-03-30 Versatilis Llc System and method for manufacturing thick and thin film devices using a donee layer cleaved from a crystalline donor
JP5409033B2 (en) * 2008-02-18 2014-02-05 株式会社半導体エネルギー研究所 Method for manufacturing semiconductor device
CN112687799B (en) * 2020-12-19 2022-10-11 复旦大学 Transfer manufacturing method of high-crystallinity semiconductor film

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4894368A (en) * 1972-03-13 1973-12-05

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4894368A (en) * 1972-03-13 1973-12-05

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