JP3207957B2 - Method for forming InSb thin film - Google Patents

Method for forming InSb thin film

Info

Publication number
JP3207957B2
JP3207957B2 JP00258693A JP258693A JP3207957B2 JP 3207957 B2 JP3207957 B2 JP 3207957B2 JP 00258693 A JP00258693 A JP 00258693A JP 258693 A JP258693 A JP 258693A JP 3207957 B2 JP3207957 B2 JP 3207957B2
Authority
JP
Japan
Prior art keywords
thin film
forming
insb thin
substrate
heat treatment
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP00258693A
Other languages
Japanese (ja)
Other versions
JPH06209130A (en
Inventor
則子 大橋
俊夫 松田
秀卓 橋本
勝司 多良
本吉  要
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Corp
Panasonic Holdings Corp
Original Assignee
Panasonic Corp
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Panasonic Corp, Matsushita Electric Industrial Co Ltd filed Critical Panasonic Corp
Priority to JP00258693A priority Critical patent/JP3207957B2/en
Publication of JPH06209130A publication Critical patent/JPH06209130A/en
Application granted granted Critical
Publication of JP3207957B2 publication Critical patent/JP3207957B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Landscapes

  • Physical Vapour Deposition (AREA)
  • Thin Magnetic Films (AREA)
  • Hall/Mr Elements (AREA)

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【産業上の利用分野】この発明はホール素子の製造方法
などにおいて用いられるInSb薄膜形成方法に関する
ものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming an InSb thin film used in a method for manufacturing a Hall element.

【0002】[0002]

【従来の技術】磁電変換素子、特にホール素子は、小型
で信頼性が高く、ビデオやオーディオのモータのブラシ
の代わりや、自動車の回転センサなど様々な用途に幅広
く応用されている。このホール素子は、GaAsやIn
Sbの素材を用いたもので、活性層GaAsの場合は
イオン注入で形成し、InSbの場合は真空蒸着で形成
するという方法に大別される。前者は禁止帯幅が大きく
温度特性に優れ、温度特性が重視される自動車等の分野
で用いられるのに対し、後者は電子の移動度が大きく磁
気感度に優れ、消費電力を重視する分野で用いられる。
2. Description of the Related Art Magnetoelectric conversion elements, particularly Hall elements, are small and highly reliable, and have been widely applied to various uses such as replacements for brushes of video and audio motors and rotation sensors for automobiles. This Hall element is made of GaAs or In.
The method uses a material of Sb. If the active layer is GaAs, it is formed by ion implantation, and if the active layer is InSb, it is formed by vacuum deposition. The former is used in fields such as automobiles where the forbidden bandwidth is large and excellent in temperature characteristics, and the temperature characteristics are important, while the latter is used in fields where electron mobility is large and excellent in magnetic sensitivity and power consumption is important. Can be

【0003】従来のInSb薄膜形成方法は、図4に示
すように、雲母等の絶縁性基板41上にInおよびSb
を各々の蒸着源からInSbの融点付近の周囲温度で蒸
着してInSb薄膜42を形成し、電極43を形成し、
プラスチックパッケージにモールドを行う。
As shown in FIG. 4, a conventional method for forming an InSb thin film employs a method of forming In and Sb on an insulating substrate 41 such as mica.
From each deposition source at an ambient temperature near the melting point of InSb to form an InSb thin film 42, form an electrode 43,
Mold on plastic package.

【0004】[0004]

【発明が解決しようとする課題】InとSbの2元化合
物であるInSbを真空蒸着のみで形成する場合、Sb
の蒸気圧が高いため周囲真空度の制御が必要であつた。
また、n形の活性層を形成するためInとSbの蒸着レ
ートの厳密な制御が必要であり、極めて制御された条件
下での製造であった(たとえば、真空度の制御について
は、特願昭56−177394号公報;蒸着レートの制
御については、特願昭56−50294号公報)。
When InSb, which is a binary compound of In and Sb, is formed by vacuum deposition only,
Because of the high vapor pressure, control of the ambient vacuum was required.
Further, in order to form an n-type active layer, strict control of the deposition rate of In and Sb is required, and the production was performed under extremely controlled conditions (for example, the control of the degree of vacuum was disclosed in Japanese Patent Application No. 2006-163873). JP-A-56-177394; control of the evaporation rate is disclosed in Japanese Patent Application No. 56-50294.

【0005】また、従来技術では低温蒸着すると結晶性
が悪く、低温蒸着後に熱処理をするとSbが抜け組成制
御が困難になるため、高温蒸着しなければならない。ま
た、高温蒸着のため、蒸着する素材全面にわたって蒸着
し、その後エッチングで活性層の形成を行わなければな
らず、その際のエッチングバラツキによるオフセット電
圧の増大という問題があつた。
In the prior art, low-temperature deposition causes poor crystallinity, and heat treatment after low-temperature deposition removes Sb, making it difficult to control the composition. Therefore, high-temperature deposition must be performed. In addition, since high-temperature deposition is performed, the active layer must be formed by vapor deposition over the entire surface of the material to be vapor-deposited, and thereafter, there is a problem in that the offset voltage increases due to variations in etching.

【0006】また、蒸着基板としては雲母結晶の配向性
が重要であり、SiO2 (ガラス)上ではうまく成膜す
ることができなかった。さらに、従来技術の雲母等の素
材上では、プレーナ構造で差動アンプやシュミット回路
を形成することができず、モノリシックIC化ができな
かった。この発明の目的は、Si基板上に安定なInS
b薄膜を容易に得ることができるInSb薄膜形成方法
を提供することである。
Further, the orientation of mica crystals is important for a deposition substrate, and a film cannot be successfully formed on SiO 2 (glass). Furthermore, on a conventional material such as mica, a differential amplifier or a Schmitt circuit cannot be formed in a planar structure, and a monolithic IC cannot be formed. An object of the present invention is to provide a stable InS
An object of the present invention is to provide an InSb thin film forming method capable of easily obtaining a b thin film.

【0007】[0007]

【0008】[0008]

【課題を解決するための手段】本発明のInSb薄膜形
成方法は、Si基板表面に0.1μm以上2μm以下の
凹凸を形成した後、前記Si基板表面に絶縁膜を形成
し、前記絶縁膜上にInSb薄膜を蒸着により形成する
ことを特徴とする。この際、ウェットエッチングまたは
ドライエッチングによりSi基板表面に凹凸を形成する
ことが好ましい。
InSb thin film forming method of the present invention According to an aspect of the, 0.1 [mu] m or more 2μm following the Si substrate surface
After forming the irregularities, an insulating film is formed on the surface of the Si substrate.
Forming an InSb thin film on the insulating film by vapor deposition;
It is characterized by the following. At this time, wet etching or
Forming irregularities on the Si substrate surface by dry etching
Is preferred.

【0009】[0009]

【0010】[0010]

【0011】[0011]

【作用】本発明のInSb薄膜形成方法によれば、Si
基板の凹凸に対応した凹凸が絶縁膜表面に残るため、凹
凸が蒸着中のIn同士の結合を分散させることができ、
その結果InとSbの結合が促進されることになり、し
たがってSi基板上に容易に安定にInおよびSbを蒸
着することができる
According to the method of forming an InSb thin film of the present invention , Si
Since unevenness corresponding to the unevenness of the substrate remains on the insulating film surface,
The protrusions can disperse the bonds between In during vapor deposition,
As a result, the bonding between In and Sb is promoted, and
Therefore, In and Sb can be easily and stably deposited on the Si substrate .

【0012】[0012]

【0013】[0013]

【実施例】図1はこの発明の一実施例のInSb薄膜形
成方法により形成したホール素子の断面図を示すもので
ある。約1.3ミクロンの凹凸程度の研磨仕上げまたは
ウェットエッチングやドライエッチングによりSi基板
1上に凹凸を形成した後、SiO2 またはプラズマSi
34 等の絶縁膜2を形成し、その上にInおよびSb
を各々の蒸着源から蒸着することにより、InSb薄膜
3を形成する。絶縁膜2の表面には、Si基板1の凹凸
に対応した凹凸が残り、この絶縁膜2の凹凸面にInS
b薄膜3が形成される。
FIG. 1 is a sectional view of a Hall element formed by a method of forming an InSb thin film according to one embodiment of the present invention. After forming irregularities on the Si substrate 1 by polishing finish of about 1.3 microns irregularities or wet etching or dry etching, SiO 2 or plasma Si is formed.
3 to form an insulating film 2 of N 4 or the like, In and Sb thereon
Is deposited from each deposition source to form the InSb thin film 3. Unevenness corresponding to the unevenness of the Si substrate 1 remains on the surface of the insulating film 2, and the uneven surface of the insulating film 2 has InS
The b thin film 3 is formed.

【0014】この際、蒸着温度は常温から融点付近まで
幅広い範囲の任意の温度で可能である。蒸着後、SiO
2 やプラズマSi34 でInおよびSbの各々の蒸着
源から蒸着した素材の表面に熱処理保護膜5を形成す
る。この熱処理保護膜5を形成した後、熱処理を行う。
この熱処理は、2段階以上の温度領域の熱処理である。
熱処理後にホール素子を形成した後、同ウェハ内のSi
基板上に形成された差動アンプやシュミット回路と配線
金属で結線を行いパッケージにモールドする。
At this time, the deposition temperature can be any temperature in a wide range from room temperature to around the melting point. After evaporation, SiO
A heat treatment protective film 5 is formed on the surface of a material deposited from In and Sb deposition sources with 2 or plasma Si 3 N 4 . After forming the heat treatment protection film 5, heat treatment is performed.
This heat treatment is a heat treatment in two or more temperature ranges.
After forming the Hall element after the heat treatment, the Si
The differential amplifier and Schmitt circuit formed on the substrate are connected with wiring metal and molded into a package.

【0015】実験において、凹凸のないSi基板上に蒸
着すると、Inの結晶化のみが進み安定なInSbを形
成することができなかつた。このことは1ミクロン程度
の凹凸が蒸着中のIn同士の結合を分散させInとSb
の結合を促進するためと考えられる。上記の凹凸の大き
さは、0.1ミクロン以上、2ミクロン以下が好まし
い。
In an experiment, when vapor deposition was performed on a Si substrate having no irregularities, only crystallization of In proceeded and stable InSb could not be formed. This means that irregularities of about 1 micron disperse the bonding between In during the deposition and cause In and Sb
It is thought to promote the binding of The size of the irregularities is preferably 0.1 μm or more and 2 μm or less.

【0016】蒸着後、熱処理を行いInとSbの結合を
進める際、Sbは蒸気圧が高く大気圧中では図2(a)
に示すように、表面のSbは蒸発する。そこで、SiO
2 やプラズマSi34 をInおよびSbの各々の蒸着
源から蒸着した素材の表面に保護膜として形成すること
で、図2(b)に示すように、熱処理中のSbの蒸発を
防止する。
After the vapor deposition, when heat treatment is performed to promote the bonding between In and Sb, the vapor pressure of Sb is high and Sb has a high vapor pressure at atmospheric pressure as shown in FIG.
As shown in the figure, Sb on the surface evaporates. Therefore, SiO
2 and plasma Si 3 N 4 are formed as a protective film on the surface of the material deposited from the respective sources of In and Sb, thereby preventing Sb from evaporating during the heat treatment, as shown in FIG. .

【0017】この際の熱処理の温度は、2段階以上の温
度領域の熱処理により高移動度を得ることが、図3より
分かる。図3において、曲線Aは熱処理温度を420℃
の1段階のみとした場合の電子の移動度を示し、曲線B
は熱処理温度を300℃と420℃の2段階とした場合
の電子の移動度を示す。2段階以上の熱処理により高移
動度が得られるのは、第1段階で蒸着時のダメージを回
復し第2段階以降でInとSbの結合が促進されるもの
と推定される。
It can be seen from FIG. 3 that a high mobility can be obtained by heat treatment in two or more temperature ranges. In FIG. 3, a curve A indicates a heat treatment temperature of 420 ° C.
Shows the electron mobility when only one stage is used, and curve B
Indicates the mobility of electrons when the heat treatment temperature is set at two stages of 300 ° C. and 420 ° C. It is presumed that high mobility can be obtained by two or more stages of heat treatment because damage during vapor deposition is recovered in the first stage and the bonding between In and Sb is promoted in the second and subsequent stages.

【0018】上記の形成方法により室温での移動度とし
て20000cm2 /V・sec という高移動度の膜質を得
ることが可能となる。なお、1段階の熱処理でも2段階
以上の熱処理に比べて多少特性は劣るものの、必要な特
性は得ることができる。その後、電極4を形成し、さら
にその上に保護膜6を形成する。
According to the above-mentioned forming method, it is possible to obtain a film quality having a high mobility of 20,000 cm 2 / V · sec at room temperature. In addition, even though the heat treatment in one stage is slightly inferior to the heat treatment in two or more stages, necessary characteristics can be obtained. Thereafter, an electrode 4 is formed, and a protective film 6 is further formed thereon.

【0019】上記の方法によれば、蒸着時の雰囲気温度
が室温から融点まで広く設定することが可能で、蒸着時
レジストを用い所望のパターニングを行い、パターニン
グを行った領域にInおよびSbを各々の蒸着源から蒸
着し、蒸着後リフトオフで所望の活性層を形成した後、
熱処理を行う製造方法が容易にできる。この方法による
と、エッチングムラによるオフセット電圧を抑えること
ができる。
According to the above-mentioned method, the ambient temperature at the time of vapor deposition can be set widely from room temperature to the melting point. At the time of vapor deposition, desired patterning is performed, and In and Sb are respectively deposited in the patterned regions. After evaporation from the evaporation source, after forming a desired active layer by lift-off after evaporation,
A manufacturing method for performing heat treatment can be easily performed. According to this method, an offset voltage due to uneven etching can be suppressed.

【0020】また、このようにしてできた蒸着膜は、同
ウェハ内のSi基板上に形成された差動アンプやシュミ
ット回路と配線金属での結線が容易で高感度のホールI
Cの製品化が可能となる。
Further, the deposited film thus formed can be easily connected to a differential amplifier or a Schmitt circuit formed on a Si substrate in the same wafer by a wiring metal and has a high sensitivity.
C can be commercialized.

【0021】[0021]

【発明の効果】以上のように、この発明のInSb薄膜
形成方法によれば、Si基板の凹凸に対応した凹凸が絶
縁膜表面に残るため、凹凸が蒸着中のIn同士の結合を
分散させることができ、その結果InとSbの結合が促
進されることになり、したがって、Si基板上に安定
nSbの薄膜形成が可能となり、高歩留まりの安価な
製品の供給が可能となる。また、集積化が可能となり、
多機能のデバイスが実現し、セットの小型化に寄与する
ことができる。
As described above, according to the InSb thin film forming method of the present invention , irregularities corresponding to the irregularities of the Si substrate are completely eliminated.
Since it remains on the surface of the edge film, unevenness may cause bonding between In during vapor deposition.
Can be dispersed, so that the bonding between In and Sb is promoted.
Will proceed to the fact, therefore, stable on Si substrate
Forming a thin film of I NSB is possible, it is possible to supply an inexpensive product of high yield. In addition, integration becomes possible,
A multifunctional device is realized, which can contribute to downsizing of the set.

【図面の簡単な説明】[Brief description of the drawings]

【図1】この発明のInSb薄膜形成方法により形成し
たホール素子の断面図である。
FIG. 1 is a sectional view of a Hall element formed by an InSb thin film forming method of the present invention.

【図2】この発明のInSb薄膜形成方法により形成し
た蒸着膜の深さ方向のInおよびSbの分布図である。
FIG. 2 is a distribution diagram of In and Sb in a depth direction of a deposited film formed by the method of forming an InSb thin film of the present invention.

【図3】この発明のInSb薄膜形成方法による蒸着膜
の熱処理による移動度への影響を示す図である。
FIG. 3 is a diagram showing the influence of the heat treatment of the deposited film on the mobility by the InSb thin film forming method of the present invention.

【図4】従来のInSb薄膜形成方法により形成したホ
ール素子の断面図である。
FIG. 4 is a cross-sectional view of a Hall element formed by a conventional InSb thin film forming method.

【符号の説明】[Explanation of symbols]

1 Si基板 2 絶縁膜 3 InSb薄膜 4 電極 5 熱処理保護膜 DESCRIPTION OF SYMBOLS 1 Si substrate 2 Insulating film 3 InSb thin film 4 Electrode 5 Heat treatment protective film

───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.7 識別記号 FI H01L 43/08 H01L 43/08 S 43/12 43/12 (72)発明者 多良 勝司 大阪府門真市大字門真1006番地 松下電 子工業株式会社内 (72)発明者 本吉 要 大阪府門真市大字門真1006番地 松下電 子工業株式会社内 (56)参考文献 特開 昭59−46077(JP,A) 特開 昭49−69074(JP,A) 特開 昭49−107187(JP,A) (58)調査した分野(Int.Cl.7,DB名) H01L 43/14 C23C 14/14 H01F 10/08 H01F 10/26 H01L 43/06 H01L 43/08 H01L 43/12 JICSTファイル(JOIS)──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. 7 Identification code FI H01L 43/08 H01L 43/08 S 43/12 43/12 (72) Inventor Katsushi Tara 1006 Kadoma Kadoma, Kadoma City, Osaka Matsushita Electric (72) Inventor: Motoyoshi Yoshimoto, 1006 Kadoma, Kazuma, Osaka Pref. Matsushita Electronics Corporation (56) References JP-A-59-46077 (JP, A) JP-A-49-69074 ( JP, A) JP-A-49-107187 (JP, A) (58) Fields investigated (Int. Cl. 7 , DB name) H01L 43/14 C23C 14/14 H01F 10/08 H01F 10/26 H01L 43 / 06 H01L 43/08 H01L 43/12 JICST file (JOIS)

Claims (2)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】 Si基板表面に0.1μm以上2μm以
下の凹凸を形成した後、前記Si基板表面に絶縁膜を形
成し、前記絶縁膜上にInSb薄膜を蒸着により形成す
ることを特徴とするInSb薄膜形成方法。
1. The method according to claim 1, wherein the surface of the Si substrate has a thickness of 0.1 μm or more and
After forming the lower irregularities, an insulating film is formed on the surface of the Si substrate.
And forming an InSb thin film on the insulating film by vapor deposition.
A method for forming an InSb thin film, comprising:
【請求項2】 ウェットエッチングまたはドライエッチ
ングによりSi基板表面に凹凸を形成することを特徴と
する請求項1記載のInSb薄膜形成方法
2. A wet etching or a dry etching.
Forming irregularities on the Si substrate surface by
The method for forming an InSb thin film according to claim 1 .
JP00258693A 1993-01-11 1993-01-11 Method for forming InSb thin film Expired - Fee Related JP3207957B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP00258693A JP3207957B2 (en) 1993-01-11 1993-01-11 Method for forming InSb thin film

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP00258693A JP3207957B2 (en) 1993-01-11 1993-01-11 Method for forming InSb thin film

Publications (2)

Publication Number Publication Date
JPH06209130A JPH06209130A (en) 1994-07-26
JP3207957B2 true JP3207957B2 (en) 2001-09-10

Family

ID=11533485

Family Applications (1)

Application Number Title Priority Date Filing Date
JP00258693A Expired - Fee Related JP3207957B2 (en) 1993-01-11 1993-01-11 Method for forming InSb thin film

Country Status (1)

Country Link
JP (1) JP3207957B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103647022A (en) * 2013-12-25 2014-03-19 杭州士兰集成电路有限公司 Anisotropic magneto resistive sensor vertical structure and manufacturing method thereof

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002299599A (en) * 2001-04-02 2002-10-11 Asahi Kasei Corp Integrated magnetic sensor and its manufacturing method
JP4480318B2 (en) * 2002-02-13 2010-06-16 旭化成エレクトロニクス株式会社 Composite semiconductor device and manufacturing method thereof

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103647022A (en) * 2013-12-25 2014-03-19 杭州士兰集成电路有限公司 Anisotropic magneto resistive sensor vertical structure and manufacturing method thereof
CN103647022B (en) * 2013-12-25 2016-04-27 杭州士兰集成电路有限公司 Anisotropic magneto resistive sensor vertical structure and manufacture method thereof

Also Published As

Publication number Publication date
JPH06209130A (en) 1994-07-26

Similar Documents

Publication Publication Date Title
JP2685819B2 (en) Dielectric isolated semiconductor substrate and manufacturing method thereof
JP3207957B2 (en) Method for forming InSb thin film
JP2841381B2 (en) Method for manufacturing thin film transistor
JPH04109623A (en) Semiconductor device with p-n junction
JP2653092B2 (en) Complementary thin film transistor and method of manufacturing the same
JP3158588B2 (en) Transfer formation method of InSb thin film
JP2857456B2 (en) Method for manufacturing semiconductor film
JPH03104209A (en) Manufacture of semiconductor device
JPS6211781B2 (en)
JP3216173B2 (en) Method of manufacturing thin film transistor circuit
JPS6292327A (en) Semiconductor device and manufacture thereof
JPH0412629B2 (en)
JP2844963B2 (en) Semiconductor device and manufacturing method thereof
JPH022174A (en) Manufacture of polymer electronics device
JP3169654B2 (en) Method for manufacturing semiconductor device
JPH0442577A (en) Thin film transistor
JPH07122752A (en) Manufacture of thin film transistor
JPH06164017A (en) Manufacture of semiconductor thin-film magneto resistance element
JPS61231765A (en) Manufacture of thin film semiconductor device
JPH04332131A (en) Semiconductor device
KR100206773B1 (en) An epitaxial ferroelectric field effect transistor and a method of fabricating the same
JPH02268443A (en) Semiconductor device
JPS62145768A (en) Structure of soi film
JPH07130979A (en) Semiconductor device and its manufacture
JPH04276652A (en) Semiconductor device

Legal Events

Date Code Title Description
LAPS Cancellation because of no payment of annual fees