JP4480318B2 - Composite semiconductor device and manufacturing method thereof - Google Patents

Composite semiconductor device and manufacturing method thereof Download PDF

Info

Publication number
JP4480318B2
JP4480318B2 JP2002036017A JP2002036017A JP4480318B2 JP 4480318 B2 JP4480318 B2 JP 4480318B2 JP 2002036017 A JP2002036017 A JP 2002036017A JP 2002036017 A JP2002036017 A JP 2002036017A JP 4480318 B2 JP4480318 B2 JP 4480318B2
Authority
JP
Japan
Prior art keywords
compound semiconductor
integrated circuit
thin film
semiconductor element
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2002036017A
Other languages
Japanese (ja)
Other versions
JP2003243646A (en
Inventor
隆行 渡辺
浩二 川口
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Asahi Kasei EMD Corp
Original Assignee
Asahi Kasei EMD Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Asahi Kasei EMD Corp filed Critical Asahi Kasei EMD Corp
Priority to JP2002036017A priority Critical patent/JP4480318B2/en
Publication of JP2003243646A publication Critical patent/JP2003243646A/en
Application granted granted Critical
Publication of JP4480318B2 publication Critical patent/JP4480318B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Description

【0001】
【発明の属する技術分野】
本発明は、化合物半導体素子と集積回路(IC)が複合化された複合半導体素子及びその製造方法に関し、より詳細には、InSbなどを活性層としたホール素子と集積回路が複合化されたホールICおよびInSbなどの化合物半導体薄膜を集積回路上に転写する技術に関する。
【0002】
【従来の技術】
高い電子移動度を有するInSb、InAs、GaAsなどの化合物半導体は、高感度ホール素子や高速電子デバイスの材料として適している。また、これら素子と信号処理機能を有する集積回路とを組み合わせた複合半導体素子があり、例えば、特開昭61−226982号公報で記載されているInSbホール素子とSiの集積回路とからなるホールICが良く知られている。これらホールICは、ホール素子部と信号処理部が同一の基板に形成されるSiモノリシックホールICと比較して、磁界に対する感度が高いという利点がある。
【0003】
【発明が解決しようとする課題】
しかしながら、前述したホールICでは、ホール素子とICをリードフレーム上に別々に配置して、それら素子の電極間をワイヤで接続するため、SiモノリシックホールICと比べるとサイズが大きいという問題があった。
【0004】
小型ホールICを実現するために、IC上にホール素子を配置する構造が考えられる。例えば、特開昭49−91196号公報では、増幅用トランジスタが形成された半導体基体(IC基板)上に絶縁層を介して化合物半導体の感磁気部が形成された感磁気素子が提案されている。具体的な化合物半導体薄膜の形成方法としては、スパッタ、蒸着などによりSiOなどの絶縁層上に直接形成することが記述されている。
【0005】
上述した化合物半導体薄膜の形成方法においては、ICが基板であるため形成温度に制約を受けること、回路が形成されているために基板の凹凸が大きいこと、さらに絶縁層の上に直接堆積させることが原因で、高電子移動度を有する高品質な化合物半導体薄膜を形成することは困難であった。したがって、化合物半導体を用いるにもかかわらず、高感度ホール素子を作製することができず、SiモノリシックホールICに対する優位性が著しく減少してしまった。
【0006】
本発明は、このような問題に鑑みてなされたもので、その目的とするところは、InSbをセンサ部としたホールICなど、化合物半導体素子とICを組み合わせた複合半導体素子において、化合物半導体の特性を活かしつつ小型化を実現できるようにした複合半導体素子及びその製造方法を提供することにある。
【0007】
【課題を解決するための手段】
本発明は、このような目的を達成するために、請求項1に記載の発明は、化合物半導体素子と集積回路とが電気的に接続されている複合半導体素子において、前記化合物半導体素子が前記集積回路上に接着剤を介して転写接着され、前記集積回路の電極パッドのみが露出された後、前記化合物半導体の端子と、前記集積回路の電極パッドとが電気的に接続する積層体の接続電極とを備え、前記化合物半導体素子が、In X1 Ga 1−X1 As Y1 Sb 1−Y1 (0≦X1≦1、0≦Y1≦1)を活性層とするホール素子であることを特徴とする。
【0009】
また、請求項に記載の発明は、請求項1に記載の発明において、前記積層体が金とチタンとからなる積層体であることを特徴とする。
また、請求項に記載の発明は、化合物半導体素子と集積回路とが電気的に接続されている複合半導体素子の製造方法において、基板上に形成された化合物半導体薄膜を前記集積回路上に接着剤を介して転写接着した後、前記基板を前記化合物半導体薄膜から除去する工程と、フォトリソグラフィー法により前記化合物半導体を所定の形状にエッチングする工程と、前記集積回路の電極パッドのみを露出する工程と、該電極パッドと前記化合物半導体の前記所定の形状の入出端子とを電気的に接続する積層体の接続電極を形成する工程とを有し、前記化合物半導体薄膜が、雲母基板上に蒸着形成されたIn X1 Ga 1−X1 As Y1 Sb 1−Y1 (0≦X1≦1、0≦Y1≦1)であることを特徴とする。
【0012】
このように、本発明者らは、上記課題を解決するために鋭意検討を重ねた結果、好適な基板上に好適な条件で形成された化合物半導体薄膜をIC上に接着剤を介して転写接着し、化合物半導体素子を形成した後、ICと電気的に接続することにより、IC上に化合物半導体素子が配置された複合半導体素子を作製することができ、化合物半導体特有の性能(ホール素子においては高感度)を達成しながら、小型化をも兼ね備えた複合半導体素子の実現に有効であることを見い出し、本発明をなすに至った。
【0013】
【発明の実施の形態】
以下、図面を参照して本発明の実施の形態について説明する。
図1は、本発明の複合半導体素子の断面構造図で、図中符号1は集積回路、1aは回路が形成された基板、1bは電極パッド、2は化合物半導体素子、3は接着剤、4は化合物半導体素子と集積回路を結ぶ接続電極を示している。
【0014】
図2(a)〜(f)は、本発明の複合半導体素子の作製プロセスを示す図である。まず、集積回路1上に接着剤3を塗布して(a)、薄膜形成用の基板5に形成された化合物半導体薄膜2aを接着剤3の上に貼り付ける(b)。その後、基板5を除去(c)してからパターンニングして化合物半導体素子2の形状に加工する(d)。さらに、電極パッド1b上の接着剤3を除去し(e)、次いで、接続電極4を形成(f)して化合物半導体素子と集積回路を接続することにより複合半導体素子を作製する。
【0015】
本発明における化合物半導体薄膜の形成は、化合物半導体薄膜に適合した薄膜形成用基板を選択し、好適な温度条件で実施することができる。したがって、化合物半導体材料が本来有する高い電子移動度を実現することができ、上述した特開昭49−91196号公報に記載されている集積回路基板上に化合物半導体薄膜が直接形成された構造の場合と異なる点である。
【0016】
図3は、本発明におけるパッケージされた複合半導体素子の上面図で、図中符号6は集積回路、7は化合物半導体素子、8はリードフレーム、9はワイヤ、10はモールドパッケージを示している。これは、化合物半導体素子と集積回路とをワイヤで接続した従来の複合半導体素子と比較して著しく小型化されている。
【0017】
つまり、本発明は、化合物半導体素子2と集積回路1とが電気的に接続されている複合半導体素子において、前記化合物半導体素子2が前記集積回路1上に接着剤3を介して接着されていることを特徴としている。
【0018】
また、本発明は、化合物半導体素子がInX1Ga1−X1AsY1Sb1−Y1(0≦X1≦1、0≦Y1≦1)を活性層とするホール素子であること特徴とする複合半導体素子である。
【0019】
本発明において、化合物半導体素子の機能、構造および材料は特に限定されるものではないが、ホール素子である場合の化合物半導体材料としては、InX1Ga1−X1AsY1Sb1−Y1(0≦X1≦1、0≦Y1≦1)が、電子移動度が高くので好ましい。また、化合物半導体素子はバルクの形態であっても薄膜の形態であってもよく、特に限定されるものではない。例えば、化合物半導体がInSbの場合、InSbバルクであっても、GaAs基板上に形成されたInSb薄膜であっても構わないが、素子の厚みを薄くするためには、集積回路上に接着した後、薄膜形成用基板を除去することが好ましい。薄膜形成用基板として、雲母を使用するとInSb、InAs薄膜の電子移動度は高いものが得られ、また接着後、雲母基板を容易に剥離除去することができることから極めて好ましい。
【0020】
つまり、本発明は、化合物半導体素子と集積回路とが電気的に接続されている複合半導体素子の製造方法において、基板上に形成された化合物半導体薄膜を前記集積回路上に接着剤を介して接着した後、前記基板を前記化合物半導体薄膜から除去する工程を有する有することを特徴とする複合半導体素子の製造方法である。
【0021】
また、本発明は、前記化合物半導体薄膜が雲母基板上に蒸着形成されたInX1Ga1−X1AsY1Sb1−Y1(0≦X1≦1、0≦Y1≦1)であることを特徴とする複合半導体素子の製造方法である。
【0022】
また、本発明は、前記基板を前記化合物半導体薄膜から除去した後、化合物半導体薄膜を所定の形状にエッチング法により加工する工程と、その後、少なくとも集積回路の電極パッド部上の接着剤を除去し、化合物半導体薄膜と集積回路の電極パッドを導体薄膜で接続する工程を有することを特徴とする複合半導体素子の製造方法である。
【0023】
本発明における接着剤材料としては、特に限定されるものではないが、プロセスの容易さ、耐熱性の観点からエポキシ系樹脂などの熱硬化性樹脂が好ましい。また、接着剤の塗布方法については、特に限定されるものではないが、薄く均一に塗布できることからスピンコート法が好ましい。この方法で塗布する場合は、低粘度の樹脂を接着剤材料として選択することが好ましい。
【0024】
また、本発明における集積回路の基板材料としては、特に限定されるものではないが、一般的にSiまたはGaAsが用いられ、用途によって選択することができる。
【0025】
以下に、本発明の具体的な実施例について説明する。
図1に示す複合半導体素子を図2に示す工程により作製した。
まず、Si基板に形成した集積回路1上に接着剤3としてのエポキシ系樹脂をスピンコートにより約2μmの厚さで塗布した(a)。次に、雲母基板5に真空蒸着法により形成した膜厚1μmのInSb薄膜2aを接着剤の上に貼り付け、恒温槽内でエポキシを熱硬化させSi集積回路とInSb薄膜を接着し(b)、その後、雲母基板を剥離除去した(c)。
【0026】
雲母基板からSi集積回路上に転写されたInSb薄膜の電子移動度を、van der Pauw法を用いて測定したところ、転写前の雲母基板上の場合と同じ30000cm/Vsであった。Si集積回路上にSiO層を介して、直接形成した場合の電子移動度4000m/Vsと比較して極めて高い値であった。
【0027】
次に、フォトリソグラフィー法によりホール素子2の形状をしたレジストパターンをInSb薄膜上に形成し、HCl系エッチング液を用いてInSb薄膜をエッチングし、レジストを除去した(d)。次いで、集積回路のAl電極パッドの部分が開口部となるレジストパターンを形成し、Oアッシングによりエポキシを除去しAl電極パッドを露出させた(e)。最後に、ホール素子の入出力端子と集積回路の所定のAl電極パッドを配線するように、1μmのAuと0.1μmのTiの積層体からなる接続電極4を形成し(f)、複合半導体素子を完成させた。
【0028】
この複合半導体素子をリードフレーム上にダイボンディング、次いでワイヤボンディング、さらにトランスファーモールドを行い、モールド素子を製作した。
【0029】
図3は、モールド素子の上面図であり、従来のホール素子と集積回路をワイヤで接続した場合の図4と比較して極めて小さくなることがわかる。なお、図4において、符号11は集積回路、12は化合物半導体素子、13はリードフレーム、14はワイヤ、15はモールドパッケージを示している。
【0030】
【発明の効果】
以上説明したように本発明によれば、好適な基板上に好適な条件で形成された高品質な化合物半導体薄膜を集積回路上に接着剤を介して転写接着し、化合物半導体素子を形成した後、化合物半導体素子と集積回路とを接続電極で電気的に接続するので、単一の化合物半導体素子で達成される性能を十分に引き出しながら、小型化をも兼ね備えた複合半導体素子を提供することができる。
【図面の簡単な説明】
【図1】本発明における複合半導体素子の一例を示す断面図である。
【図2】本発明における複合半導体素子を作製する工程図の一例を示す図である。
【図3】本発明におけるモールドされた複合半導体素子の上面図である。
【図4】化合物半導体素子と集積回路とがワイヤで接続された従来の複合半導体素子の上面図である。
【符号の説明】
1、6、11 集積回路
1a 回路が形成された基板
1b 電極パッド
2、7、12 化合物半導体素子
2a 化合物半導体薄膜
3 接着剤
4 接続電極
5 薄膜形成用基板
8、13 リードフレーム
9、14 ワイヤ
10、15 モールドパッケージ
[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a composite semiconductor element in which a compound semiconductor element and an integrated circuit (IC) are combined, and a method for manufacturing the same. The present invention relates to a technique for transferring a compound semiconductor thin film such as IC and InSb onto an integrated circuit.
[0002]
[Prior art]
Compound semiconductors such as InSb, InAs, and GaAs having high electron mobility are suitable as materials for high-sensitivity Hall elements and high-speed electronic devices. Further, there is a composite semiconductor element in which these elements and an integrated circuit having a signal processing function are combined. For example, a Hall IC composed of an InSb Hall element and an Si integrated circuit described in JP-A-61-226982 Is well known. These Hall ICs have an advantage that they are more sensitive to magnetic fields than Si monolithic Hall ICs in which the Hall element part and the signal processing part are formed on the same substrate.
[0003]
[Problems to be solved by the invention]
However, the Hall IC described above has a problem that the Hall element and the IC are separately arranged on the lead frame and the electrodes of these elements are connected by wires, so that the size is larger than that of the Si monolithic Hall IC. .
[0004]
In order to realize a small Hall IC, a structure in which Hall elements are arranged on the IC can be considered. For example, Japanese Patent Laid-Open No. 49-91196 proposes a magnetosensitive element in which a magnetosensitive portion of a compound semiconductor is formed on a semiconductor substrate (IC substrate) on which an amplifying transistor is formed via an insulating layer. . As a specific method for forming a compound semiconductor thin film, it is described that it is directly formed on an insulating layer such as SiO 2 by sputtering, vapor deposition or the like.
[0005]
In the method of forming a compound semiconductor thin film described above, the IC is a substrate, so that the formation temperature is restricted, the circuit is formed, the substrate has large irregularities, and is directly deposited on the insulating layer. For this reason, it has been difficult to form a high-quality compound semiconductor thin film having high electron mobility. Therefore, despite using a compound semiconductor, a high-sensitivity Hall element cannot be produced, and the superiority over the Si monolithic Hall IC has been significantly reduced.
[0006]
The present invention has been made in view of such problems, and an object of the present invention is to provide characteristics of a compound semiconductor in a composite semiconductor element in which a compound semiconductor element and an IC are combined, such as a Hall IC using InSb as a sensor part. It is an object of the present invention to provide a composite semiconductor device and a method for manufacturing the same that can realize downsizing while utilizing the above.
[0007]
[Means for Solving the Problems]
In order to achieve the above object, the present invention provides a composite semiconductor device in which a compound semiconductor device and an integrated circuit are electrically connected, wherein the compound semiconductor device is the integrated semiconductor device. A connection electrode of the laminate in which the compound semiconductor terminal and the electrode pad of the integrated circuit are electrically connected after the electrode pad of the integrated circuit is exposed and transferred onto the circuit through an adhesive. And the compound semiconductor element is a Hall element having In X1 Ga 1 -X1 As Y1 Sb 1 -Y1 (0 ≦ X1 ≦ 1, 0 ≦ Y1 ≦ 1) as an active layer .
[0009]
The invention according to claim 2 is the invention according to claim 1 , wherein the laminate is a laminate made of gold and titanium.
According to a third aspect of the present invention, there is provided a method of manufacturing a composite semiconductor device in which a compound semiconductor device and an integrated circuit are electrically connected, and a compound semiconductor thin film formed on a substrate is bonded onto the integrated circuit. A step of removing the substrate from the compound semiconductor thin film after transfer adhesion through an agent, a step of etching the compound semiconductor into a predetermined shape by a photolithography method, and a step of exposing only the electrode pads of the integrated circuit If, possess and forming a connection electrode of the stack for electrically connecting the input and terminals of the predetermined shape of the compound semiconductor with the electrode pad, wherein the compound semiconductor thin film is vapor deposited on the mica substrate In X1 Ga 1-X1 As Y1 Sb 1-Y1 (0 ≦ X1 ≦ 1, 0 ≦ Y1 ≦ 1) .
[0012]
As described above, the present inventors have conducted extensive studies to solve the above problems, and as a result, transferred and bonded the compound semiconductor thin film formed on a suitable substrate under suitable conditions onto an IC via an adhesive. Then, after forming the compound semiconductor element, it is possible to produce a composite semiconductor element in which the compound semiconductor element is arranged on the IC by electrically connecting with the IC. It has been found that the present invention is effective for realizing a composite semiconductor device that achieves high sensitivity and is also miniaturized, and has led to the present invention.
[0013]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below with reference to the drawings.
FIG. 1 is a cross-sectional view of a composite semiconductor device according to the present invention. Indicates a connection electrode connecting the compound semiconductor element and the integrated circuit.
[0014]
2 (a) to 2 (f) are diagrams showing a manufacturing process of the composite semiconductor element of the present invention. First, the adhesive 3 is applied onto the integrated circuit 1 (a), and the compound semiconductor thin film 2a formed on the substrate 5 for thin film formation is attached onto the adhesive 3 (b). Thereafter, the substrate 5 is removed (c) and then patterned to be processed into the shape of the compound semiconductor element 2 (d). Further, the adhesive 3 on the electrode pad 1b is removed (e), then the connection electrode 4 is formed (f), and the compound semiconductor element and the integrated circuit are connected to produce a composite semiconductor element.
[0015]
The formation of the compound semiconductor thin film in the present invention can be carried out under a suitable temperature condition by selecting a thin film forming substrate suitable for the compound semiconductor thin film. Accordingly, the high electron mobility inherent in the compound semiconductor material can be realized, and the compound semiconductor thin film is directly formed on the integrated circuit substrate described in Japanese Patent Laid-Open No. 49-91196 described above. It is a different point.
[0016]
FIG. 3 is a top view of a packaged composite semiconductor device according to the present invention, in which reference numeral 6 denotes an integrated circuit, 7 denotes a compound semiconductor device, 8 denotes a lead frame, 9 denotes a wire, and 10 denotes a molded package. This is significantly reduced in size as compared with a conventional composite semiconductor element in which a compound semiconductor element and an integrated circuit are connected by a wire.
[0017]
That is, according to the present invention, in the composite semiconductor element in which the compound semiconductor element 2 and the integrated circuit 1 are electrically connected, the compound semiconductor element 2 is bonded to the integrated circuit 1 via the adhesive 3. It is characterized by that.
[0018]
According to another aspect of the present invention, the compound semiconductor element is a Hall element having an active layer of In X1 Ga 1 -X1 As Y1 Sb 1 -Y1 (0 ≦ X1 ≦ 1, 0 ≦ Y1 ≦ 1). It is an element.
[0019]
In the present invention, the function, structure, and material of the compound semiconductor element are not particularly limited, but as the compound semiconductor material in the case of a Hall element, In X1 Ga 1-X1 As Y1 Sb 1-Y1 (0 ≦ X1 ≦ 1, 0 ≦ Y1 ≦ 1) is preferable because of high electron mobility. Further, the compound semiconductor element may be in a bulk form or a thin film form and is not particularly limited. For example, when the compound semiconductor is InSb, it may be an InSb bulk or an InSb thin film formed on a GaAs substrate. However, in order to reduce the thickness of the element, after bonding onto an integrated circuit The thin film forming substrate is preferably removed. When mica is used as the thin film forming substrate, it is very preferable because the InSb and InAs thin films having high electron mobility can be obtained and the mica substrate can be easily peeled off after bonding.
[0020]
That is, the present invention relates to a method for manufacturing a composite semiconductor device in which a compound semiconductor device and an integrated circuit are electrically connected, and a compound semiconductor thin film formed on a substrate is bonded to the integrated circuit via an adhesive. Then, a method for producing a composite semiconductor element, comprising: removing the substrate from the compound semiconductor thin film.
[0021]
Further, the present invention is characterized in that the compound semiconductor thin film is In X1 Ga 1 -X1 As Y1 Sb 1 -Y1 (0 ≦ X1 ≦ 1, 0 ≦ Y1 ≦ 1) formed by vapor deposition on a mica substrate. This is a method for manufacturing a composite semiconductor device.
[0022]
The present invention also includes a step of removing the substrate from the compound semiconductor thin film, then processing the compound semiconductor thin film into a predetermined shape by an etching method, and thereafter removing at least the adhesive on the electrode pad portion of the integrated circuit. A method of manufacturing a composite semiconductor device comprising a step of connecting a compound semiconductor thin film and an electrode pad of an integrated circuit with a conductive thin film.
[0023]
Although it does not specifically limit as adhesive material in this invention, Thermosetting resin, such as an epoxy resin, is preferable from a viewpoint of the ease of a process and heat resistance. The method for applying the adhesive is not particularly limited, but the spin coating method is preferred because it can be applied thinly and uniformly. When applying by this method, it is preferable to select a low-viscosity resin as the adhesive material.
[0024]
In addition, the substrate material of the integrated circuit in the present invention is not particularly limited, but generally Si or GaAs is used and can be selected depending on the application.
[0025]
Specific examples of the present invention will be described below.
The composite semiconductor element shown in FIG. 1 was produced by the process shown in FIG.
First, an epoxy resin as the adhesive 3 was applied on the integrated circuit 1 formed on the Si substrate by spin coating to a thickness of about 2 μm (a). Next, a 1 μm-thick InSb thin film 2a formed by vacuum deposition is applied to the mica substrate 5 on an adhesive, and the epoxy is thermally cured in a thermostat to bond the Si integrated circuit and the InSb thin film (b) Thereafter, the mica substrate was peeled and removed (c).
[0026]
When the electron mobility of the InSb thin film transferred from the mica substrate onto the Si integrated circuit was measured using the van der Pauw method, it was 30000 cm 2 / Vs, the same as that on the mica substrate before transfer. The electron mobility was 4000 m 2 / Vs when formed directly on the Si integrated circuit via the SiO 2 layer, which was an extremely high value.
[0027]
Next, a resist pattern having the shape of the Hall element 2 was formed on the InSb thin film by photolithography, and the InSb thin film was etched using an HCl-based etchant to remove the resist (d). Next, a resist pattern was formed in which the Al electrode pad portion of the integrated circuit was an opening, and the epoxy was removed by O 2 ashing to expose the Al electrode pad (e). Finally, a connection electrode 4 made of a laminate of 1 μm Au and 0.1 μm Ti is formed so as to wire the input / output terminals of the Hall element and a predetermined Al electrode pad of the integrated circuit (f), and the composite semiconductor The device was completed.
[0028]
This composite semiconductor element was die-bonded on a lead frame, then wire bonded, and further transfer molded to produce a mold element.
[0029]
FIG. 3 is a top view of the mold element, and it can be seen that it is extremely small compared to FIG. 4 in the case where the conventional Hall element and the integrated circuit are connected by a wire. In FIG. 4, reference numeral 11 denotes an integrated circuit, 12 denotes a compound semiconductor element, 13 denotes a lead frame, 14 denotes a wire, and 15 denotes a mold package.
[0030]
【The invention's effect】
As described above, according to the present invention, after a compound semiconductor element is formed by transferring and bonding a high-quality compound semiconductor thin film formed on a suitable substrate under suitable conditions onto an integrated circuit via an adhesive. Since the compound semiconductor element and the integrated circuit are electrically connected by the connection electrode, it is possible to provide a composite semiconductor element that combines downsizing while sufficiently achieving the performance achieved by a single compound semiconductor element it can.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view showing an example of a composite semiconductor element in the present invention.
FIG. 2 is a diagram showing an example of a process chart for manufacturing a composite semiconductor element according to the present invention.
FIG. 3 is a top view of a molded composite semiconductor device according to the present invention.
FIG. 4 is a top view of a conventional composite semiconductor device in which a compound semiconductor device and an integrated circuit are connected by a wire.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1, 6, 11 Integrated circuit 1a The board | substrate 1b in which the circuit was formed Electrode pad 2, 7, 12 Compound semiconductor element 2a Compound semiconductor thin film 3 Adhesive 4 Connection electrode 5 Thin film formation board | substrate 8, 13 Lead frame 9, 14 Wire 10 , 15 Mold package

Claims (3)

化合物半導体素子と集積回路とが電気的に接続されている複合半導体素子において、
前記化合物半導体素子が前記集積回路上に接着剤を介して転写接着され、前記化合物半導体の端子と、前記集積回路の電極パッドとが電気的に接続する積層体の接続電極とを備え
前記化合物半導体素子が、In X1 Ga 1−X1 As Y1 Sb 1−Y1 (0≦X1≦1、0≦Y1≦1)を活性層とするホール素子であることを特徴とする複合半導体素子。
In a composite semiconductor element in which a compound semiconductor element and an integrated circuit are electrically connected,
The compound semiconductor element is transferred and bonded to the integrated circuit via an adhesive, and includes a connection electrode of a laminate in which the terminal of the compound semiconductor and the electrode pad of the integrated circuit are electrically connected ,
The compound semiconductor device, In X1 Ga 1-X1 As Y1 Sb 1-Y1 composite semiconductor device characterized by (0 ≦ X1 ≦ 1,0 ≦ Y1 ≦ 1) is a Hall element to the active layer.
前記積層体が金とチタンとからなる積層体であることを特徴とする請求項1に記載の複合半導体素子。The composite semiconductor element according to claim 1, wherein the laminate is a laminate made of gold and titanium. 化合物半導体素子と集積回路とが電気的に接続されている複合半導体素子の製造方法において、
基板上に形成された化合物半導体薄膜を前記集積回路上に接着剤を介して転写接着した後、前記基板を前記化合物半導体薄膜から除去する工程と、フォトリソグラフィー法により前記化合物半導体を所定の形状にエッチングする工程と、前記集積回路の電極パッドのみを露出する工程と、該電極パッドと前記化合物半導体の前記所定の形状の入出端子とを電気的に接続する積層体の接続電極を形成する工程とを有し、
前記化合物半導体薄膜が、雲母基板上に蒸着形成されたIn X1 Ga 1−X1 As Y1 Sb 1−Y1 (0≦X1≦1、0≦Y1≦1)であることを特徴とする複合半導体素子の製造方法。
In a method for manufacturing a composite semiconductor element in which a compound semiconductor element and an integrated circuit are electrically connected,
After the compound semiconductor thin film formed on the substrate is transferred and adhered to the integrated circuit via an adhesive, the substrate is removed from the compound semiconductor thin film, and the compound semiconductor is formed into a predetermined shape by photolithography. Etching, exposing only the electrode pad of the integrated circuit, forming a connection electrode of a laminate that electrically connects the electrode pad and the input / output terminal of the predetermined shape of the compound semiconductor; I have a,
The compound semiconductor thin film is In X1 Ga 1-X1 As Y1 Sb 1-Y1 (0 ≦ X1 ≦ 1, 0 ≦ Y1 ≦ 1) formed by vapor deposition on a mica substrate . Production method.
JP2002036017A 2002-02-13 2002-02-13 Composite semiconductor device and manufacturing method thereof Expired - Fee Related JP4480318B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2002036017A JP4480318B2 (en) 2002-02-13 2002-02-13 Composite semiconductor device and manufacturing method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2002036017A JP4480318B2 (en) 2002-02-13 2002-02-13 Composite semiconductor device and manufacturing method thereof

Publications (2)

Publication Number Publication Date
JP2003243646A JP2003243646A (en) 2003-08-29
JP4480318B2 true JP4480318B2 (en) 2010-06-16

Family

ID=27778038

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2002036017A Expired - Fee Related JP4480318B2 (en) 2002-02-13 2002-02-13 Composite semiconductor device and manufacturing method thereof

Country Status (1)

Country Link
JP (1) JP4480318B2 (en)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPWO2010090075A1 (en) * 2009-02-05 2012-08-09 アルプス電気株式会社 Magnetic detector
KR20160052798A (en) * 2012-12-14 2016-05-12 아사히 가세이 일렉트로닉스 가부시끼가이샤 Magnetic sensor and magnetic sensor device, and magnetic sensor manufacturing method
JP2016070829A (en) * 2014-09-30 2016-05-09 エスアイアイ・セミコンダクタ株式会社 Hall sensor
GB2535683A (en) * 2014-11-03 2016-08-31 Melexis Technologies Nv Magnetic field sensor and method for making same
US11067643B2 (en) * 2014-11-03 2021-07-20 Melexis Technologies Nv Magnetic field sensor and method for making same
WO2016129288A1 (en) * 2015-02-12 2016-08-18 旭化成エレクトロニクス株式会社 Sensor device and method for manufacturing same
US11230471B2 (en) 2016-02-05 2022-01-25 X-Celeprint Limited Micro-transfer-printed compound sensor device
CN113745268A (en) * 2021-08-06 2021-12-03 苏州矩阵光电有限公司 Monolithic integrated Hall circuit
CN113758993A (en) * 2021-08-06 2021-12-07 苏州矩阵光电有限公司 Two-dimensional detection circuit integrated with array type Hall element

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS584991A (en) * 1981-07-01 1983-01-12 Matsushita Electric Ind Co Ltd Semiconductor device
JPH05175148A (en) * 1991-12-25 1993-07-13 Murata Mfg Co Ltd Method for transferring and forming insb thin film
JPH06209130A (en) * 1993-01-11 1994-07-26 Matsushita Electron Corp Forming method of insb thin film
JPH09116207A (en) * 1995-10-18 1997-05-02 Asahi Chem Ind Co Ltd Hall element and its manufacture
JPH09223848A (en) * 1996-02-16 1997-08-26 Nippon Telegr & Teleph Corp <Ntt> Semiconductor integrated circuit
JPH11134045A (en) * 1997-10-27 1999-05-21 Sharp Corp Direct-current stabilized power unit

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS584991A (en) * 1981-07-01 1983-01-12 Matsushita Electric Ind Co Ltd Semiconductor device
JPH05175148A (en) * 1991-12-25 1993-07-13 Murata Mfg Co Ltd Method for transferring and forming insb thin film
JPH06209130A (en) * 1993-01-11 1994-07-26 Matsushita Electron Corp Forming method of insb thin film
JPH09116207A (en) * 1995-10-18 1997-05-02 Asahi Chem Ind Co Ltd Hall element and its manufacture
JPH09223848A (en) * 1996-02-16 1997-08-26 Nippon Telegr & Teleph Corp <Ntt> Semiconductor integrated circuit
JPH11134045A (en) * 1997-10-27 1999-05-21 Sharp Corp Direct-current stabilized power unit

Also Published As

Publication number Publication date
JP2003243646A (en) 2003-08-29

Similar Documents

Publication Publication Date Title
US11370656B2 (en) Stacked-die MEMS resonator
US4908685A (en) Magnetoelectric transducer
US7109065B2 (en) Bumped chip carrier package using lead frame and method for manufacturing the same
JP4480318B2 (en) Composite semiconductor device and manufacturing method thereof
US11855035B2 (en) Stack of electrical components and method of producing the same
JP3402086B2 (en) Semiconductor device and manufacturing method thereof
TWI512925B (en) A wirebond structure and method forming the same
US6724059B2 (en) Magnetoelectric transducer and method for producing the same
JP2003007908A (en) Wafer level chip-scale package and method of manufacturing the same
TW201225245A (en) Semiconductor package device with cavity structure and the packaging method thereof
JP2682200B2 (en) Semiconductor device
US20060113874A1 (en) Surface acoustic wave device package
JP4573368B2 (en) Manufacturing method of small magnetoelectric transducer for face-down connection
JPH02170584A (en) Magnetoelectric conversion element
JPS6120378A (en) Magnetoelectric conversion element
JPH11330584A (en) Magnetoelectric transducer, magnetic sensor using the transducer, and manufacture of the magnetoelectric transducer
JP4467090B2 (en) Small magnetoelectric transducer and manufacturing method thereof
JPH0462474B2 (en)
JP2727605B2 (en) Semiconductor device and manufacturing method thereof
JPH10209154A (en) Semiconductor device
TWI612587B (en) A method of semiconductor package without substrate
JPH08204250A (en) Semiconductor device
JPH0462475B2 (en)
JPH0671105B2 (en) Method for manufacturing magnetoelectric conversion element
JPH0471351B2 (en)

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20050210

A711 Notification of change in applicant

Free format text: JAPANESE INTERMEDIATE CODE: A712

Effective date: 20070402

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20080213

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20081003

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20081202

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20090515

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20090714

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20100108

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20100218

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20100312

A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20100316

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20130326

Year of fee payment: 3

R150 Certificate of patent or registration of utility model

Ref document number: 4480318

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

Free format text: JAPANESE INTERMEDIATE CODE: R150

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20140326

Year of fee payment: 4

LAPS Cancellation because of no payment of annual fees