JPH09223848A - Semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a three-dimensional semiconductor integrated circuit, having high-speed operability and high functionality, by electrically connecting a semiconductor element, integrated on a semiconductor board, and one or more semiconductor elements, placed on an insulating layer, through windows formed in the insulating layer. SOLUTION: Windows are formed in an insulating layer 300, and a lightreceiving element 100A and a plane luminous element 100B are connected with metal traces 200A on an integrated circuit board 200 through the windows using traces 400. At this time, using the insulating layer 300 as an adhesive layer facilitates the threedimensional arrangement of semiconductor elements. Since the adhesive layer is non-conductive, it is possible to easily form traces on the adhesive layer, and thus to provide the elements placed in the integrated circuit with required traces. This obtains an optical array switch with a high extinction ratio and a simple optical system, having high-speed responsivity.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit, and more particularly to a semiconductor integrated circuit in which semiconductor elements are three-dimensionally integrated.

[0002]

2. Description of the Related Art Three-dimensional integration of semiconductor devices is important not only for increasing the degree of integration of semiconductor integrated circuits, but also for forming an optical switch array.
The development of an optical switch array as a key device for optical signal processing and optical information processing is highly desired. Conventionally, as an element of this type, for example, the document “IEEE PHOTONICS TECHNOL
OGY LETTERS, Vol. 7, p. 360 (1995) ”, a multiple quantum well pin diode is mounted on a silicon integrated circuit substrate by a solder bump, and the multiple quantum well p
An element called "Hybrid Seed (H-SHEED)" has been proposed in which an in diode is used as a light receiving element or an optical modulator to input and output light and to perform a logical function on a silicon integrated circuit. In this device, an input optical signal incident on an input multiple quantum well pin diode is converted into an electric signal, transmitted to a silicon integrated circuit substrate, electrically processed, and then applied to the output multiple quantum well pin diode. Control the voltage. At this time, in the output multiple quantum well pin diode, the reflection intensity of the light biased at a constant intensity can be controlled by the quantum confined Stark effect according to the voltage change. The structure is shown in Figure 1.
2 and the characteristics are shown in FIG.

As shown in FIG. 12A, the epitaxial substrate 10 includes a p-GaAs substrate 11 and a p-Al substrate.
GaAs layer 12, i-MQW layer 13 and (n ^-- Ga)
As layer and n ⁺ -GaAs layer) 14 are sequentially laminated, and B
An optical modulation section is formed by forming the e-ion implantation layer 15 and the Ti / Au film 16 as a reflection layer. The p-side and n-side electrodes are on the same plane, and the solder 17 is formed on the Be ion implantation layer 15 and the Ti / Au film 16. On the other hand, Al: Ti for improving the wettability is formed on the surface of the silicon integrated circuit substrate 20 on which the CMOS is formed.
A / Pt / Au film 21 is formed, and the solder 17 is provided thereon. As shown in FIG. 12B, the optical modulator is mounted on the silicon integrated circuit substrate by joining the two substrates with solder bumps. After the bonding, the periphery of the bonded portion is filled with the epoxy resin 18, and then the GaAs substrate is removed. The epoxy resin can then be removed. Finally, as shown in FIG. 12C, an antireflection coating 19 is applied to obtain an optical modulator integrated with silicon CMOS. This conventional example has a 2-input 2-output switch function.

FIG. 13 shows the relationship between the gate-source voltage and the reflectance in the hybrid seed element thus manufactured. Switching operation is possible by controlling the gate-source voltage of CMOS.

[0005]

However, the above-mentioned optical switch array has the following problems.

First, a multiple quantum well type p is used as an optical modulator.
Since the in diode is used, the extinction ratio is low and the loss is large.

Secondly, since it is necessary to enter bias light into the light modulator, the optical system becomes complicated.

Thirdly, since the operating voltage of the light modulator is as large as about 10V, the response speed is slow.

Fourth, the operating wavelength of the modulator using the quantum confined Stark effect is limited to several nm, and the operating wavelength of the modulator fluctuates due to heat generated from the silicon integrated circuit. The wavelength is severely limited,
Furthermore, it is necessary to control the element to a constant temperature.

On the other hand, the method of forming the three-dimensional structure of the electronic element and the optical element by the solder bump like the above-mentioned conventional element has the following problems.

That is, if an optical element having a different layer structure such as a light receiver and a surface emitting laser is to be simultaneously arranged on a silicon integrated circuit, since each optical element has a different structure, they are formed on the same substrate. However, it is necessary to separately place each element on the silicon integrated circuit by solder bumps. Such individual mounting involves the following difficulties.

First, the solder bumps must be formed a plurality of times, which complicates the process.

Secondly, in the optical switch array, the relative position of each optical element must match the predetermined positional relationship of the incoming and outgoing light. However, solder bumping is performed for each individual optical element. It is difficult to accurately determine the relative position between the optical elements. Therefore, it is difficult to match the positional relationship of each optical element with the positional relationship of the incoming and outgoing light.

An object of the present invention is to solve the above problems in the conventional optical switch array, to realize a three-dimensional semiconductor integrated circuit in which the problems of the three-dimensional structure due to solder bumps are solved, and an extinction ratio. It is to realize an optical switch array having a large size, a simple optical system, a high response speed, and a large operation margin.

[0015]

A semiconductor integrated circuit according to the present invention is a semiconductor substrate in which semiconductor elements are integrated on one main surface, an insulating layer arranged on the substrate, and an insulating layer on the insulating layer. One or more semiconductor elements arranged, a semiconductor element integrated on the semiconductor substrate through one or more windows formed in the insulating layer, and one or more semiconductor elements arranged on the insulating layer. It is characterized in that it has wiring to be electrically connected.

Here, it is preferable that the insulating layer is an organic material cured by heat treatment, and the insulating layer has a metal layer that is in contact with the semiconductor substrate and has a thickness equal to that of the insulating layer. preferable.

Here, the semiconductor element integrated on the semiconductor substrate is an electric element, and the one or more semiconductor elements include a light receiving element and a vertical cavity surface emitting laser. It is preferable that the wiring is arranged so that a current generated by processing the generated signal current by the electric element can be supplied to the vertical cavity surface emitting laser.

Further, the semiconductor element integrated on the semiconductor substrate is an electric element, and the one or more semiconductor elements include a light receiving element, a vertical cavity surface emitting laser, and other electric elements. In the insulating layer in which the wiring is arranged so that the signal current generated in the light receiving element is supplied to the vertical cavity surface emitting laser by processing the current generated in the other electric element and the electric element, It is preferable to have a metal layer that is in contact with the semiconductor substrate and has a thickness equal to that of the insulating layer. Here, it is preferable that the electric element is a field effect transistor.

It is preferable that a plurality of optical switches composed of the light receiving element, the vertical cavity surface emitting laser and the electric element are periodically arranged on the one main surface, or the light receiving element. It is preferable that a plurality of the vertical cavity surface emitting lasers, the other electric element, and an optical switch including the electric element are periodically arranged on the one main surface.

[0020]

FIG. 1 shows an embodiment of the device according to the present invention. The optical input / output board 10 is provided on the integrated circuit board 200 in which semiconductor elements such as MOSFETs, transistors, and diodes are integrated on one main surface, with the insulating layer 300 interposed therebetween.
0 is integrated. A plurality of light receiving elements 100A and a vertical cavity surface emitting laser (hereinafter referred to as a surface emitting laser) 100B are arranged on the light input / output substrate 100.
A window is provided in the insulating layer 300, and the light receiving element 100A and the surface emitting element 100B are connected to the metal wiring 200A of the integrated circuit board 200 through the window by the wiring 400. 100C and 100D are the light receiving elements 10 respectively.
0A and the surface light emitting element 100B. This element converts the light input from the light receiving element 100A into an electric signal, and the electric signal is subjected to processing such as amplification and switching by a semiconductor element integrated on the integrated circuit board 200, and the processing result is output as a current output. It can be transmitted to the light emitting laser 100B and its operation can be controlled.

FIG. 2 shows the operating characteristics of this device. The example of FIG. 2 shows the result of synchronizing, amplifying, and shaping the waveform of the input signal. In the case of the device of the present invention, various processing can be performed by the processing function of the integrated circuit board, and in addition to this example, 2 × 2 switching, various arithmetic processing, image processing and the like can be mentioned.

In the optical switch array according to the present invention, since the vertical cavity surface emitting laser is used as the optical modulator, bias light is not required and high contrast can be obtained, so that the optical system is simplified. Further, since an operating voltage of about 3V is sufficient, high speed operation can be realized. In addition, when the device of the present invention is configured in multiple stages and optical connection such that the output light from the previous stage is used as the input light is performed to perform processing such as optical interconnection, the surface emitting laser has an oscillation wavelength of a film thickness. It is very sensitive to fluctuations of light and is difficult to control, but if a pin diode, MSM photodiode, etc. is used as the light receiving part, almost uniform photosensitivity can be obtained in a wide wavelength range of 100 nm or more. The emission wavelength of the light emitting laser is not limited, and it is also advantageous for multi-stages.

In an attempt to manufacture the optical switch array as described above, since the vertical cavity surface emitting laser and the photodetector have different layer structures, they cannot be simultaneously formed on one substrate. The solder bump technology cannot be used. In order to solve this problem, the present invention arranges a semiconductor element such as a vertical resonator via an insulating layer on a semiconductor substrate in which the semiconductor element is integrated on one main surface, and further Wiring is provided between a semiconductor element integrated on a semiconductor substrate and a vertical resonator arranged on an insulating layer through a window formed in the layer.

As the insulating layer, there are polyimide, SiO _{2 and the} like, and any of them has the ability to bond the semiconductors to each other by an appropriate process. Therefore, by using these insulating layers as the adhesive layer, the three-dimensional arrangement of the semiconductor elements becomes easy. Furthermore, since it is insulating, wiring can be easily provided on this adhesive layer, so that necessary wiring can be provided to the device arranged on the integrated circuit. For example, when a layer structure for a laser and a layer structure for a light receiver are stacked on a single substrate and attached to a semiconductor integrated circuit with an insulating adhesive layer, each layer is etched by etching as shown in FIG. After exposing the structure as needed, the required wiring can be facilitated.

[0025]

Example 1 The growth surface of the optical input / output substrate is directed to the integrated circuit substrate side.
Only a first specific example of applying the present invention when adhered to the optical switch array shown in FIGS. 3 and 4.

FIG. 3 is a sectional view of an optical input / output substrate when GaAs / AlGaAs multiple quantum wells are used for the active layer. On a semi-insulating GaAs substrate 101, an AlAs layer 102 for selective etching and an n ⁺ -GaAs contact layer 10
3, n-DBR (Distributed Bragg Reflector) layer 10
4, active layer 105, p-DBR layer 106 and i-Ga
The As light absorption layer 107 was sequentially formed by the molecular beam epitaxial growth method. Be and Si were used for the p-type and n-type dopants, respectively. Here, the n-DBR layer is n-AlAs (71.5 nm) / n-Al _0.15 Ga _0.85.
The p-DBR layer has a structure in which As (62.9 nm) is alternately laminated for 25 periods, and the p-DBR layer is p-AlAs (71.5 nm).
/ P-Al _0.15 Ga _0.85 As (62.9 nm) is alternately laminated for 30 cycles.

FIG. 4 shows a method of manufacturing the optical switch. First,
As shown in FIG. 4A, the growth layer 10 of the light input / output substrate 100.
OE is adhered with an adhesive 300 toward the main surface side of the silicon integrated circuit substrate 200 on which the semiconductor elements are integrated. In this case, polyimide is applied as an adhesive to the adhesive surfaces of both substrates by spin coating to prevent air bubbles from entering. After that, the two substrates are bonded together and heat-treated at a high temperature while applying a load to cure them. As for the procedure of bonding, first perform temporary adhesion at a temperature of about 150 ° C.
The aAs substrate 101 is divided into a size of about one chip.
Then, final curing is performed at 350 ° C. This is to prevent the substrate from warping due to the difference in thermal expansion coefficient between silicon and GaAs when a large substrate of 2 inches or more is formed. At this time, when the thick metal film 200A for electrical connection and cooling is formed on the integrated circuit substrate 200, the metal film 20
The 0A portion is extruded by applying a load to the polyimide 300 that has entered between the optical input / output board 100 and the adhesive, and as a result, as shown in FIG. Like

After that, the GaAs substrate 101 is formed to a thickness of 50 μm.
Polished to about m, PA30 solution (H ₂ O ₂ : NH ₃ O
H = 30: 1) selectively etches only the GaAs substrate 101 and stops the etching at the AlAs layer 102. Next, only the AlAs layer 102 is selectively etched with hydrochloric acid so that the n ⁺ -GaAs contact layer 103 is exposed on the surface as shown in FIG. 4C. FIG.
(C ') is an enlarged view showing the growth layer in this state.

Next, as shown in FIG. 4D, the light input / output substrate is processed to form the surface emitting laser 100B and the SMS photodetector 100A. FIG. 4D 'is an enlarged view of the surface emitting laser section. AuZnNi is used as the p-type electrode 110 and AuG is used as the n-type electrode 111 of the surface emitting laser.
Schottky electrode 11 of photodetector using eNi
Ti / Pt / Au was used as 2, and then FIG.
As shown in (e), a portion of the optical input / output substrate 100 where the electrical wiring between the two substrates is to be formed is etched by the metal film 200A.
Open the through hole until is exposed. The SMS photo detector portion is also partitioned.

Then, the inter-element wiring metal 400 is formed by plating, and the wiring 113 is applied to obtain the structure shown in FIG. 4 (f).

When a solder bump is used as in the conventional example, the electrode must be formed on the surface of the substrate on which the laser and the light receiver are laminated, so that it is difficult to form the electrode on either one of the elements. Become. For example, when the laminated structure shown in FIG. 3 is used, the p-DBR layer 106 and the active layer 105 are formed.
It is difficult to form an electrode on the laser structure including the n-DBR layer 104 and the n-DBR layer 104. However, the structure of the present invention does not cause such a problem. Thick metal film 2 on integrated circuit board 200
00A has the effect of reducing the level difference in the electrical connection between both substrates, the effect of preventing the incidence of light from the light receiving element and the light emitting element onto the integrated circuit substrate, and the effect of removing the heat generated in the light input / output substrate through the metal film. is there.

Actually, MSM-PD, ME within one pixel
8x8 = 6 with 3 SFETs and surface emitting laser
A two-dimensional array of 4 pixels is prepared, and input light of 0.1 mW, 200 MHz is input to MSD-PD in the wavelength band of 850 nm.
It was confirmed that the operation of inputting 1 mW of output light from the surface emitting laser to all the pixels was performed in parallel.

Further, the number of surface emitting lasers and light receiving elements is not limited to one for each processing unit (cell) in the integrated circuit, and there may be a plurality of input / output elements.

In this embodiment, the plating is used to form the inter-element wiring metal, but the present invention is not limited to this. For example, tungsten or the like may be used to fill the step by selective growth.
Further, although polyimide is used for bonding the both substrates, the present invention is not limited to this, and various adhesives such as epoxy type may be used, and it is also possible to bond dielectrics such as SiO _{2 to} each other. is there.

The optical input / output substrate is made of semi-insulating GaAs.
On the substrate 101, an AlAs layer for selective etching, p ⁺ −
GaAs contact layer, p-DBR layer, i-GaAs /
AlGaAs active layer, n-DBR layer and i-GaAs
Light-absorbing layers are laminated in this order, and p of the DBR layer of the surface-emitting laser,
The polarities of n may be exchanged. In this case, p-DBR
The layers are stacked for 25 cycles, and the n-DBR layer is stacked for 30 cycles. This is for setting the reflectance of the DBR mirror on the integrated circuit substrate side higher than the reflectance of the DBR mirror on the emission side so that output light can be obtained on the emission side with high efficiency. This is the same in the following embodiments.

Example 2 The growth surface of the optical input / output substrate is integrated.
When bonded opposite to the side of the road substrate (1) Process the optical input / output substrate after the substrate is bonded
Case A second specific example in which the present invention is applied to an optical switch array is shown in FIGS.

FIG. 5 is a sectional view of an optical input / output substrate when GaAs / AlGaAs multiple quantum wells are used for the active layer. On the semi-insulating GaAs substrate 101, AlAs layer 102 for selective etching, i-GaAs light absorption layer 107,
p-DBR layer 106, i-GaAs / AlGaAs active layer 105, n-DBR layer 104, and n ⁺ -GaAs
The contact layer 103 was sequentially formed by the molecular beam epitaxial growth method. The stacking order of the light receiving element constituent layer and the light emitting element constituent layer is opposite to that of the first embodiment. here,
Similar to Example 1, the n-DBR layer has a structure in which 30 periods are stacked, and the p-DBR layer has a structure in which 25 periods are stacked.

FIG. 6 shows a method of making an optical switch. First,
As shown in FIG. 6A, the optical input / output substrate 100 is provided with a flat quartz plate 4.
00 with the growth layer 100E facing upward and pasted with wax 500.

Then, as shown in FIG. 6B, GaA
After polishing the s substrate 101 to a thickness of about 50 μm, only the GaAs substrate is etched with a citric acid solution to remove Al.
Etching is stopped at the As layer 102. Next, only the AlAs layer 102 is selectively etched with hydrochloric acid.

Next, as shown in FIG. 6C, polyimide 30
0 is attached to the integrated circuit board 200. First, baking is performed at about 100 ° C. to cure the polyimide.

At this time, the quartz plate 400 and the light input / output substrate 1
Since the wax existing between 00 is melted by heat, the integrated circuit substrate 200 and the growth layer 100E of the optical input / output substrate are removed together from the quartz plate as shown in FIG. 6 (d). Then, the polyimide is finally cured at a high temperature of about 300 ° C. This state is the same as that of FIG. 4C of Example 1, and thereafter, the element can be manufactured in the same manner as in Example 1.

In this case, i-GaAs is selectively etched.
It is not necessary to expose the light absorption layer, and the semi-insulating GaAs substrate 101 may be attached to the integrated circuit substrate 200 while remaining. This example is shown in FIG.

(Part 2) After the optical input / output substrate is processed
When Bonding FIG. 8 shows a third specific example of the optical switch array to which the present invention is applied. The optical input / output board is the same as that of the second specific example shown in FIG.

FIG. 8 shows a method of manufacturing the optical switch. First,
Surface emitting laser 100B, MSM photodiode 100
After A is processed without treating the semi-insulating GaAs substrate 101, a flat quartz plate 400 is faced with the processed surface as shown in FIG.
Stick with 0. FIG. 8A 'is an enlarged view of the light input / output board.

Next, as shown in FIG.
The substrate is polished to a thickness of about 50 μm, then only the GaAs substrate is etched with PA30 solution, the etching is stopped at the AlAs layer, and only the AlAs layer is selectively etched with hydrochloric acid.

Next, as shown in FIG. 8C, after applying the polyimide 300 to both substrates, the infrared camera (C
While monitoring the circuit patterns of the integrated circuit board 200 and the optical input / output board 100 using a CD camera),
Both substrates are aligned and bonded using 0.

Next, as in the case of (No. 1), 100
The polyimide is cured at about 0 ° C., at the same time, both substrates are removed from the quartz plate, and then the temperature is raised to 300 ° C. to finally cure the polyimide 300 to obtain the structure shown in FIG. 8D. This state is the same as that shown in FIG. 4C, and thereafter, the same process as the previous specific example is performed.

In this case, similarly to the second specific example, it is not necessary to expose the i-GaAs light absorption layer by selective etching, and the semi-insulating GaAs substrate 101 can be attached to the integrated circuit substrate 200 while remaining. Good.

Example 3 An electric circuit is also formed on the optical input / output board.
In such a case , the surface emitting laser and the photodetector were formed on the light input / output substrate 100 in the above-described embodiments, but it is also possible to form an electric circuit such as an FET on the light input / output substrate 100. Here, an example in which an optical switch is configured by the same method as the first specific example will be described. The FET can be configured by epitaxial growth as described below or by ion implantation.

FIG. 9 is a sectional view of an optical input / output substrate when GaAs / AlGaAs multiple quantum wells are used for the active layer.

On the semi-insulating GaAs substrate 101, the AlAs layer 102 for selective etching, the p ⁺ -GaAs contact layer 120, the p-DBR layer 106, and the i-GaAs / Al layer are formed.
GaAs active layer 105, n-DBR layer 104, n-InGaP layer 121 (10 nm) as a selective etching layer,
N ⁺ -GaAs layer 122 as a contact layer for FET
(0.4 μm), n ⁻ −GaA as FET channel layer
s channel layer 123 (0.2 μm) and i-GaAs
The light absorption layer 107 (2 μm) was sequentially formed by the molecular beam epitaxial growth method. Be and Si were used for the p-type and n-type dopants, respectively. Where p-DB
R layer is p-AlAs (71.5 nm) / p-Al _0.15 G
a _0.85 As (62.9 nm) is alternately laminated for 25 periods, and the n-DBR layer has n-AlAs (71.5 nm).
nm) / n-Al _0.15 Ga _0.85 As (62.9 nm) is alternately laminated for 30 cycles.

This is processed as shown in FIG. 10 to produce an optical switch.

First, as shown in FIG. 10A, the optical input / output substrate 100 is adhered onto the integrated circuit substrate 200 using the polyimide 300 in the same manner as in the first embodiment, and thereafter, polishing and etching are performed. Epitaxial growth layer 10
Leave only 0E. FIG. 10A 'is an enlarged sectional view of the growth layer.

Next, as shown in FIG. 10B, mesa etching of the surface emitting laser section 100B is performed. FIG.
(B ') is an enlarged cross-sectional view of a surface emitting laser section. At this time, the mesa depth is changed to InGaP layer 1 by selective etching.
Reach by 21.

As for the process of FET, as shown in FIG. 10C, after etching the InGaP layer 121, FE is used.
Mesa etching of T100F is performed on the i-GaAs light absorption layer 1
Perform until 07. Next, the n ⁺ -GaAs contact layer 12
A source / drain electrode 124 is formed in 2. The recess etching is performed up to the n ^-- GaAs channel layer 123,
After that, the gate electrode 125 is formed. At this time, the electrodes of the MSM photodetector 100A are also formed at the same time.

Finally, as shown in FIG. 10D, electrical wiring 400 with the integrated circuit board 200 is provided.

As described above, when the electric circuit is also formed on the optical input / output substrate, the FE having a larger gain than that of Si is used.
Since T can be created and the integrated circuit can drive the surface emitting laser with only a small voltage amplitude, the load on the integrated circuit substrate can be reduced and a faster response can be achieved.

In the above specific examples, the MS is used as the light receiving element.
Although the example using the M photodiode has been described, the element of the semi-invention can be configured by using a pin photodiode, a photoconductor, or the like as the light receiving portion.

Example 4 FIG. 11 shows an example prepared using a pin photodiode. As illustrated, the pin photodiode 100G includes an n-GaAs layer 131, an i-GaAs light absorption layer 107, and a p-GaAs layer 130, and the insulating film 1
Integrated circuit board 2 by polyimide 300 through 32
00 and electrically connected by wiring 400. The structure of the surface emitting laser 100B is as described above. In this case, unlike the case of the MSM photodiode, since the conductive layer is also included in the light receiving portion, it is necessary to separate the light receiving portions from each other, and the light is not required when the integrated circuit substrate 200 and the light input / output substrate 100 are bonded. The insulating film 132 is vapor-deposited on the bonding surface of the input / output substrate 100, which is different from the above-described specific examples.

In the specific examples described so far, GaAs /
Although the optical switch is composed of AlGaAs, it is not limited to this, and InGaAs / InP, InAlAs / I
Other material systems such as nGaAs and GaAs / InGaAs can also be used. It goes without saying that GaAs, InP and the like can be used for the integrated circuit substrate in addition to silicon.

Further, in the above embodiments, only the optical switch array has been described, but it is clear that the present invention is effective for the configuration of other three-dimensional integrated circuits other than the optical switch array. In addition, according to the present invention, even when the elements integrated on the insulating film such as polyimide do not have different layer structures, the respective elements can be separated, so that electrical isolation (isolation) between the elements is facilitated. Has the advantage that

[0062]

As described above, the optical switch array according to the present invention has the features of combining the high speed and high functionality of the integrated circuit board with the high parallelism and high speed of the optical input / output board. There is. By connecting these elements in multiple stages by light, it becomes very promising as a future optical information processing element or an element for optical interconnection of LSI.

Further, according to the present invention, it becomes possible to form a three-dimensional semiconductor integrated circuit composed of semiconductor elements having different layer structures. Further, it becomes possible to provide a three-dimensional semiconductor integrated circuit having excellent isolation between elements.

[Brief description of drawings]

FIG. 1 is a diagram showing a cross-sectional structure of a device according to the present invention.

FIG. 2 is a diagram showing characteristics of the device of the present invention.

FIG. 3 is a cross-sectional view of an example of a light input / output board.

FIG. 4 is a diagram showing a method of manufacturing the optical switch according to the first embodiment.

FIG. 5 is a cross-sectional view of another example of the light input / output board.

FIG. 6 is a diagram showing a method of manufacturing the optical switch according to the second embodiment.

FIG. 7 is a cross-sectional view of an example in which selective etching is not used.

FIG. 8 is a diagram showing a method of manufacturing another specific example of the device of the present invention.

FIG. 9 is a cross-sectional view of a light input / output substrate forming an electric circuit.

FIG. 10 is a diagram showing a manufacturing method of an example in which an electric circuit is formed on a light input / output substrate.

FIG. 11 is a cross-sectional view of a specific example using a pin photodiode as a light receiving element.

FIG. 12 is a sectional view of a conventional example.

FIG. 13 is a characteristic diagram of a conventional example.

[Explanation of symbols]

101 semi-insulating GaAs substrate 102 AlAs layer for selective etching 103 n ⁺ -GaAs contact layer 104 n-DBR layer 105 active layer 106 p-DBR layer 107 i-GaAs light absorption layer 110 p-type electrode 111 n-type electrode 112 Schottky electrode 113 wiring metal 120 p ⁺ -GaAs contact layer 121 selective etching InGaP layer 122 n ⁺ -GaAs contact layer 123 n ^-- GaAs channel layer 130 p-GaAs layer 131 n-GaAs layer 132 insulating film

Claims (8)

[Claims] 1. A semiconductor substrate having semiconductor elements integrated on one main surface, an insulating layer disposed on the substrate, one or more semiconductor elements disposed on the insulating layer, and A wiring for electrically connecting a semiconductor element integrated on the semiconductor substrate and one or more semiconductor elements arranged on the insulating layer through a window formed in the insulating layer, Integrated semiconductor circuit. 2. The semiconductor integrated circuit according to claim 1, wherein the insulating layer is an organic material cured by heat treatment. 3. The semiconductor integrated circuit according to claim 1, further comprising a metal layer in contact with the semiconductor substrate and having a thickness equal to that of the insulating layer, in the insulating layer. 4. The semiconductor device integrated on the semiconductor substrate is an electric device, and the one or more semiconductor devices are:
It is composed of a light receiving element and a vertical cavity surface emitting laser, and the wiring is arranged so that a current generated by processing a signal current generated by the light receiving element by the electric element can be supplied to the vertical cavity surface emitting laser. The semiconductor integrated circuit according to claim 1, wherein the semiconductor integrated circuit is provided. 5. The semiconductor device integrated on the semiconductor substrate is an electric device, and the one or more semiconductor devices are:
The vertical resonator type surface is composed of a light receiving element, a vertical cavity surface emitting laser and other electric elements, and a signal current generated by the light receiving element is processed by the other electric element and the electric element to generate a current. 4. The wiring is arranged so that it can be supplied to a light emitting laser.
The semiconductor integrated circuit according to any one of 1. 6. The semiconductor integrated circuit according to claim 5, wherein the other electric element is a field effect transistor. 7. An optical switch comprising the light receiving element, the vertical cavity surface emitting laser, and the electric element is periodically arranged in plural on the one main surface. 4. The semiconductor integrated circuit according to 4. 8. A plurality of optical switches comprising the light receiving element, the vertical cavity surface emitting laser, the other electric element, and the electric element are periodically arranged on the one main surface. 7. The semiconductor integrated circuit according to claim 5, wherein: