JP2001176796A - Forming method of semiconductor film, and semiconductor device - Google Patents
Forming method of semiconductor film, and semiconductor deviceInfo
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- JP2001176796A JP2001176796A JP36194699A JP36194699A JP2001176796A JP 2001176796 A JP2001176796 A JP 2001176796A JP 36194699 A JP36194699 A JP 36194699A JP 36194699 A JP36194699 A JP 36194699A JP 2001176796 A JP2001176796 A JP 2001176796A
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- crystal
- film
- semiconductor film
- forming
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Abstract
Description
【0001】[0001]
【発明の属する技術分野】本発明は、半導体膜の形成方
法およびそれを用いた半導体装置に関し、特に、非単結
晶絶縁膜上または非単結晶絶縁基板上に形成された非晶
質または多結晶等の非単結晶半導体膜にエネルギーを加
えて、大略結晶方位が揃った大きな結晶粒または大略結
晶方位が揃った大面積の結晶性半導体膜を得ることがで
きる半導体膜の形成方法、およびその半導体膜を用いて
優れた性能を発揮することができる液晶ドライバーや半
導体メモリー、半導体論理回路等の半導体装置に関す
る。The present invention relates to a method for forming a semiconductor film and a semiconductor device using the same, and more particularly, to an amorphous or polycrystalline film formed on a non-single-crystal insulating film or a non-single-crystal insulating substrate. A method for forming a semiconductor film capable of obtaining large crystal grains having substantially uniform crystal orientation or a large-area crystalline semiconductor film having substantially uniform crystal orientation by applying energy to a non-single-crystal semiconductor film such as The present invention relates to a semiconductor device such as a liquid crystal driver, a semiconductor memory, or a semiconductor logic circuit that can exhibit excellent performance using a film.
【0002】[0002]
【従来の技術】従来から、基板上に形成した非単結晶絶
縁膜上または非単結晶絶縁基板上に、非晶質または多結
晶等の非単結晶の半導体膜を形成し、これに熱や光、荷
電粒子等のエネルギーを加えて単結晶化する方法が知ら
れている。この方法において、結晶欠陥が少なく、か
つ、結晶方位の揃った大きな結晶粒や、結晶方位の揃っ
た大面積の結晶性半導体膜を得るためには、不規則な核
発生を抑制して制御された結晶核を種結晶として結晶成
長させることが重要である。2. Description of the Related Art Conventionally, a non-single-crystal semiconductor film such as an amorphous or polycrystalline semiconductor film is formed on a non-single-crystal insulating film formed on a substrate or on a non-single-crystal insulating substrate, and heat or heat is applied thereto. There is known a method in which single crystal is formed by applying energy such as light and charged particles. In this method, in order to obtain large crystal grains with few crystal defects and uniform crystal orientation and a large-area crystalline semiconductor film with uniform crystal orientation, the generation is controlled by suppressing irregular nucleation. It is important to grow the crystal nuclei as seed crystals.
【0003】例えば、特開昭58−85519号公報に
は、図7に示すように、絶縁性基板9上にSi膜10を
形成し、このSi膜10に幅が狭小な狭小領域11と、
それに続く縁部がある角度をもって拡大する形状をなす
領域とをパターン加工し、それに熱エネルギーを照射す
る方法が提案されている。これにより、その狭小領域1
1に種結晶機能を付与してSi膜10を単結晶化するこ
とができるとされている。この狭小領域11の種結晶と
しては、狭小領域11に自然発生した結晶核を用いる方
法と、単結晶片を狭小領域11上に載置する方法が開示
されている(従来例1)。For example, in Japanese Patent Application Laid-Open No. 58-85519, as shown in FIG. 7, a Si film 10 is formed on an insulating substrate 9 and a narrow region 11 having a narrow width is formed on the Si film 10.
There has been proposed a method of patterning a region having a shape in which an edge portion is formed so as to expand at an angle, and irradiating the region with heat energy. Thereby, the narrow area 1
It is stated that the Si film 10 can be monocrystallized by imparting a seed crystal function to the silicon film 10. As a seed crystal of the narrow region 11, a method using a crystal nucleus naturally generated in the narrow region 11 and a method of placing a single crystal piece on the narrow region 11 are disclosed (conventional example 1).
【0004】また、USP4576676には、図8に
示すように、基板12上の多結晶Si膜13にくびれ部
15を形成し、このくびれ部15によって1つの結晶方
位を有する結晶粒のみを選択しようとする方法が開示さ
れている(従来例2)。なお、図8において、14は結
晶方位のフィルター部を示す。In U.S. Pat. No. 4,576,676, as shown in FIG. 8, a constricted portion 15 is formed in a polycrystalline Si film 13 on a substrate 12, and only a crystal grain having one crystal orientation is selected by the constricted portion 15. Is disclosed (conventional example 2). In FIG. 8, reference numeral 14 denotes a crystal orientation filter part.
【0005】さらに、Appl.Phys.Lett.
Vol.41 No.8 p.747〜p.749で
は、図9に示すように、多結晶Si膜16の一部17を
エッチング除去して砂時計のような細い部分18を形成
している。そして、多結晶Si膜16の熔融部がこの細
い部分18を通過するように結晶成長させることによ
り、結晶方位の選択を行っている(従来例3)。なお、
図9において、19は結晶成長方向を示す。Further, Appl. Phys. Lett.
Vol. 41 No. 8 p. 747-p. In 749, as shown in FIG. 9, a part 17 of the polycrystalline Si film 16 is removed by etching to form a thin part 18 like an hourglass. The crystal orientation is selected by growing the crystal so that the melted portion of the polycrystalline Si film 16 passes through the narrow portion 18 (Conventional Example 3). In addition,
In FIG. 9, 19 indicates the crystal growth direction.
【0006】さらに、特開平6−244103号公報に
は、触媒材料を導入して非晶質Si膜を結晶化させる方
法が開示されている。この方法では、まず、図10
(a)および図10(b)に示すように、基板20上に
SiO2膜21を介して非晶質Si膜22を形成し、そ
の上に、結晶化を助長する元素であるNi、Fe、Co
およびPtのうちの少なくとも一種類を含有する触媒材
料からなる膜23を、図10(a)に示すように全面的
に、または図10(b)に示すように部分的に形成す
る。その後でアニールを行うことにより、非晶質Si膜
22を結晶化させて結晶性Si膜を得る(従来例4)。Further, Japanese Patent Application Laid-Open No. Hei 6-244103 discloses a method of introducing a catalyst material to crystallize an amorphous Si film. In this method, first, FIG.
As shown in FIG. 10A and FIG. 10B, an amorphous Si film 22 is formed on a substrate 20 with an SiO 2 film 21 interposed therebetween, and Ni, Fe, which are elements for promoting crystallization, are formed thereon. , Co
A film 23 made of a catalyst material containing at least one of Pt and Pt is entirely formed as shown in FIG. 10A or partially formed as shown in FIG. 10B. Thereafter, by annealing, the amorphous Si film 22 is crystallized to obtain a crystalline Si film (conventional example 4).
【0007】[0007]
【発明が解決しようとする課題】しかしながら、上述し
た従来例1の方法のうち、図7に示した狭小領域11に
単結晶片を載置せずに狭小領域11で自然発生した結晶
核を種結晶として用いる方法では、1つの狭小領域11
から成長した領域は1つの結晶方位を有する結晶粒にな
るが、狭小領域11で発生する結晶核の方位は不規則で
あるため、必ずしも結晶成長しやすい方位を有する結晶
が成長するとは限らない。このため、結晶成長し難い方
位の結晶では、すぐに他の方位の結晶も成長してしま
い、多結晶になり易いという問題が生じる。また、図7
に示した形状のSi膜10が複数個ある場合には、各狭
小領域11で発生する種結晶の結晶方位が一致しないた
め、個々のSi膜10の結晶方位も一致しない。However, in the method of the prior art 1 described above, a single crystal piece is not placed in the narrow region 11 shown in FIG. In the method used as a crystal, one narrow region 11 is used.
Although the region grown from the above becomes a crystal grain having one crystal orientation, since the orientation of the crystal nucleus generated in the narrow region 11 is irregular, a crystal having an orientation that facilitates crystal growth does not always grow. For this reason, in a crystal having an orientation in which crystal growth is difficult, a crystal in another orientation also grows immediately, and there is a problem that the crystal tends to be polycrystalline. FIG.
In the case where there are a plurality of Si films 10 having the shapes shown in (1), the crystal orientations of the seed crystals generated in each of the narrow regions 11 do not match, so that the crystal orientations of the individual Si films 10 also do not match.
【0008】また、従来例1の方法のうち、狭小領域1
1に載置した単結晶片を種結晶として用いる方法では、
狭小領域11に種結晶とする結晶片を貼り付けるため、
固相成長の場合には結晶片と結晶化させたいSi膜10
の狭小領域11との貼り付け界面が原子レベルで清浄で
あることが必要である。このような清浄界面を形成し、
かつ、保持しておくことは非常に困難である。Further, in the method of the conventional example 1, the narrow area 1
In the method using the single crystal piece placed on 1 as a seed crystal,
In order to attach a seed piece as a seed crystal to the narrow area 11,
In the case of solid phase growth, crystal fragments and Si film 10 to be crystallized
It is necessary that the bonding interface with the narrow region 11 is clean at the atomic level. Forming such a clean interface,
And it is very difficult to keep.
【0009】上述した従来例2および従来例3の方法で
は、多結晶Siの熔融部をエッチングで形成した細い部
分を通過させる必要があるため、基板温度が上昇し、ガ
ラス等の安価な基板を用いることができない。In the above-described methods of Conventional Example 2 and Conventional Example 3, it is necessary to pass the melted portion of polycrystalline Si through a thin portion formed by etching, so that the substrate temperature rises and an inexpensive substrate such as glass can be used. Can not be used.
【0010】さらに、上述した従来例1、従来例2およ
び従来例3では、パターニングした多結晶Si膜のエッ
ジ側面と底面との交差部の形状に角がある場合には、そ
こで不規則な結晶方位を有する結晶核が発生しやすくな
る。なお、従来例1では、多結晶Si膜の底面とは、絶
縁性基板9とSi膜10との界面であり、従来例2では
基板12と多結晶Si膜13との界面であり、従来例3
では多結晶Si膜16と下地(図示せず)との界面であ
り、いずれもフラットである。Further, in the above-described conventional example 1, conventional example 2 and conventional example 3, when the shape of the intersection between the edge side surface and the bottom surface of the patterned polycrystalline Si film has an angle, the irregular crystal is formed there. Crystal nuclei having an orientation are likely to be generated. In the first conventional example, the bottom surface of the polycrystalline Si film is the interface between the insulating substrate 9 and the Si film 10, and in the second conventional example, the bottom surface of the polycrystalline Si film is the interface between the substrate 12 and the polycrystalline Si film 13. 3
Is an interface between the polycrystalline Si film 16 and a base (not shown), and both are flat.
【0011】上述した従来例4の方法のうち、図10
(a)に示した触媒材料からなる膜23を全面的に形成
する方法では、結晶成長の核が非晶質Si膜22の全面
にわたって不規則に発生するため、μmオーダーの結晶
粒が得られるに過ぎず、結晶方位の揃った大きな結晶粒
や単結晶領域を得ることは困難である。[0011] Of the above-described method of the conventional example 4, FIG.
In the method of forming the film 23 made of the catalyst material over the entire surface shown in (a), crystal growth nuclei are generated irregularly over the entire surface of the amorphous Si film 22, so that crystal grains on the order of μm can be obtained. However, it is difficult to obtain large crystal grains or single crystal regions with uniform crystal orientation.
【0012】さらに、上述した従来例4の方法のうち、
図10(b)のように触媒材料からなる膜25を部分的
に形成する方法では、触媒材料からなる膜23を形成し
た領域から形成していない領域に向かって結晶成長が進
むが、触媒材料からなる膜23を形成した領域内では核
発生が不規則に起こる。このため、図10(a)に示し
た方法に比べると、より長い結晶粒や単結晶領域が得ら
れるが、結晶粒の幅はμmオーダーのものが得られるに
過ぎず、さらに大きな結晶粒や単結晶領域を得ることは
困難である。Further, in the method of the above-mentioned conventional example 4,
In the method of partially forming the film 25 made of the catalyst material as shown in FIG. 10B, crystal growth proceeds from a region where the film 23 made of the catalyst material is formed to a region where the film 23 is not formed. Nucleation occurs irregularly in the region where the film 23 made of is formed. For this reason, as compared with the method shown in FIG. 10A, longer crystal grains and a single crystal region can be obtained, but the width of the crystal grains can only be obtained on the order of μm. Obtaining a single crystal region is difficult.
【0013】このような結晶方位が揃っていない半導体
膜を有する半導体膜を用いて液晶ドライバーや半導体メ
モリー、半導体論理回路等の半導体装置を作製した場合
には、トランジスタのキャリア移動度が小さくなった
り、閾値電圧が大きくなり、さらに、これらのバラツキ
も大きくなってしまうという問題がある。When a semiconductor device such as a liquid crystal driver, a semiconductor memory, or a semiconductor logic circuit is manufactured using a semiconductor film having a semiconductor film in which the crystal orientations are not aligned, the carrier mobility of the transistor may decrease. In addition, there is a problem that the threshold voltage increases, and furthermore, these variations also increase.
【0014】本発明はこのような従来技術の課題を解決
すべくなされたものであり、基板上に形成した非単結晶
絶縁膜上または非単結晶絶縁基板上に、かつ、大略結晶
方位が揃った大きな結晶粒または大略結晶方位が揃った
大面積の結晶性半導体膜を形成することができる半導体
膜の形成方法およびそれを用いた高性能な半導体装置を
提供することを目的とする。The present invention has been made to solve such problems of the prior art, and has a crystal orientation substantially uniform on a non-single-crystal insulating film or a non-single-crystal insulating substrate formed on a substrate. It is an object of the present invention to provide a method for forming a semiconductor film capable of forming a large-sized crystalline semiconductor film having large crystal grains or substantially aligned crystal orientations, and a high-performance semiconductor device using the same.
【0015】[0015]
【課題を解決するための手段】本発明の半導体膜の形成
方法は、基板上に形成した非単結晶絶縁膜上、または非
単結晶絶縁基板上に半導体膜を形成する方法であって、
該非単結晶絶縁膜または該非単結晶絶縁基板に、側面と
底面とが滑らかに連続する断面形状であって、かつ、く
びれ部を有する掘り込み部を形成する工程と、該非単結
晶絶縁膜上または該非単結晶絶縁基板上に非単結晶半導
体膜を形成して、該掘り込み部を埋め込む工程と、該非
単結晶半導体膜にエネルギーを加えることにより、該く
びれ部の一方側から反対側に該くびれ部を通過して結晶
成長を進ませる工程とを含み、そのことにより上記目的
が達成される。A method of forming a semiconductor film according to the present invention is a method of forming a semiconductor film on a non-single-crystal insulating film formed on a substrate or on a non-single-crystal insulating substrate,
A step of forming a dug portion having a cross section in which the side surface and the bottom surface are smoothly continuous with the non-single-crystal insulating film or the non-single-crystal insulating substrate, and having a constricted portion; Forming a non-single-crystal semiconductor film on the non-single-crystal insulating substrate and embedding the dug portion; and applying energy to the non-single-crystal semiconductor film to form the constriction from one side to the opposite side of the constriction portion. And allowing the crystal growth to proceed through the portion, whereby the above object is achieved.
【0016】前記非単結晶半導体膜をシリコン材料を用
いて形成してもよい。The non-single-crystal semiconductor film may be formed using a silicon material.
【0017】前記非単結晶半導体膜のくびれ部を挟んで
一方側にFe、Co、Ni、Cu、Ge、Pd、Auお
よびこれらの金属を含む化合物のうちの少なくとも一種
類を導入してもよい。At least one of Fe, Co, Ni, Cu, Ge, Pd, Au and a compound containing these metals may be introduced to one side of the constricted portion of the non-single-crystal semiconductor film. .
【0018】前記くびれ部の上面の幅を0.2μm以上
10μm以下に形成するのが好ましい。It is preferable that the width of the upper surface of the constricted portion is formed to be 0.2 μm or more and 10 μm or less.
【0019】前記くびれ部の上面の長さを0.5μm以
上100μm以下に形成するのが好ましい。It is preferable that the length of the upper surface of the constricted portion is formed to be 0.5 μm or more and 100 μm or less.
【0020】前記非単結晶半導体膜に対してエネルギー
を加える部分を、前記くびれ部の片側から反対側に移動
させてもよい。The portion for applying energy to the non-single-crystal semiconductor film may be moved from one side of the constricted portion to the other side.
【0021】前記非単結晶半導体膜に対してエネルギー
を略均一に加えてもよい。The energy may be substantially uniformly applied to the non-single-crystal semiconductor film.
【0022】本発明の半導体装置は、本発明の半導体膜
の形成方法により得られる半導体膜を用いており、その
ことにより上記目的が達成される。The semiconductor device of the present invention uses the semiconductor film obtained by the method of forming a semiconductor film of the present invention, thereby achieving the above object.
【0023】以下、本発明の作用について説明する。Hereinafter, the operation of the present invention will be described.
【0024】本発明にあっては、非単結晶絶縁膜または
非単結晶絶縁基板に、側面と底面とが滑らかに連続する
断面形状であって、かつ、くびれ部を有する掘り込み部
を形成し、その掘り込み部に非単結晶半導体膜を埋め込
む。そして、非単結晶半導体膜にエネルギーを加えるこ
とにより、くびれ部を通過して結晶成長を進ませる。こ
れにより、くびれ部の片側で不規則に発生する多数の結
晶核のうち、材料および構造に特有の結晶成長し易い方
位の結晶を、くびれ部で選択する。さらに、結晶成長が
くびれ部を通過した後、結晶粒を大きく成長させたい領
域においてエッジ部で不規則な結晶核が生じるのを、掘
り込み部の側面と底面とを滑らかに連続する断面形状に
することによって抑制する。よって、大略結晶方位が揃
った大きな結晶粒または大略結晶方位が揃った大面積の
結晶性半導体膜を形成することが可能となる。According to the present invention, a non-single-crystal insulating film or a non-single-crystal insulating substrate is formed with a dug portion having a cross-sectional shape where a side surface and a bottom surface are smoothly continuous and having a constricted portion. Then, a non-single-crystal semiconductor film is embedded in the dug portion. Then, by applying energy to the non-single-crystal semiconductor film, crystal growth proceeds through the constricted portion. As a result, of the many crystal nuclei irregularly generated on one side of the constricted portion, a crystal having an orientation easy to grow and which is peculiar to the material and the structure is selected in the constricted portion. Furthermore, after the crystal growth passes through the constricted portion, the occurrence of irregular crystal nuclei at the edge portion in the region where crystal grains are to grow larger is changed to a cross-sectional shape that smoothly connects the side surface and the bottom surface of the dug portion. Suppress by doing. Therefore, it is possible to form a large crystal grain having a substantially uniform crystal orientation or a large-area crystalline semiconductor film having a substantially uniform crystal orientation.
【0025】上記非単結晶半導体膜としては、シリコン
材料(Si膜)や、SiGe、GaAs、InP等の化
合物半導体を用いることができる。なお、シリコン材料
は、単一元素からなる半導体膜なので、化合物半導体を
用いた場合のように組成のわずかなズレによる結晶欠陥
が生じず、より安定した良好な結晶性半導体膜が得られ
易い。また、シリコンは通常のLSIに広く用いられて
いる材料であり、本発明を用いて形成した半導体膜はこ
れらに広く利用可能である。As the non-single-crystal semiconductor film, a silicon material (Si film) or a compound semiconductor such as SiGe, GaAs or InP can be used. Note that since a silicon material is a semiconductor film made of a single element, a crystal defect due to a slight shift in composition does not occur as in the case of using a compound semiconductor, and a more stable and favorable crystalline semiconductor film is easily obtained. Silicon is a material widely used for ordinary LSIs, and a semiconductor film formed by using the present invention can be widely used for these.
【0026】上記くびれ部の上面の幅を0.2μmより
狭くしたり、くびれ部の上面の長さを100μmより長
くすると、くびれ部の片側(結晶成長方向に向かって入
り口側)で発生した結晶核がくびれ部を通過して反対側
まで結晶方位を引き継いで成長しなくなる。また、くび
れ部の上面の幅を10μmより広くしたり、くびれ部の
上面の長さを0.5μmより短くすると、くびれ部での
結晶方位選択効果が低下して、くびれ部の片側(結晶成
長方向に向かって入り口側)で発生した複数の結晶方位
を有する結晶核がくびれ部を通過して反対側まで成長し
てしまい、結晶方位の揃った大きな結晶粒または結晶方
位の揃った大面積の結晶性半導体膜を形成することがで
きなくなる。よって、くびれ部の上面の幅を0.2μm
以上10μm以下にし、くびれ部の上面の長さを0.5
μm以上100μm以下にすれば、結晶方位の選択効果
がより確実になるので好ましい。なお、掘り込み部の広
い部分(くびれ部の両側)の幅や長さには特に制限は無
い。また、非晶質Si膜の膜厚(掘り込み部の厚み)に
ついては、くびれ部の厚さが10μmより厚くなると、
くびれ部の幅が広くなったのと同様に、膜厚方向に異な
った結晶方位を有する複数の結晶粒がくびれ部を通過す
るようになり、結晶方位選択効果が悪くなる。When the width of the upper surface of the constricted portion is made smaller than 0.2 μm or the length of the upper surface of the constricted portion is made longer than 100 μm, the crystal generated on one side of the constricted portion (the entrance side in the crystal growth direction). The nucleus passes through the constricted portion and inherits the crystal orientation to the opposite side and stops growing. Further, when the width of the upper surface of the constricted portion is made wider than 10 μm or the length of the upper surface of the constricted portion is made smaller than 0.5 μm, the crystal orientation selecting effect at the constricted portion is reduced, and one side of the constricted portion (crystal growth) The crystal nuclei having a plurality of crystal orientations generated on the entrance side toward the direction) pass through the constricted portion and grow to the opposite side, and have large crystal grains with uniform crystal orientation or large areas with uniform crystal orientation. A crystalline semiconductor film cannot be formed. Therefore, the width of the upper surface of the constricted portion is set to 0.2 μm
Not less than 10 μm and the length of the upper surface of the constricted portion is 0.5
It is preferable that the thickness be in the range of μm or more and 100 μm or less, because the effect of selecting the crystal orientation becomes more reliable. There is no particular limitation on the width or length of the wide portion of the dug portion (both sides of the constricted portion). As for the thickness of the amorphous Si film (the thickness of the dug portion), when the thickness of the constricted portion is larger than 10 μm,
As in the case where the width of the constricted portion is increased, a plurality of crystal grains having different crystal orientations in the film thickness direction pass through the constricted portion, and the crystal orientation selection effect is deteriorated.
【0027】この非単結晶半導体膜に対してエネルギー
を部分的に加える場合、そのエネルギーを加える部分を
くびれ部の片側から反対側に移動させることにより、結
晶成長をくびれ部を通過して進ませることができる。When energy is partially applied to the non-single-crystal semiconductor film, the crystal growth proceeds through the constricted portion by moving the portion to which the energy is applied from one side of the constricted portion to the opposite side. be able to.
【0028】さらに、非単結晶半導体膜のくびれ部を挟
んで一方側に、結晶化を容易にするFe、Co、Ni、
Cu、Ge、Pd、Auおよびこれらの金属を含む化合
物のうちの少なくとも一種類を導入すれば、その導入部
で結晶核を発生させることができる。この場合には、非
単結晶半導体膜に対してエネルギーを略均一に加えて
も、結晶化を容易にする物質を導入した側で発生した結
晶核を種として横方向に結晶成長が進み、結晶成長を結
晶化を容易にする物質を導入した側からくびれ部や滑ら
かなエッジ形状を有する部分、段差部を通過して進ませ
ることができる。Further, on one side of the constricted portion of the non-single-crystal semiconductor film, Fe, Co, Ni,
If at least one of Cu, Ge, Pd, Au and a compound containing these metals is introduced, a crystal nucleus can be generated at the introduced portion. In this case, even when energy is applied substantially uniformly to the non-single-crystal semiconductor film, crystal growth proceeds in the lateral direction using the crystal nuclei generated on the side where the substance that facilitates crystallization is introduced as seeds, The growth can proceed through a constricted portion, a portion having a smooth edge shape, and a step portion from the side where the substance that facilitates crystallization is introduced.
【0029】このようにして得られる結晶方位の揃った
大きな結晶粒または結晶方位の揃った大面積の結晶性半
導体膜を用いれば、トランジスタのキャリア移動度を大
きく、閾値電圧を小さくすることが可能であり、さら
に、これらのバラツキも小さくすることができるので、
特性の向上を図ることが可能である。By using the thus obtained large-sized crystal grains having a uniform crystal orientation or a large-area crystalline semiconductor film having a uniform crystal orientation, the carrier mobility of the transistor can be increased and the threshold voltage can be reduced. In addition, since these variations can be reduced,
It is possible to improve the characteristics.
【0030】なお、本発明において、掘り込み部の側面
と底面とが滑らかに連続する断面形状とは、大略、側面
と底面との交差部の断面形状の2次微分が連続関数であ
ることを言う。また、本発明において、くびれ部の幅と
は図11に示す最も狭い部分の幅Wの寸法を示し、くび
れ部の長さとは図11に示す最も狭い部分の長さLの寸
法を示す。In the present invention, the cross-sectional shape where the side surface and the bottom surface of the dug portion are smoothly continuous generally means that the second derivative of the cross-sectional shape of the intersection between the side surface and the bottom surface is a continuous function. To tell. Further, in the present invention, the width of the constricted portion indicates the size of the width W of the narrowest portion shown in FIG. 11, and the length of the constricted portion indicates the size of the length L of the narrowest portion shown in FIG.
【0031】[0031]
【発明の実施の形態】以下に、本発明の実施の形態につ
いて、図面を参照しながら説明する。Embodiments of the present invention will be described below with reference to the drawings.
【0032】(実施形態1)本実施形態1では、非単結
晶絶縁膜または非単結晶絶縁基板に、側面と底面とが滑
らかに連続する断面形状であって、かつ、くびれ部を有
する掘り込み部を形成して、その掘り込み部に非単結晶
半導体膜を埋め込んでエネルギーを加え、くびれ部を通
過して結晶成長を進ませて、大略結晶方位が揃った大き
な結晶粒または大略結晶方位が揃った大面積の結晶性半
導体膜を形成する例について説明する。(Embodiment 1) In Embodiment 1, a non-single-crystal insulating film or a non-single-crystal insulating substrate has a dug shape having a smoothly continuous side surface and bottom surface and a constricted portion. A portion is formed, a non-single-crystal semiconductor film is buried in the dug portion, energy is applied, crystal growth proceeds through a constricted portion, and a large crystal grain or a substantially crystal orientation having a substantially uniform crystal orientation is formed. An example in which a uniform large-area crystalline semiconductor film is formed is described.
【0033】図1(a)〜図1(c)は実施形態1の半
導体膜の形成方法について説明するための斜視図であ
り、図1(d)は断面図である。まず、図1(a)に示
すように、ガラス基板1に、CF4ガスとO2ガスを用い
たRIE(反応性イオンエッチング)法と緩衝フッ酸に
よる湿式エッチングとを組み合わせて、上面の幅が5μ
mで長さが20μmのくびれ部2を有し、かつ、側面と
底面とが滑らかに連続する断面形状を持つ掘り込み部3
を形成する。この掘り込み部3の断面形状は、図1
(d)の断面図に示すように、側面を略円周の1/4に
形成して底面に滑らかに連続させる。FIGS. 1A to 1C are perspective views for explaining a method of forming a semiconductor film according to the first embodiment, and FIG. 1D is a sectional view. First, as shown in FIG. 1A, the width of the upper surface of a glass substrate 1 is formed by combining RIE (reactive ion etching) using CF 4 gas and O 2 gas with wet etching using buffered hydrofluoric acid. Is 5μ
dug portion 3 having a constricted portion 2 having a length of 20 μm and a length of 20 μm, and having a sectional shape in which a side surface and a bottom surface are smoothly continuous.
To form The sectional shape of the dug portion 3 is shown in FIG.
As shown in the cross-sectional view of (d), the side surface is formed to be approximately 1/4 of the circumference and smoothly connected to the bottom surface.
【0034】次に、図1(b)に示すように、減圧CV
D(化学気相成長)法によりSi2H6ガスを用いて非晶
質Si膜4を100nmの厚みに形成し、その一部をR
IE法によりCF4ガスとO2ガスを用いてエッチングし
て、非晶質Si膜4をガラス基板1の掘り込み部3に埋
め込む。Next, as shown in FIG.
An amorphous Si film 4 having a thickness of 100 nm is formed by a D (chemical vapor deposition) method using Si 2 H 6 gas,
The amorphous Si film 4 is buried in the dug portion 3 of the glass substrate 1 by etching using CF 4 gas and O 2 gas by the IE method.
【0035】その上に、図1(c)に示すように、常圧
CVD法によりSiH4ガスとO2ガスを用いてSiO2
膜5を100nmの厚みに形成した後、ライン状ヒータ
ー6を用いて局所的に600℃となるように加熱し、矢
印Vに示すように、加熱部をくびれ部2の片側から反対
側へ、くびれ部2を通って1cm/時の速度で移動させ
て横方向への結晶成長を継続させる。このようにSiO
2膜5を非晶質Si膜4の上に形成することにより、エ
ネルギー印加を行って結晶成長させる際に、非晶質Si
膜4の表面に低品質のSiO2膜が形成されるのを防ぐ
ことが可能である。また、この加熱の際に、局所加熱部
とその周りの基板の温度差が大きすぎると、基板が熱歪
みのために沿ってしまう。そこで、結晶成長の起こらな
い範囲で基板全体を加熱することにより、基板の反りの
発生を防止することができる。但し、基板全体の加熱温
度を上げ過ぎると、局所加熱部以外でも不規則な核発生
が生じて、大きな結晶粒または単結晶領域が得られなく
なる。そこで、本実施形態では、ガラス基板1全体を4
00℃に加熱した。[0035] thereon, as shown in FIG. 1 (c), SiO 2 using SiH 4 gas and O 2 gas by atmospheric pressure CVD
After forming the film 5 to a thickness of 100 nm, the film 5 is locally heated to 600 ° C. using the linear heater 6, and the heating portion is moved from one side of the constricted portion 2 to the opposite side as shown by an arrow V. The crystal is moved at a speed of 1 cm / hour through the constriction 2 to continue the crystal growth in the lateral direction. Thus, SiO
By forming the 2 film 5 on the amorphous Si film 4, during crystal growth of performing energization, amorphous Si
It is possible to prevent a low-quality SiO 2 film from being formed on the surface of the film 4. In addition, during this heating, if the temperature difference between the local heating portion and the substrate around it is too large, the substrate will follow along due to thermal distortion. Thus, by heating the entire substrate within a range where crystal growth does not occur, the occurrence of substrate warpage can be prevented. However, if the heating temperature of the entire substrate is excessively increased, irregular nuclei are generated even in a portion other than the local heating portion, so that large crystal grains or single crystal regions cannot be obtained. Therefore, in the present embodiment, the entire glass substrate 1 is
Heated to 00 ° C.
【0036】このように、ガラス基板1に形成した、く
びれ部2を有し、かつ、側面と底面とが滑らかに連続す
る断面形状を持つ掘り込み部3に、非晶質Si膜4を埋
め込み、くびれ部2を通過して結晶成長させることによ
り、くびれ部2の片側(入り口側)の非晶質Si膜4で
不規則に発生した多数の結晶核のうち、材料および構造
に特有の結晶成長しやすい方位の結晶をくびれ部2で選
択し、かつ、くびれ部2の反対側(出口側)の結晶粒を
大きく結晶成長させたい領域で不規則な結晶核が生じる
のを、掘り込み部3の側面と底面とを滑らかに連続する
断面形状にすることにより抑制することができる。よっ
て、大略(111)面に配向した大面積の結晶性Si膜
を得ることができる。As described above, the amorphous Si film 4 is embedded in the dug portion 3 having the constricted portion 2 formed on the glass substrate 1 and having the cross-sectional shape in which the side surface and the bottom surface are smoothly continuous. Out of a large number of crystal nuclei irregularly generated in the amorphous Si film 4 on one side (entrance side) of the constricted portion 2 by growing the crystal through the constricted portion 2, A crystal having an orientation that facilitates growth is selected at the constricted portion 2, and an irregular crystal nucleus is generated in a region where crystal grains on the opposite side (exit side) of the constricted portion 2 are to be grown. This can be suppressed by forming the side surface and the bottom surface of the third member into a smoothly continuous cross-sectional shape. Therefore, a large-area crystalline Si film oriented substantially in the (111) plane can be obtained.
【0037】(実施形態2)本実施形態2では、上述し
た実施形態1の半導体膜の形成方法において、くびれ部
の片側(入り口)の半導体膜の一部にその結晶化を容易
にする物質を導入し、エネルギーを均一に加えた例につ
いて説明する。(Embodiment 2) In Embodiment 2, in the method of forming a semiconductor film of Embodiment 1 described above, a substance that facilitates crystallization is added to a part of the semiconductor film on one side (entrance) of the constricted portion. An example in which energy is introduced and energy is applied uniformly will be described.
【0038】図2(a)は実施形態2の半導体膜の形成
方法について説明するための斜視図であり、図2(b)
は断面図である。まず、実施形態1と同様にして、ガラ
ス基板1に、上面の幅が5μm、長さが20μmのくび
れ部2を有し、かつ、側面と底面とが滑らかに連続する
断面形状を持つ掘り込み部3を形成して、非晶質Si膜
4を掘り込み部3に埋め込む。この掘り込み部3の断面
形状は、図2(b)の断面図に示すように、側面を略円
周の1/8に形成して底面に滑らかに連続させる。FIG. 2A is a perspective view for explaining a method of forming a semiconductor film according to the second embodiment, and FIG.
Is a sectional view. First, in the same manner as in the first embodiment, the glass substrate 1 has a constricted portion 2 having a top surface width of 5 μm and a length of 20 μm, and a cross-sectional shape in which the side surface and the bottom surface are smoothly continuous. The portion 3 is formed, and the amorphous Si film 4 is embedded in the dug portion 3. As shown in the cross-sectional view of FIG. 2B, the cross-sectional shape of the dug portion 3 is such that the side surface is formed to be approximately 1/8 of the circumference and smoothly connected to the bottom surface.
【0039】その上に、実施形態1と同様にして、Si
O2膜5を100nmの厚みに形成した後、RIE法に
よりCF4ガスとCHF3ガスを用いてSi02膜5をエ
ッチングして非晶質Si膜4の一部を露出させる。そし
て、非晶質Si膜4の露出部7にスパッタリング法によ
りNiを1nmの厚みに蒸着し、炉を用いて600℃に
なるように均一加熱8して、非晶質Si膜4の露出部7
にNiを蒸着した側からくびれ部2を通って反対側へ、
横方向への結晶成長を継続させる。Further, in the same manner as in the first embodiment, Si
After forming the O 2 film 5 to a thickness of 100 nm, the SiO 2 film 5 is etched by RIE using CF 4 gas and CHF 3 gas to expose a part of the amorphous Si film 4. Then, Ni is vapor-deposited on the exposed portion 7 of the amorphous Si film 4 to a thickness of 1 nm by a sputtering method, and is uniformly heated 8 at 600 ° C. by using a furnace to expose the exposed portion of the amorphous Si film 4. 7
From the side on which Ni is deposited to the opposite side through the constricted portion 2,
Continue the crystal growth in the lateral direction.
【0040】このように、均一な加熱であっても、Ni
を蒸着した部分の非晶質Si膜4は結晶化が起こり易い
ため、まず、その部分で結晶核が発生し、それを種とし
て結晶成長がくびれ部2を通って反対側まで進む。本実
施形態では、大略(110)面に配向した大面積の結晶
性Si膜が得られた。Thus, even with uniform heating, Ni
Since the crystallization is likely to occur in the portion of the amorphous Si film 4 where is deposited, first, a crystal nucleus is generated in that portion, and crystal growth proceeds to the opposite side through the constricted portion 2 using the seed as a seed. In the present embodiment, a large-area crystalline Si film oriented substantially in the (110) plane was obtained.
【0041】なお、スパッタリング法によりNiを蒸着
する際に、SiO2膜5上にもNiが蒸着されるが、S
iO2膜5がNiの拡散のバリアとなってSiO2膜5下
の非晶質Si膜4まではNiが拡散しない。よって、こ
のNiの影響は生じない。When Ni is deposited by sputtering, Ni is also deposited on the SiO 2 film 5.
The iO 2 film 5 serves as a barrier for Ni diffusion, and Ni does not diffuse to the amorphous Si film 4 under the SiO 2 film 5. Therefore, the effect of Ni does not occur.
【0042】(実施形態3)本実施形態3では、上述し
た実施形態1の半導体膜の形成方法において、個々のく
びれ部に対して基板の掘り込み部を1つ1つの島状にパ
ターニングするのではなく、複数個の島状の部分を連結
させた形状にパターニングした例について説明する。(Embodiment 3) In Embodiment 3, in the method of forming a semiconductor film of Embodiment 1 described above, the recessed portions of the substrate are patterned into individual islands for each constricted portion. Instead, an example in which a plurality of island-shaped portions are patterned into a connected shape will be described.
【0043】図3は実施形態3の半導体膜の形成方法に
ついて説明するための斜視図である。まず、実施形態1
と同様にして、図3(a)に示すように、ガラス基板1
に上面の幅が5μm、長さが20μmの複数個のくびれ
部2を有し、かつ、側面と底面とが滑らかに連続する形
状を持つ掘り込み部3を形成する。この掘り込み部3の
断面形状は、図1(d)に示したものと同様である。FIG. 3 is a perspective view for explaining a method of forming a semiconductor film according to the third embodiment. First, Embodiment 1
In the same manner as described above, as shown in FIG.
A dug portion 3 having a plurality of constricted portions 2 having a top surface width of 5 μm and a length of 20 μm and having a shape in which a side surface and a bottom surface are smoothly continuous is formed. The cross-sectional shape of the dug portion 3 is the same as that shown in FIG.
【0044】次に、図3(b)に示すように、非晶質S
i膜4により掘り込み部3を埋め込む。Next, as shown in FIG.
The dug portion 3 is buried with the i film 4.
【0045】その上に、図3(c)に示すように、Si
O2膜5を100nmの厚みに形成した後、ライン状ヒ
ーター6を用いて局所的に600℃となるように加熱
し、矢印Vに示すように、加熱部をくびれ部2の片側か
ら反対側へ、くびれ部2を通って1cm/時の速度で移
動させて横方向への結晶成長を継続させる。このとき、
ガラス基板1全体を400℃に加熱しておく。On top of that, as shown in FIG.
After the O 2 film 5 is formed to a thickness of 100 nm, it is locally heated to 600 ° C. using the linear heater 6, and the heating portion is moved from one side of the constricted portion 2 to the opposite side as shown by an arrow V. The crystal is moved at a speed of 1 cm / hour through the constriction 2 to continue the crystal growth in the lateral direction. At this time,
The entire glass substrate 1 is heated to 400.degree.
【0046】このように個々のくびれ部2に対して掘り
込み部3を複数個連結させた形状にすることにより、全
体として大略結晶方位が揃った大きな結晶粒または大略
結晶方位の揃った大面積の結晶性半導体膜を得ることが
できる。本実施形態では、大略(111)面に配向した
大面積の結晶性Si膜が得られた。As described above, by forming a shape in which a plurality of engraved portions 3 are connected to the individual constricted portions 2, large crystal grains having substantially the same crystal orientation as a whole or a large area having substantially the same crystal orientation are provided as a whole. Can be obtained. In this embodiment, a large-area crystalline Si film oriented substantially in the (111) plane was obtained.
【0047】(実施形態4)本実施形態4では、上述し
た実施形態3の半導体膜の形成方法において、くびれ部
の片側(入り口)の半導体膜の一部にその結晶化を容易
にする物質を導入し、エネルギーを均一に加えた例につ
いて説明する。(Embodiment 4) According to Embodiment 4, in the method of forming a semiconductor film of Embodiment 3 described above, a material that facilitates crystallization of a part of the semiconductor film on one side (entrance) of the constricted portion is used. An example in which energy is introduced and energy is applied uniformly will be described.
【0048】図4は実施形態4の半導体膜の形成方法に
ついて説明するための斜視図である。まず、実施形態3
と同様にして、ガラス基板1に、上面の幅が5μm、長
さが20μmのくびれ部2を有し、かつ、側面と底面と
が滑らかに連続する断面形状を持つ掘り込み部3を形成
して、非晶質Si膜4を掘り込み部3に埋め込む。この
掘り込み部3の断面形状は、図2(b)に示したものと
同様である。FIG. 4 is a perspective view for explaining a method of forming a semiconductor film according to the fourth embodiment. First, Embodiment 3
In the same manner as described above, a dug portion 3 having a constricted portion 2 having a top surface width of 5 μm and a length of 20 μm and having a cross-sectional shape where a side surface and a bottom surface are smoothly continuous is formed on the glass substrate 1. Then, the amorphous Si film 4 is embedded in the dug portion 3. The cross-sectional shape of the dug portion 3 is the same as that shown in FIG.
【0049】その上に、実施形態2と同様にして、非晶
質Si膜4の一部が露出するようにSiO2膜5を10
0nmの厚みに形成した後、非晶質Si膜4の露出部7
にNiを1nmの厚みに蒸着し、炉を用いて600℃に
なるように均一加熱8して、非晶質Si膜4の露出部7
にNiを蒸着した側からくびれ部2を通って反対側へ、
横方向への結晶成長を継続させる。Further, as in the second embodiment, an SiO 2 film 5 is formed so that a part of the amorphous Si film 4 is exposed.
After being formed to a thickness of 0 nm, the exposed portions 7 of the amorphous Si film 4
Then, Ni is vapor-deposited to a thickness of 1 nm, and is uniformly heated 8 at 600 ° C. using a furnace to expose exposed portions 7 of the amorphous Si film 4.
From the side on which Ni is deposited to the opposite side through the constricted portion 2,
Continue the crystal growth in the lateral direction.
【0050】このように、均一な加熱であっても、Ni
を蒸着した部分の非晶質Si膜4は結晶化が起こり易い
ため、まず、その部分で結晶核が発生し、それを種とし
て結晶成長がくびれ部2を通って反対側まで進む。本実
施形態では、大略(110)面に配向した大面積の結晶
性Si膜が得られた。Thus, even with uniform heating, Ni
Since the crystallization is likely to occur in the portion of the amorphous Si film 4 where is deposited, first, a crystal nucleus is generated in that portion, and crystal growth proceeds to the opposite side through the constricted portion 2 using the seed as a seed. In the present embodiment, a large-area crystalline Si film oriented substantially in the (110) plane was obtained.
【0051】(比較例)この比較例では、掘り込み部の
断面形状において側面と底面の交差部に角部を形成した
例について説明する。(Comparative Example) In this comparative example, an example in which a corner is formed at the intersection of the side surface and the bottom surface in the cross-sectional shape of the dug portion will be described.
【0052】図12は比較例の半導体膜の形成方法につ
いて説明するための図であり、(b)は上面図、(a)
は(b)のA−B線による断面図である。FIGS. 12A and 12B are views for explaining a method of forming a semiconductor film of a comparative example, where FIG. 12B is a top view and FIG.
FIG. 3B is a cross-sectional view taken along line AB in FIG.
【0053】図12(a)に示すように、ガラス基板1
に、RIE法によりCF4ガスとO2ガスを用いて、側面
と底面の交差部が角24を有する掘り込み部3aを深さ
100nmに形成する。この掘り込み部3aは、図12
(b)に示すように、幅が5μm、長さが20μmのく
びれ部2を有するようにする。その上に、減圧CVD法
によりSi2H6ガスを用いて非晶質Si膜4を100n
mの厚みに形成し、その一部をRIE法によりCF4ガ
スとO2ガスを用いてエッチングして、非晶質Si膜4
をガラス基板1の掘り込み部3aに埋め込む。その上
に、常圧CVD法によりSiH4ガスとO2ガスを用いて
SiO2膜5を非晶質Si膜4の一部が露出するように
100nmの厚みに形成して、非晶質Si膜4の露出部
7にスパッタリング法でNiを1nmの厚みに蒸着す
る。この状態で、ライン状ヒーター6を用いて局所的に
600℃となるように加熱し、矢印Vに示すように、加
熱部をくびれ部2に対してNiを蒸着した側から反対側
へ、くびれ部2を通って1cm/時の速度で移動させて
横方向への結晶成長を継続させる。このとき、ガラス基
板1全体を400℃に加熱しておく。As shown in FIG. 12A, the glass substrate 1
Then, a dug portion 3a having a corner 24 at the intersection of the side surface and the bottom surface is formed to a depth of 100 nm by using the CF 4 gas and the O 2 gas by the RIE method. This dug portion 3a is formed as shown in FIG.
As shown in (b), a constricted portion 2 having a width of 5 μm and a length of 20 μm is provided. On top of this, an amorphous Si film 4 is formed to a thickness of 100 n using a Si 2 H 6 gas by a low pressure CVD method.
m, and a part of the amorphous Si film 4 is etched by RIE using CF 4 gas and O 2 gas.
Is embedded in the dug portion 3a of the glass substrate 1. An SiO 2 film 5 is formed thereon by a normal pressure CVD method using SiH 4 gas and O 2 gas to a thickness of 100 nm so that a part of the amorphous Si film 4 is exposed. Ni is deposited to a thickness of 1 nm on the exposed portion 7 of the film 4 by a sputtering method. In this state, the heater is locally heated to 600 ° C. using the linear heater 6, and the heating portion is constricted from the side where Ni is deposited on the constricted portion 2 to the opposite side as shown by the arrow V. It is moved at a speed of 1 cm / hour through the part 2 to continue the crystal growth in the lateral direction. At this time, the entire glass substrate 1 is heated to 400 ° C.
【0054】このように、非晶質Si膜4にNiを蒸着
した場合には、結晶成長し易い方位としてくびれ部2で
(110)面が選択される。しかし、掘り込み部3aの
側面と底面の交差部が角24を持つ場合には、くびれ部
2で(110)面が選択されても、その後の掘り込み部
3aの側面と底面の交差部が角24で不規則な結晶核が
生じる。その結果、例えば(111)面や(112)
面、(114)面、(123)面、(334)面、(3
45)面等の各種面方位を有する結晶核の発生が起こ
り、結晶方位の揃った大きな結晶性Si膜が得られな
い。As described above, when Ni is vapor-deposited on the amorphous Si film 4, the (110) plane is selected in the constricted portion 2 as a direction in which crystal growth is easy. However, when the intersection of the side surface and the bottom surface of the dug portion 3a has a corner 24, even if the (110) plane is selected in the constricted portion 2, the intersection of the subsequent side surface and the bottom surface of the dug portion 3a is formed. At the corner 24, irregular crystal nuclei occur. As a result, for example, (111) plane or (112)
Plane, (114) plane, (123) plane, (334) plane, (3
45) Crystal nuclei having various plane orientations such as planes are generated, and a large crystalline Si film having a uniform crystal orientation cannot be obtained.
【0055】(実施形態5)この実施形態5では、上述
した各実施形態の半導体膜の形成方法で作製した結晶性
Si薄膜を用いて薄膜トランジスタ等の半導体装置を形
成する方法を説明する。(Embodiment 5) In Embodiment 5, a method for forming a semiconductor device such as a thin film transistor using the crystalline Si thin film produced by the method for forming a semiconductor film of each of the above embodiments will be described.
【0056】図6は実施形態5の半導体装置の製造方法
について説明するための断面図である。具体的には、上
述した各実施形態のいずれかで作製した結晶性Si薄膜
49を、RIE(Reactive Ion Etch
ing)法によりCF4ガスとO2ガスを用いてパターニ
ングする。そして、通常の薄膜トランジスタ製造工程と
同様にして、プラズマCVD法によりTEOS(テトラ
エトキシシラン)ガスとO3ガスを用いてSiO2からな
るゲート絶縁膜10を形成する。その上にスパッタリン
グ法によりWSi2/多結晶Siを成膜し、RIE法に
よりCF4ガスとO2ガスを用いてパターニングしてゲー
ト電極11を形成する。次に、ソース・ドレイン領域に
イオンドーピング法によりP(リン)やB(ホウ素)の
注入を行う。そして、プラズマCVD法によりTEOS
ガスとO3ガスを用いてSiO2からなる絶縁膜12を形
成し、RIE法によりCF4ガスとO2ガスを用いて絶縁
膜12のエッチングを行ってコンタクトホールを形成す
る。その上にスパッタリング法によりAl膜を成膜し
て、RIE法によりBCl3ガスとCl2ガスを用いてパ
ターニングして配線13を形成する。次に、プラズマC
VD法によりSiH 4ガスとNH3ガスとN2ガスを用い
てSiNからなる保護膜14を形成し、最後にRIE法
によりCF4ガスとCHF3ガスを用いて保護膜14の一
部をエッチングして窓開けする。以上により薄膜トラン
ジスタや抵抗、キャパシタ等を備えた半導体装置を作製
することができる。FIG. 6 shows a method of manufacturing a semiconductor device according to the fifth embodiment.
FIG. 3 is a cross-sectional view for explaining the method. Specifically, on
Crystalline Si thin film prepared in any of the embodiments described above
49 with RIE (Reactive Ion Etch).
ing) CFFourGas and OTwoPattani with gas
To run. Then, the normal thin film transistor manufacturing process and
Similarly, a TEOS (tetra-oxide) is formed by a plasma CVD method.
Ethoxysilane) gas and OThreeSiO using gasTwoFrom
A gate insulating film 10 is formed. Sputtering on it
WSi by theTwo/ Deposition of polycrystalline Si, RIE method
More CFFourGas and OTwoPatterning using gas
The electrode 11 is formed. Next, in the source / drain region
P (phosphorus) or B (boron) by ion doping
Perform injection. Then, TEOS is formed by plasma CVD.
Gas and OThreeSiO using gasTwoThe insulating film 12 made of
RIE methodFourGas and OTwoInsulation using gas
Etching of film 12 to form contact holes
You. An Al film is formed thereon by sputtering.
And BCl by RIEThreeGas and ClTwoGas using gas
The wiring 13 is formed by turning. Next, plasma C
SiH by VD method FourGas and NHThreeGas and NTwoUsing gas
To form a protective film 14 made of SiN,
By CFFourGas and CHFThreeOne of the protective films 14 is formed using gas.
Etch the part and open the window. As described above,
Manufacture semiconductor devices with resistors, resistors, capacitors, etc.
can do.
【0057】さらに、比較例で示した掘り込み部の断面
形状において側面と底面の交差部に角部を持つ場合の結
晶性Si膜を用いて同様に半導体装置を作製し、本実施
形態の薄膜トランジスタと特性を比較したところ、本実
施形態により得られた薄膜トランジスタの方がキャリア
移動度が大きく、閾値電圧が小さかった。また、キャリ
ア移動度や閾値電圧等の特性のバラツキも、本実施形態
の方が小さく、特性の向上を図ることができた。Further, a semiconductor device was manufactured in the same manner using a crystalline Si film having a corner portion at the intersection of the side surface and the bottom surface in the cross-sectional shape of the dug portion shown in the comparative example. When the characteristics were compared, the thin film transistor obtained by this embodiment had higher carrier mobility and lower threshold voltage. In addition, variations in characteristics such as carrier mobility and threshold voltage are smaller in the present embodiment, and the characteristics can be improved.
【0058】なお、上記実施形態では非単結晶絶縁基板
としてガラス基板を用いたが、石英基板を用いても良
い。また、ガラス基板や石英基板、Si基板等の基板上
にSiO2膜やSiN膜等の非単結晶絶縁膜を形成した
ものを用いてもよい。さらに、非単結晶絶縁膜の下地基
板に掘り込み部を形成した後、非単結晶絶縁膜をその上
に形成するか、非単結晶絶縁膜を厚く形成して、非単結
晶絶縁膜自身に掘り込み部を形成することも可能であ
る。Although a glass substrate is used as the non-single-crystal insulating substrate in the above embodiment, a quartz substrate may be used. Further, a substrate in which a non-single-crystal insulating film such as a SiO 2 film or a SiN film is formed over a substrate such as a glass substrate, a quartz substrate, or a Si substrate may be used. Furthermore, after forming a dug portion on the base substrate of the non-single-crystal insulating film, a non-single-crystal insulating film is formed thereon, or a thick non-single-crystal insulating film is formed on the non-single-crystal insulating film itself. It is also possible to form a dug portion.
【0059】半導体膜としてはSi膜を用いたが、Si
Ge膜やGaAs膜、InP膜等の半導体膜を用いても
良い。Although a Si film was used as the semiconductor film,
A semiconductor film such as a Ge film, a GaAs film, and an InP film may be used.
【0060】半導体膜の結晶化を容易にするためにNi
を1nm蒸着したが、0.1nm〜100nm相当であ
ればよい。また、Niをスパッタリング法により蒸着し
て導入したが、真空蒸着等の他の蒸着法を用いてもよ
く、また、Niやその化合物(例えば酢酸ニッケル)を
含む溶液を塗布したり、イオン注入やCVD法等により
導入してもよい。半導体膜の結晶化を容易にする物質と
しては、Fe、Co、Ni、Cu、Ge、Pd、Auお
よびこれらの金属を含む化合物のうちの少なくとも一種
類を導入すればよい。To facilitate crystallization of the semiconductor film, Ni
Was deposited to a thickness of 1 nm, but may be 0.1 nm to 100 nm. In addition, although Ni is vapor-deposited and introduced by a sputtering method, another vapor-deposition method such as vacuum vapor-deposition may be used, and a solution containing Ni or a compound thereof (for example, nickel acetate) may be applied or ion-implanted. It may be introduced by a CVD method or the like. As a substance that facilitates crystallization of the semiconductor film, at least one of Fe, Co, Ni, Cu, Ge, Pd, Au, and a compound containing these metals may be introduced.
【0061】実施形態1および実施形態3では、エネル
ギーを加える部分を移動させるためにライン状ヒーター
を用いたが、ライン状に整形した光、ライン状に整形し
た荷電粒子、点状光をライン状に高速スキャンさせたも
の、点状荷電粒子ビームをライン状に高速スキャンさせ
たもの等のエネルギーを用いてもよい。In the first and third embodiments, the linear heater is used to move the portion to which energy is applied. However, the linear shaped light, the charged particles shaped into the linear shape, and the point light are converted into the linear shape. Energy may be used such as that obtained by scanning at a high speed or that obtained by scanning a point-like charged particle beam at a high speed in a line.
【0062】実施形態2および実施形態4では、半導体
膜の結晶化を容易にする物質をくびれ部の入り口側に導
入して均一加熱を行ったが、実施形態1および実施形態
3と同様に、部分的に加熱を行い、その加熱部を半導体
膜の結晶化を容易にする物質を導入した側からくびれ部
の反対側まで移動させてもよい。また、図2および図4
には、くびれ部の片側において大半の非晶質Si膜を露
出させた形状を示したが、図5(a)および図5(b)
に示すように、非晶質Si膜の一部のみを露出させても
よい。In the second and fourth embodiments, the material for facilitating crystallization of the semiconductor film is introduced into the constricted portion at the entrance side to perform uniform heating. However, as in the first and third embodiments, Heating may be performed partially, and the heated portion may be moved from the side where the substance that facilitates crystallization of the semiconductor film is introduced to the side opposite to the constricted portion. 2 and FIG.
5A and 5B show a shape in which most of the amorphous Si film is exposed on one side of the constricted portion.
As shown in (1), only a part of the amorphous Si film may be exposed.
【0063】[0063]
【発明の効果】以上詳述したように、本発明による場合
には、非単結晶絶縁膜または非単結晶基板上に形成した
非晶質または多結晶等の非単結晶半導体膜に熱や光、荷
電粒子等のエネルギーを加えることにより結晶成長させ
るに際して、核形成部で不規則に発生した多数の結晶核
のうち、材料および構造に特有の結晶成長しやすい方位
を有する結晶をくびれ部で選択することができる。さら
に、結晶粒を大きく成長させたい領域で不規則な核発生
が起こるのを、堀り込み部を側面と底面とが滑らかに連
続する断面形状にすることにより抑制することができ
る。よって、大略結晶方位の揃った大きな結晶粒または
大略結晶方位が揃った大面積の結晶性半導体膜を形成す
ることができる。このように結晶性が改善された半導体
膜を用いることにより、半導体装置の高性能化を図るこ
とができる。As described above in detail, in the case of the present invention, heat or light is applied to a non-single-crystal semiconductor film such as an amorphous or polycrystalline film formed on a non-single-crystal insulating film or a non-single-crystal substrate. From the many crystal nuclei generated irregularly in the nucleation part during the crystal growth by applying the energy of charged particles, etc., select the crystal having the orientation easy to grow crystal peculiar to the material and structure in the constriction part can do. Further, occurrence of irregular nucleation in a region where crystal grains are to be grown large can be suppressed by forming the dug portion into a cross-sectional shape in which the side surface and the bottom surface are smoothly continuous. Thus, a large crystal grain having a substantially uniform crystal orientation or a large-area crystalline semiconductor film having a substantially uniform crystal orientation can be formed. By using a semiconductor film with improved crystallinity, the performance of a semiconductor device can be improved.
【図1】実施形態1の半導体膜の形成方法について説明
するための図であり、(a)〜(c)は斜視図、(d)
は断面図である。FIGS. 1A to 1C are views for explaining a method of forming a semiconductor film according to a first embodiment, where FIGS. 1A to 1C are perspective views and FIG.
Is a sectional view.
【図2】実施形態2の半導体膜の形成方法について説明
するための図であり、(a)は斜視図、(b)は断面図
である。FIGS. 2A and 2B are views for explaining a method of forming a semiconductor film according to a second embodiment, wherein FIG. 2A is a perspective view and FIG.
【図3】(a)〜(c)は実施形態3の半導体膜の形成
方法について説明するための斜視図である。FIGS. 3A to 3C are perspective views illustrating a method for forming a semiconductor film according to a third embodiment.
【図4】実施形態4の半導体膜の形成方法について説明
するための斜視図である。FIG. 4 is a perspective view illustrating a method for forming a semiconductor film according to a fourth embodiment.
【図5】(a)および(b)は本発明における半導体膜
の結晶化を容易にする物質を導入する領域の他の形状の
例を示す斜視図である。FIGS. 5A and 5B are perspective views showing examples of other shapes of a region into which a substance for facilitating crystallization of a semiconductor film in the present invention is introduced.
【図6】実施形態5の半導体装置の製造方法について説
明するための断面図である。FIG. 6 is a cross-sectional view for describing the method for manufacturing the semiconductor device of the fifth embodiment.
【図7】従来例1の半導体膜の形成方法について説明す
るための平面図である。FIG. 7 is a plan view for describing a method of forming a semiconductor film of Conventional Example 1.
【図8】従来例2の半導体膜の形成方法について説明す
るための斜視図である。FIG. 8 is a perspective view for describing a method of forming a semiconductor film of Conventional Example 2.
【図9】従来例3の半導体膜の形成方法について説明す
るための平面図である。FIG. 9 is a plan view for describing a method of forming a semiconductor film of Conventional Example 3.
【図10】(a)および(b)は従来例4の半導体膜の
形成方法について説明するための断面図である。FIGS. 10A and 10B are cross-sectional views illustrating a method for forming a semiconductor film of Conventional Example 4. FIGS.
【図11】本発明におけるくびれ部の幅(W)および長
さ(L)の定義を説明するための斜視図である。FIG. 11 is a perspective view for explaining definitions of a width (W) and a length (L) of a constricted portion in the present invention.
【図12】比較例において、側面と底面の交差部が角を
持つことによる不規則な角発生を示す図であり、(a)
は断面図、(b)は上面図である。12A and 12B are diagrams showing irregular corner generation due to a corner at a crossing portion between a side surface and a bottom surface in a comparative example, and FIG.
Is a sectional view, and (b) is a top view.
1 ガラス基板 2、15 くびれ部 3、3a 掘り込み部 4、22 非晶質Si膜 5、21 SiO2膜 6 ライン状ヒーター 7 非晶質Si膜の露出部 8 均一加熱 9 絶縁性基板 10 Si膜 11 狭小領域 12、20 基板 13、16 多結晶Si膜 14 結晶方位のフィルター部 17 多結晶Si膜の除去部 18 細い部分 19 結晶成長方向 23 触媒材料からなる膜 24 掘り込み部の側面と底面の交差部の角 40 ゲート絶縁膜 41 ゲート電極 42 絶縁膜 43 配線 44 保護膜 49 結晶性Si薄膜 V ライン状ヒーターの移動方向 W くびれ部の幅 L くびれ部の長さ A、B 掘り込み部の断面を切った線REFERENCE SIGNS LIST 1 glass substrate 2, 15 constricted portion 3, 3a dug portion 4, 22 amorphous Si film 5, 21 SiO 2 film 6 linear heater 7 exposed portion of amorphous Si film 8 uniform heating 9 insulating substrate 10 Si Film 11 Narrow area 12, 20 Substrate 13, 16 Polycrystalline Si film 14 Filter part of crystal orientation 17 Removal part of polycrystalline Si film 18 Thin part 19 Crystal growth direction 23 Film made of catalytic material 24 Side and bottom of dug part At the intersection of 40 gate insulating film 41 gate electrode 42 insulating film 43 wiring 44 protective film 49 crystalline Si thin film V moving direction of linear heater W width of constricted portion L length of constricted portion A, B of dug portion Cross section line
Claims (8)
たは非単結晶絶縁基板上に半導体膜を形成する方法であ
って、 該非単結晶絶縁膜または該非単結晶絶縁基板に、側面と
底面とが滑らかに連続する断面形状であって、かつ、く
びれ部を有する掘り込み部を形成する工程と、 該非単結晶絶縁膜上または該非単結晶絶縁基板上に非単
結晶半導体膜を形成して、該掘り込み部を埋め込む工程
と、 該非単結晶半導体膜にエネルギーを加えることにより、
該くびれ部の一方側から反対側に該くびれ部を通過して
結晶成長を進ませる工程とを含む半導体膜の形成方法。1. A method for forming a semiconductor film on a non-single-crystal insulating film formed on a substrate or on a non-single-crystal insulating substrate, comprising: A step of forming a dug portion having a cross section that is smoothly continuous with the bottom surface and having a constricted portion; and forming a non-single-crystal semiconductor film on the non-single-crystal insulating film or on the non-single-crystal insulating substrate. Burying the dug portion, and applying energy to the non-single-crystal semiconductor film,
Passing the constricted portion from one side to the opposite side of the constricted portion to promote crystal growth.
用いて形成する請求項1に記載の半導体膜の形成方法。2. The method according to claim 1, wherein the non-single-crystal semiconductor film is formed using a silicon material.
で一方側にFe、Co、Ni、Cu、Ge、Pd、Au
およびこれらの金属を含む化合物のうちの少なくとも一
種類を導入する請求項1または請求項2に記載の半導体
膜の形成方法。3. One side of the non-single-crystal semiconductor film with a constricted portion therebetween being Fe, Co, Ni, Cu, Ge, Pd, Au.
The method for forming a semiconductor film according to claim 1, wherein at least one kind of a compound containing these metals is introduced.
上10μm以下に形成する請求項1乃至請求項3のいず
れかに記載の半導体膜の形成方法。4. The method for forming a semiconductor film according to claim 1, wherein the width of the upper surface of the constricted portion is formed to be 0.2 μm or more and 10 μm or less.
以上100μm以下に形成する請求項1乃至請求項4の
いずれかに記載の半導体膜の形成方法。5. The length of the upper surface of the constricted part is 0.5 μm.
The method for forming a semiconductor film according to claim 1, wherein the semiconductor film is formed to have a thickness of at least 100 μm.
ーを加える部分を、前記くびれ部の片側から反対側に移
動させる請求項1乃至請求項5のいずれかに記載の半導
体膜の形成方法。6. The method for forming a semiconductor film according to claim 1, wherein a portion for applying energy to the non-single-crystal semiconductor film is moved from one side of the constricted portion to the opposite side.
ーを略均一に加える請求項3乃至請求項5のいずれかに
記載の半導体膜の形成方法。7. The method for forming a semiconductor film according to claim 3, wherein energy is substantially uniformly applied to the non-single-crystal semiconductor film.
の半導体膜の形成方法により得られる半導体膜を用いた
半導体装置。8. A semiconductor device using a semiconductor film obtained by the method for forming a semiconductor film according to claim 1.
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JP36194699A JP2001176796A (en) | 1999-12-20 | 1999-12-20 | Forming method of semiconductor film, and semiconductor device |
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JP36194699A JP2001176796A (en) | 1999-12-20 | 1999-12-20 | Forming method of semiconductor film, and semiconductor device |
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Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2003059831A (en) * | 2001-08-17 | 2003-02-28 | Semiconductor Energy Lab Co Ltd | Method for manufacturing semiconductor device |
JP2003178979A (en) * | 2001-08-30 | 2003-06-27 | Semiconductor Energy Lab Co Ltd | Method for manufacturing semiconductor device |
US7422987B2 (en) | 2001-08-30 | 2008-09-09 | Semiconductor Energy Laboratory Co., Ltd. | Method for manufacturing semiconductor device |
-
1999
- 1999-12-20 JP JP36194699A patent/JP2001176796A/en not_active Withdrawn
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2003059831A (en) * | 2001-08-17 | 2003-02-28 | Semiconductor Energy Lab Co Ltd | Method for manufacturing semiconductor device |
JP2003178979A (en) * | 2001-08-30 | 2003-06-27 | Semiconductor Energy Lab Co Ltd | Method for manufacturing semiconductor device |
US7422987B2 (en) | 2001-08-30 | 2008-09-09 | Semiconductor Energy Laboratory Co., Ltd. | Method for manufacturing semiconductor device |
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