JPH0433156A - Electronic equipment - Google Patents

Abstract

PURPOSE:To prevent the malfunction of a sub-processor by permitting a main processor th detect the abnormality of a main mechanism, to write an error status in a shared memory and to generate interruption in the sub-processor. CONSTITUTION:When a system error such as write abnormality and read abnormality as against RAM 14 occurs in the middle of the execution of a normal processing, main CPU 11 writes the error status in common RAM 22 through an extension slot 18. Then an interruption signal is generated in sub-CPU 21 through an interruption generation circuit 17. When CPU 21 receives interruption from CPU 11, it reads the content of a main status area in RAM 22, and stops a function as a sub-unit 2 when the error status of a main unit 1 is read. Thus, the malfunction of the sub-processor can be prevented.

Description

Detailed Description of the Invention [Field of Industrial Application] The present invention connects a main device having a main processor and a sub device having a sub-processor, and transfers data between the two processors using a shared memory. Regarding electronic equipment.

[Prior Art] Generally, when adding additional functions such as online transmission to an electronic device such as a personal computer or an electronic cash register, a main processor having a main processor that constitutes the control unit of the electronic device is generally used. The system is expanded by connecting a sub-device having a communication sub-processor to the device. In this system, a shared memory that can be accessed by both processors is used for data exchange between the main processor and the sub-processor.

By the way, when an error such as an abnormality in writing or reading into the memory occurs, the main processor stops its function as a processor by detecting its own error. On the other hand, the sub-processor also stops functioning as a processor by detecting its own error. Therefore, if an abnormality occurs in a sub-equipment and the sub-processor stops its function, even if the main processor sends a command to the sub-equipment, there is no response from the sub-equipment, so the main processor uses timer monitoring to send a command to the sub-equipment. You can learn about equipment abnormalities. However, since the sub-device is not normally provided with a timer monitoring function, the sub-processor does not detect an abnormality in the main device and perform predetermined error processing. In particular, sub-devices with communication functions may malfunction due to access from other devices connected to the line, even if the corresponding main device has stopped functioning due to an abnormality. When considering a system in which the electronic device is brought online with a higher-end model via a line, there are problems such as a delay in detecting a down electronic device.

[Problems to be Solved by the Invention] Conventionally, even if the main processor stops functioning due to an abnormality in the main device, it is difficult to notify the sub-processor, and there is a risk that the sub-processor may malfunction. there were.

SUMMARY OF THE INVENTION Therefore, the present invention aims to provide an electronic device that can notify the sub-processor in real time when the main processor has stopped its function due to an abnormality in the main device, thereby preventing the sub-processor from malfunctioning. be.

[Means for Solving the Problems] The present invention provides an electronic device that connects a main device having a main processor and a sub device having a sub-processor and transfers data between the two processors using a shared memory. When the processor detects an abnormality in the main device, the processor writes an error status to the shared memory and generates an interrupt to the subprocessor.The subprocessor writes the error status to the shared memory in response to the interrupt from the main processor. The apparatus is provided with a status reading means for reading the status read by the means, and an error processing means for determining an error in the main device and performing predetermined error processing when the status read by this means is an error status.

[Operation] By taking such measures, when an abnormality occurs in the main device and is detected by the main processor, an error status is written to the shared memory and an interrupt is generated to the sub-processor. On the other hand, the subprocessor reads the status written to the shared memory in response to an interrupt.

If the error status is read at this time, it is determined that an error has occurred in the main device, and error processing such as stopping the sub-function is performed.

[Example] Hereinafter, an example of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of an electronic device in which a sub-device 2 having a communication control function is connected to a main device 1 such as a personal computer or an electronic cash register. The main device 1 has a pass line 12 connected to a main processor (hereinafter referred to as main CPU) 11 constituting the main body of the control unit.
Through [7] ROM 13, RAM 14, timer 15, interface 16, interrupt generation circuit 17, expansion slot 18
etc. are connected.

The interface 16 has a display 19.
Peripheral devices such as a keyboard 20 are connected. Further, the interrupt generating circuit 17 generates an interrupt signal to the processor (hereinafter referred to as sub CPU) 21 in the sub processor of the sub device 2 according to instructions from the main CPU II. The expansion slot 18 controls writing and reading of data in a shared memory (hereinafter referred to as common RAM) 22 provided in the sub-device 2 .

On the other hand, the sub device 2 has the sub CPU 21 for communication,
It is constructed by connecting a ROM 24, a RAM 25, the common RAM 22, a communication controller 26, an interrupt generation circuit 27, etc. via a path line 23.

The interrupt generation circuit 27 generates an interrupt signal to the main CPU II of the main device 1 according to instructions from the sub CPU 21.

As shown in FIG. 2, the common RAM 22 has a main status area A1 into which a predetermined status is written by the main CPU 1, a sub-status area A2 into which a predetermined status is written by the sub CPU 21, and another data area A3. It consists of This common RAM 22 is connected to the main CPU
Both the CPUs I and sub CPU 21 can be accessed, and the main CPU II and sub CPU 21 are connected to the common R
Data is exchanged using AM22.

The main CPU 11 is controlled by the program in the ROM 1B to execute the processing shown in FIG. That is, when it does not detect its own error and there is no interruption from the sub CPU 21, it executes normal processing as the main device 1.

During the execution of this normal processing, if a system error such as a write abnormality or a read abnormality to the RAM 14 occurs and is detected, the common RAM is
The error status is written in the main status area A1 of 22. Also, the contents of the sub-status area A2 of the common RAM 22 are read. If the error status of sub-equipment 2 is not set, interrupt generation circuit 1
7, an interrupt signal is generated to the sub CPU 21. (Error notification means) After that, the function as the main CPU 11 is stopped.

Note that if the error status of sub device 2 is set in the above sub status area A2, the sub CPU
Main CPU II without interrupting 21
stop functioning as

On the other hand, when an interrupt is received from the sub CPU 21 during execution of normal processing, the contents of the sub status area A2 of the common RAM 22 are read and processing according to the status is executed. Here, when the error status of the sub-device 2 is read, an abnormality has occurred in the sub-device 2, so error handling is performed, such as displaying a message on the display 19 to the effect that the sub-device 2 is abnormal.

Further, the sub CPU 21 is controlled by a program in the ROM 24 to execute the processing shown in FIG. In other words, it does not detect its own errors,
Further, if there is no interrupt from the main CPU II, normal processing as the sub device 2 is executed.

During execution of this normal processing, when a system error such as a write abnormality or a read abnormality to the RAM 25 occurs and is detected, the error status is written in the sub-status area A2 of the common RAM 22. Also, the above common R
Read the contents of main status area A1 of AM22. If the error status of the main device is not set, the main CPU
11 to generate an interrupt signal.

Thereafter, the function as the sub CPU 21 is stopped. Note that if the error status of main device 1 is set in the main status area A1, the main C
Sub CPU 21 without interrupting PUII
stop functioning as

On the other hand, when an interrupt is received from the main CPU 1 during execution of normal processing, the contents of the main status area A1 of the common RAM 22 are read and processing according to the status is executed (status reading means). Here, when the error status of the main device 1 is read, an abnormality has occurred in the main device 1, so the function as the sub device 2 is stopped (error processing means).

In this embodiment configured in this way, when an abnormality in data writing to the RAM 14 occurs in the main device 1 and the main CPU 1 detects it, a predetermined error status is written in the main status area A1 of the common RAM 22. At the same time, an interrupt is issued to the sub CPU 21. And main CPUI 1
stops its function.

On the other hand, the sub CPU 21 reads the contents of the main status area A1 of the common RAM 22 in response to an interrupt from the main CPU 1. At this time, since the error status of the main device 1 is written in the main status area A1, the sub CPU 21 can know that an abnormality has occurred in the main device 1. This allows sub-C
PU21 stops its function.

Therefore, if an abnormality occurs in the main device 1, it is notified to the sub CPU 21 in real time, and the sub CPU 21 is notified of the abnormality in real time.
Since the function of 21 is stopped, there is no problem such as the sub-device 2 malfunctioning due to external access when the main device 1 is abnormal. This means that when the electronic device of this embodiment is considered as a system that is connected to a host model online via a line, abnormalities in the electronic device can be promptly notified to the host model. Also, sub equipment 2
There is also the advantage that no abnormal data is output to the line, and the line can be used more effectively.

Also, if an abnormality occurs in sub device 2, it will be transferred to sub CP.
The same applies when U21 detects the error, and a predetermined error status is written in the sub-status area A2 of the common RAM 22, and an interrupt is issued to the main CPU II. As a result, the main CPU 11 reads the contents of the sub-status area A2 of the common RAM 22, and by reading the error status, the sub-equipment 2
It is determined that an abnormality has occurred. Therefore, compared to the conventional case in which an abnormality in the sub-device 2 is determined by detecting no response to a command by timer monitoring, an abnormality in the sub-device 2 can be detected more quickly.

Note that the present invention is not limited to the above embodiments.

For example, in the embodiment described above, the common RAM 22 is applied to a system in which the sub-device 2 is provided, but it can also be applied to a system in which the common RAM 22 is provided in the main device 1. Moreover, the sub-device 2 in the present invention
is not limited to communication equipment, but can be applied to various types of intelligent equipment. It goes without saying that various other modifications can be made without departing from the gist of the present invention.

[Effects of the Invention] As detailed above, according to the present invention, when the main processor stops its function due to an abnormality in the main device, it is possible to notify the sub-processor in real time, and the sub-processor It is possible to provide electronic devices that can prevent malfunctions.

[Brief explanation of the drawing]

The figures are diagrams showing one embodiment of the present invention, in which Fig. 1 is a block diagram showing the overall configuration of an electronic device, Fig. 2 is a diagram showing a memory format of a shared memory, and Fig. 3 is a diagram related to the present invention. FIG. 4 is a flowchart showing the operation of the main processor, and FIG. 4 is a flowchart showing the operation of the subprocessor related to the present invention. 1... Main device, 2... Sub device, 11... Main processor (main CPU), 21... Sub processor. Tsusa (sub CPU), 22...shared memory (common RAM). Figure 3

Claims (1)

[Scope of Claims] An electronic device that connects a main device having a main processor and a sub device having a sub-processor and transmits data between the two processors using a shared memory, wherein the main processor is connected to the main device. error notification means for writing an error status to the shared memory and generating an interrupt to the sub-processor when an abnormality is detected, the sub-processor writing to the shared memory in response to the interrupt from the main processor; and an error processing means for determining an error in the main device and performing predetermined error processing when the status read by the means is an error status. Electronics.