JPH03171332A - Abnormal access detecting system - Google Patents

Abstract

PURPOSE:To prevent the abnormal accesses and at the same time to inform an external device of the abnormal access to assure a normal operation for improvement of reliability by a system by providing a circuit which inhibits the access to an internal circuit of a device and a circuit which detects externally the access given to the internal circuit. CONSTITUTION:A 1st device 10 has a direct access to an internal circuit of a 2nd device 20 to perform the communication with the device 20. That is, an access detecting means 1 detects an access given to the internal circuit of the device 20 from the device 10. A setting means 2 sets the inhibition of the access given to the device 20 from the device 10. Then an abnormality detecting means 3 detects the abnormality based on the set state of the means 2 when an access given to the internal circuit of the device 20 from the device 10 is detected by the means 1. In such a constitution, the abnormal accesses is prevented and informed to an external device.

Description

[Detailed Description of the Invention] [Summary] Regarding the detection of abnormal access from an external device, the object of the present invention is to provide a method for detecting abnormal access in order to prevent and notify abnormal access from an external device, A system in which a device communicates with a second device by directly accessing an internal circuit of the second device, wherein the second device includes access detection means for detecting access to the internal circuit; It is advisable to provide a means for setting prohibition of access to the circuit, and an abnormality detecting means for detecting an abnormality based on the setting of the setting means when access to the internal circuit is detected by the detecting means.

[Industrial application field]

The present invention relates to detection of abnormal access from an external device.

In recent years, microprocessors are being used in all fields as semiconductor products become cheaper due to advances in semiconductor technology. For example, in communication between two devices with microprocessors, one device typically communicates with the other device directly via a public bus within the other device. /Set the command to register t-L to start operation (-, also memory etc. (,
It is planned to read and write this data and send data fj. In such a structure, if the register or memory is accessed illegally while the device is in operation, 2
The operation of the device will be disturbed, leading to malfunctions. Therefore, a system that can detect n-fold accesses is desired.

[Conventional technology]

It is a bookmark diagram that does not show the fourth ILLu example. The same symbols indicate the same objects throughout the figures.

The host device 10 executes a program using a central processor 11 (called CPU) 11, outputs data from an output device 21 (called IO) 21, and outputs it to +021. At the same time, data processing is performed. The human output controller i (referred to as IOC) 20A is a human output controller.
The control memory (referred to as IOP) 5a is
The control program stored in the CS (CS) 6 and { is executed to control the output of data between the host 1 and the FIOA 1021. The host 1/device 10A and the IOc 20A interconnect the common busses of their respective processors, and input the addresses of the respective processors into registers (not shown) and data buffers (referred to as DB) 8a in the control unit 7. connected by assigning a common address in space. For example, Hoss I? ? In the write operation of outputting data from 10A to 1021, host storage 10A specifies the address of DB8a, transfers and stores the output data, and specifies the command 1/register (not shown) of control unit 7a to write the data. Seven commands are given. The control unit 7a is an interface circuit (referred to as NFC)
The IO21 is activated via 9a and the data in DBBa is output to 1021, thereby executing the write operation.

[Problem to be solved by the invention 1 According to the conventional method as described above, rOc20A and boss]
・Communication with the device 10A is carried out via a common bus (7) by directly accessing commonly accessible registers and buffers, so if the host device 10A is in operation and the command register of 10C2OA is etc. and change the contents, 10C2O
A had a problem in that the operation sequence was disrupted and malfunction 11 did not occur.

An eleventh object of the present invention is to provide a system for detecting abnormal access in order to prevent abnormal access from a client device, and to notify the abnormal access.

(Means for solving problems) FIG. 1 shows a block diagram of the principle of the present invention.

In between, 10 is a first device, 20 is a second device, 1 is access detection means for detecting access from the first device 10 to the internal circuit of the second device 20, and 2 is the first device 10. means for setting prohibition of access from the first device 10 to the internal circuit of the second device 20; This is a 1,000-stage abnormality detection system that detects abnormalities based on the settings of stage 2.

[Function] According to the present invention, the first equipment 10 directly accesses the internal same path of the second device 20, so that the second device 2
In systems that communicate with 0, access detection is 1,000 steps.
detects the access from the first device 10 to the internal circuit of the second device 20, and the setting step 2 detects the access from the first device 10 to the internal circuit of the second device 20.
setting prohibition of access to the internal same path of the device 20;
The abnormality detection stage 3 detects an abnormality based on the setting of the setting stage 2 when the access from the first device 10 to the internal circuit of the second device 20 is detected by the detection stage 1.
It becomes possible to prevent and notify abnormal access.

[Example] Hereinafter, an example of the present invention will be described with reference to FIGS. 2 and 3. The same reference numerals indicate the same objects throughout the figures.

Components in FIG. 2 that correspond to those in FIG. 1 are surrounded by dashed lines.

In Fig. 2, 1 0 C20B, IO P5b, C S6
b, D B8b, control unit 7b, and lFc9b are IOC20810 P5a, C S6a explained in the conventional example.
, D B8a, control unit 7a. ．． It has the same functions as IFC98.

The decoder 1b decodes a common path address signal from a host device (not shown) and detects that an address assigned to an internal circuit of the IOC 20B, such as a command register (not shown) or DB 8b, is specified.

Flip-flop (referred to as FF) 2b is IOC20B
It is set by the control program 3c when it is necessary to prohibit access from the host device to the internal circuits of the IOC 20B, such as when the IOC 20B is in operation.

The operation of this embodiment will be explained with reference to the timing diagram of FIG.

(2) The control program 3c sets the FF 2b when it is necessary to prohibit access from the host device to the internal circuit.

(2) An address signal and a write or read timing signal of 10W or IOR are output from the common bus of the host device.

(2) When the decoder 1b detects that the address signal specifies the internal circuit of the IOC 20B, it outputs an RS signal.

■At the timing of IOW or IOR (OR circuit 4b),
When the decoder 1b outputs the RS signal and the FF 2b is set (NAND circuit 3a), the SINT signal is turned on.

(2) Suppresses access from the host device to the internal circuit by the SINT signal, sets FF3b and outputs an interrupt request (*INT) to the host device to notify abnormal access.

〔Effect of the invention〕

As explained above, according to the present invention, in a system in which two devices communicate with each other by directly accessing the internal circuits of the other device, a circuit for prohibiting access to the internal circuits of the devices and an external The system is equipped with a circuit that detects access to internal circuits to detect abnormal access, which prevents abnormal access that disrupts the operation sequence between devices, and also notifies external devices to ensure normal operation. This has the effect of improving reliability.

[Brief Description of the Drawings] Fig. 1 is a principle block diagram of the present invention, Fig. 2 is a block diagram showing an embodiment of the present invention, Fig. 3 is a timing diagram of the embodiment of the present invention, and Fig. 4 is a conventional block diagram. FIG. 2 is a block diagram illustrating an example. In the figure, l is an access detection means, 1b is a decoder, 2 is a setting means, 2b is a flip-flop (FF), 3 is an abnormality detection means, 3a is a NAND circuit, 3b is a flip-flop (FF), 3c is a control program, 4b is an OR circuit, 5b is a human output processor (■○P), 6b is a control memory (CS), 7b is a control unit, 8b is a data buffer (DB), 9b is an interface circuit (IFC), 10 is a first device , 20 is a second device, 20B is an input/output control device (■○C), and 2l is a human output device (■○). Principle brochure diagram of non-explosion B month Ubu≦Ei ``;A] Timing diagram of non-invention 0 implementation Ita 1j

Claims (1)

Claims: A system in which a first device (10) communicates with a second device (20) by directly accessing an internal circuit of the second device (20), comprising: 20), access detection means (1) for detecting access to the internal circuit; and means (2) for setting prohibition of access to the internal circuit;
and an abnormality detecting means (3) for detecting an abnormality based on the setting of the setting means (2) when the detecting means (1) detects an access to the internal circuit. Access detection method.