JPH0433071B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION "Field of Industrial Application" The present invention relates to an approximate function value generation circuit that generates an approximate value of a function f for a binary number Y.

``Prior Art'' Conventionally, this type of approximate function value generation circuit prepares a memory in which the approximate function value for a specified address is stored, addresses the memory with the value for which the function value is to be found, and writes the contents. The first method, which obtains approximate function values by reading, and the second method, which uses calculation hardware to obtain the function values by calculation, have been common.

Furthermore, the document of JP-A No. 57-204931 discloses a digital nonlinear converter that generates an arbitrary function of input data, and the document of JP-A-59-109975 discloses a digital nonlinear converter that generates an arbitrary function of input data. 2. Description of the Related Art A function generating device is disclosed that outputs a function value that changes periodically at predetermined intervals.

``Problems to be Solved by the Invention'' In the first method, as the number of digits of the numerical value for which the function value is to be determined increases, the number of required memory addresses increases exponentially. The disadvantage is that the required memory capacity also increases exponentially.

On the other hand, the latter second method has disadvantages in that it takes a long time to obtain the approximate function value, and the approximate function value generation sequence tends to be complicated.

Moreover, the above-mentioned basic problem can certainly be solved by the methods of "nonlinear converter" and "function generator" cited in the prior art. However, since these methods are approximations, there is always the problem of ensuring accuracy. By the way, in order to guarantee accuracy,
Naturally, it is easier to guarantee accuracy if the basic accuracy of the method is even slightly higher. In other words, due to the high basic precision of the system, the bit width of the memory and multiplier/adder can be narrow. Further, even if there is no need to guarantee that the actual value is within a set error range, high accuracy is desirable in itself. In all of the conventional techniques of nonlinear converters and function generators mentioned above, if the symbol of this invention is used as a basic method, f(Y)=f(y ₀ +y ₁ ) ≒f^(y ₀ )+f^( 1) (y ₀ )・y ₁ Note: Since the bit width of memory is finite, generally f(y ₀ ) and f(1)(y ₀ ) cannot be determined accurately, but with a finite bit width. f^(y ₀ ) + f^(1) close to the representable true value
(y ₀ ) (approximate value) will be substituted.

This is based on the approximation method shown in FIG. 3. This seems to be a common sense method at first glance, but there remains room for improvement in accuracy.The present invention regards this room as a problem that should be improved, and focuses on solving this problem to improve accuracy. It is something.

"Means for Solving Problems" According to this invention, a heavily weighted value y ₀ is obtained from a binary number Y.
The first part with the value y 1 and the second part with the light weight value y ₁ are taken out, and the memory is read out using the first part as an address. That memory has the above
Approximate value of the function f at the value y ₀ + ω _{0 /2, which is the sum of y 0 and 1/2} value ω ₀ /2 of the weight ω ₀ of the least significant bit of y 0
f^ (y ₀ + ω ₀ /2) and its first derivative approximate value f^(1) (
y ₀ +ω ₀ /2) are stored as first data and second data, respectively. By inverting the most significant bit of y ₁ from the value y ₁ of the second part read out, the calculation result of y ₁ −ω ₀ /2 is expressed as a signed binary number y ₁ ' in two's complement representation. generated by subtractive means,
This signed binary number y ₁ ′ and the read second data are multiplied together by a multiplier to calculate a correction value, and this correction value and the read first data are combined by an adder. are added and a correction calculation is performed,
An approximate function value for the function f of the binary number Y is output.

Generally, when finding the approximate value of a function g where the data X is X=x+Δx, g(X)1=g(x+Δx)≒g(x)+g(1)(x)
・
When performing approximate calculations in the form Δx, the smaller the absolute value of Δx, the higher the approximation accuracy.

According to the invention, f(Y)=f( _y0 + _y1 )=f[( _y0 + _ω0 /2)+( _y1 − _ω0 /2)]=f[( _y0 + _ω0 /2) )+y ₁ ′] ≒f^(y ₀ +ω ₀ /2)+f^ ₁ (1)(y ₀ +ω ₀ /2)・
y ₁ ′ Note: Since the bit width of memory is finite, generally f(y ₀ + ω ₀ /2) and f(1)(y ₀ + ω ₀ /2) cannot be determined accurately; Values f^ (y ₀ + ω ₀ /2) and f^(1) (y ₀ + ω ₀ /2) (approximate values), which are close to the true value and can be expressed in width, are substituted.

Approximate calculations are performed using the following functions, and this is cleverly applied to digital binary operations. That is, for example, when performing the following calculation, it is said that it is done by reversing the bits.

y ₁ ′=y ₁ −ω ₀ /2 Now, regarding the portion corresponding to Δx mentioned above, when comparing the method explained in “Prior art” with the method of the present invention, Δx=y ₁ … “Prior art Δx=y ₁ ′..."method of the present invention", and the range of possible values is |y ₁ |<ω ₀ for the former, while y ₁ ′=y ₁ −ω for the latter. From _0/2 , |y ₁ ′|≦ω ₀ /2, and it can be seen that the method according to the present invention is superior in accuracy. In other words, this method relies on an approximation method as shown in FIG. 4, which gives an image consistent with the fact that the accuracy is high. In the present invention, when calculating y ₁ ', how is it possible to perform subtraction by simply reversing the bits?
To briefly explain whether the result can be obtained as a signed binary number, the range of possible values of y ₁ is 0≦y ₁ <ω ₀ . Furthermore, if y ₁ is supplemented with 0 at the position of weight ω ₀ and considered as a sign, it can be regarded as a signed binary number expressed in two's complement. As shown in Figure 5, the position of the weight ω ₀ /2 in y ₁ is the position of the most significant bit, so the operation of subtracting ω ₀ /2 means subtracting 1 from the position of the most significant bit. Yes, in other words, it is a bit inversion operation. At this time, the range of possible values of y ₁ ', which is the result of subtraction, is -ω ₀ /2≦y ₁ '≦ω ₀ /2, and the result is the position of ω ₀ /2, that is, the position of the most significant bit. will represent the sign. Therefore, subtraction is possible by simple bit inversion, and the result can be obtained as a signed binary number.

"Example" Next, the present invention will be described with reference to the drawings. FIG. 1 shows an approximate function value generation circuit according to an embodiment of the present invention. The memory 10 inputs the first part of the binary value Y (value y ₀ with heavy weight) through the line 1, and accordingly inputs the first data among the read data onto the line 101. , and second data to the lines 102, respectively. The first data is the approximate value f^ of the function f at the value _{y 0 +} ω ₀ /2, which is the sum of y ₀ and the value ω ₀ /2, which is 1/2 of the weight ω ₀ of the least significant bit of y 0. (y ₀ +ω ₀ /2), and the second data is an approximate value f^(1) (y ₀ +ω 0 /2) of the differential coefficient _of the function f at y ₀ +ω ₀ /2. The subtractor 40 is connected to the second part (the less weighted value) of the numerical value Y supplied via line 2.
The most significant bit of y ₁ ) is inverted and the calculation result of y ₁ −ω ₀ /2 is output as a signed binary number y ₁ ' in two's complement representation to line 401. The adder 30 receives the binary number y ₁ ' of receiving the first data from the memory 10 and the correction value from the multiplier 20;
Correction is performed by adding the two, and the final result, which is the approximation function value of the numerical value Y, is output.

The operation of this embodiment will be explained below using an example.For ease of understanding, the function f is f:y-1/y as an approximate reciprocal generator, and the numerical value Y is a signed binary number and is negative by two's complement. It is assumed that the value is always normalized, and the memory ₁₀ has the function f
The approximate value of 1/(y ₀ + ω ₀ /2) is 12 bits, and the second data is the approximate value of -1/(y ₀ + ω ₀ /2) ² of the first derivative of the function f. A case will be explained in which the first part y ₀ of the numerical value Y is stored as 5 bits from the top (higher), and the second part y ₁ is stored as 6th to 9th bits.

In this case, the memory 10 is addressed by the value _y0 of the first five bits of the number Y, but if the number Y is normalized, the value of the sign bit is S.
Since the second bit is always required, the first bit does not actually need to be used for addressing, and the four bits starting from the second bit are used for addressing. This situation and the contents stored in the memory 10 are shown in FIG.

Here, initially the number Y is a signed binary number 0,
The operation of each part will be explained in order for the case of 10011010.... First, the second part that defines the first part y ₀ of the numerical value Y
~5th bit value 1001 is sent to memory 10 via line 1
The memory 10 receives the address and writes the signed binary values 001, 101011110, which are approximate values of the reciprocals of the binary values 0, 10011, to the line 101 as the initial approximate reciprocal (first data) of the numerical value Y. At the same time, the approximate value 101, 0010101 of the first-order differential coefficient at the binary value 0, 10011 of the function f:y→1/y is output as second data (signed binary value) to the line 102. . The subtractor 40 subtracts the value 0, which is the second part y ₁ of the number Y.
The value 1010 as the lower 4 bits of 00001010 is received via line 2, and the most significant bit 1 is inverted to 0, and the value 0010 as the lower 4 bits of the signed binary value 0,00000010 is output on line 401. Multiplier 20 receives this value 0010 via line 401, and also receives function f:y→
The approximate value (second data) of the first differential coefficient of 1/y at the binary value 0, 10011 (second data) 101, 0010101 is the line 10
2 and multiplying both to obtain a corrected value of the initial approximate reciprocal of the number Y. 111110100 is output on line 201 as a signed binary number. Finally, the adder 30 receives the initial approximate reciprocal (first data) 001, 101011110 of the numerical value Y via the line 101, and
A correction value of the initial approximate reciprocal of the numerical value Y.
111110100, add it with sign extension as necessary to obtain the approximate reciprocal of the desired value Y
001, 101010011 are output from line 301 as signed binary numbers.

Next, the operation of each part will be explained in order for the case where the numerical value Y is a signed binary number 1, 00100101, . . . . First, the value 0010 of the second to fifth bits defining the first part _y0 of the numerical value Y addresses the memory 10 via the line 1, and the memory 10 receives the binary value 1 on the line 101, Signed binary values 110 and 110100001, which are approximate values (first data) of the reciprocal of 00101, are output as the initial approximate reciprocal of Y, and the line 102 shows the function f:
An approximate value (second data) 110, 1001100 of the first-order differential coefficient in the binary value 1,00101 of y→1/y is output as a signed binary value. The subtracter 40 is a numerical value Y
The value 0101 is received on line 2 as the lower 4 bits of the value 0,00000101, which is the second part of y ₁ , and its most significant bit is inverted and the signed binary value 1,
Outputs the value 1101 as the lower 4 bits of 11111101. Multiplier 20 receives this value via line 401;
Also, the approximate value 110, 1001100 of the first-order differential coefficient of the function f: y → 1/y at the binary value 1, 00101 is expressed by the line 102.
By multiplying both values, a correction value of the initial approximation reciprocal of the numerical value Y is obtained. 0000010001 is output on line 201 as a signed binary number. Finally, the adder 30 outputs the initial approximate reciprocal of the number Y via the line 101.
110, 110100001, and a correction value of the initial approximation reciprocal of the numerical value Y via the line 201. Receive 0000010001,
Approximate inverse value 110, 110101010 of desired value Y is obtained by extending the sign as necessary and adding them together.
is output from line 301 as a signed binary number.

It goes without saying that the calculated bit length, decimal point position, etc. of each component output can be determined as appropriate depending on desired conditions.

``Effects of the Invention'' As explained above, the present invention provides a small-capacity memory means necessary for determining the initial approximation function value, a means for subtracting a small amount of metal objects, and a multiplication means and an addition method that are made more efficient thereby. The simple and small-scale circuit configuration of the means has the advantage of being able to calculate approximate function values quickly and efficiently with a small amount of hardware.

Furthermore, compared to other function value approximation mechanisms that use the same or similar formats to the present invention, the present invention has the advantage of being more efficient in terms of hardware and ensuring higher accuracy.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the approximation function value generation circuit of the present invention, FIG. 2 is a diagram showing the addresses and contents of the memory 10 in FIG. 1, and FIG. 3 is an approximation method according to the prior art. FIG. 4 is a diagram showing an approximation method according to the configuration of the present invention, and FIG. 5 is a diagram explaining the principle of the means for generating y ₁ ' defined in the present invention. 10...memory, 20...multiplier, 30...adder, 40...subtractor.

Claims (1)

[Claims] 1. Means for extracting a first part having a heavy weight value y ₀ and a second part having a light weight value y ₁ from a binary number Y, and inputting the first part as an address. By doing so, the weight of the least significant bit of y ₀ is given to y ₀ by ω ₀
The approximate value f^(y ₀ +ω ₀ /2) of the function f at the value y ₀ +ω ₀ /2, which is the sum of 1/2 of the value ω ₀ /2, and the approximate value f^(1 )(y ₀ +ω ₀ / ₂ ) as first data and _second data, respectively; a subtraction means for obtaining _the calculation result of ₁ −ω ₀ /2 as a signed binary number y ₁ ′ in two's complement representation; a multiplier that calculates and outputs a correction value by multiplying; and a multiplier that performs correction by inputting the first data and the correction value and adding them together to calculate an approximate function value of the function f for the binary number Y; 1. An approximate function value generation circuit comprising: addition means for outputting .