JPS61216025A - Generating circuit for approximate function value - Google Patents

Abstract

PURPOSE:To calculate an approximate function speedily with high efficiency by small hardware by providing a small-capacity memory, a subtracting means, a multiplying means which is increased in efficiency by it, and an adding means. CONSTITUTION:The 1st part with a heavy-weight value y0 and the 2nd part with a lightweight value y1 are extracted from a binary number Y and the 1st part is used as an address to read the memory 10. The memory 10 is stored with an approximate value of a function (f) at the value obtained by adding a value a half as large as the weight omega0 of the low-order bits of the value Y0 to the value y0 and an approximate value of its primary coefficient of differentiation as the 1st data and the 2nd data respectively. The most significant digit bit of the value Y1 of the 2nd read part to generate a new binary number y1' with a sign by the subtracter 40 and this number y1' and the 1st data are multiplied mutually by the multiplier 20 to calculate a correcting value; and the 1st data is added to this correcting value by the adder 30 to perform correction arithmetic, thereby outputting an approximate function value for the function (f) of the binary number Y.

Description

DETAILED DESCRIPTION OF THE INVENTION "Industrial Application Field" The present invention relates to an approximate function value generation circuit (:) that generates an approximate value of a function f for a binary number YC.

``Prior Art'' Conventionally, this type of approximation function value generation circuit prepares a memory in which the approximation function value for a designated address C: is stored, and specifies the address of the memory with the value for which the function value is to be obtained. The first method is to read out the contents (; the first method is to obtain an approximate function value, and the second method is to use calculation hardware to obtain the function value by calculating the function value. .

``Problems to be solved by the invention'' In the first method, the number of digits of the numerical value for which the function value is to be determined increases; However, along with this, the required memory capacity also increases exponentially.

On the other hand, the latter second method C2 has disadvantages in that it takes a long time to obtain the approximate function value, and the approximate function value generation sequence tends to be complicated.

"Means for Solving the Problem" According to the present invention, a first part having a heavily weighted value y0 and a second part having a lightly weighted value y1 are extracted from a binary number Y. The memory is read using the part as an address. In that memory, said y0t=that y. The weight of the least significant bit of ω. The value y is the sum of the negative value i. The approximate value of the function f (y0+"JL) and the approximate value of its first derivative coefficient yo+" are stored as the first data and the second data, respectively. .

A new signed binary number y is obtained from the read second part value y1 by inverting the most significant bit of yl.
: is generated by the subtraction means, and this signed binary number y: and the read second data are mutually (squared) by the multiplication means to calculate a correction value, and this correction value and the read second data are The first data is added by an adding means, a correction operation is performed, and an approximate function value for the function f c of the binary number Y is output.

"Example" Next (2) This invention C will be explained with reference to the drawings.

FIG. 1 shows an approximate function value generation circuit according to an embodiment of the present invention. Memory 0 inputs the first part of the binary number Y (value yo with heavy weight) through line 1, and inputs the first data among the read data accordingly to line 101 C1 second part Data is output to each line 102C. The first data is the approximate value of the differential coefficient of the function f in the value C2 of Σ of the weight ω0 of the least significant bit of the yo (11 (Yo 10)).The subtracter 40 is a numerical value The most significant bit of the second part of Y (value yt with light weight) is inverted and output as a new signed binary number y: on line 401 (-), and the multiplier 20 outputs the binary number from line 401. y;
, and also receives the second data from memory 0, and calculates the correction value of the numerical value Y by multiplying these by each other to obtain the line 20
1 (two outputs; the adder 30 receives the first data from the memory 10 and the correction value from the multiplier 20,
Correction is performed by adding the two, and the final result, which is the approximation function value of the numerical value Y, is output.

The operation of this embodiment will be explained below using an example. For ease of understanding, the function f is f:y-1 as an approximate reciprocal generator.
, the numerical value Y is a signed binary number that expresses a negative value using two's complement, and is always normalized, and memory 0 has the address Y, -2 as the first data. The approximate value of the function f, 1/(yo+-7iL), is 12 bits, and the second data is the approximate value of 7,1/(yo+V)2, the first derivative of the function f, is 10 bits. The first part y0 of the numerical value Y is stored as the 5 bits from the beginning (higher), and the second part y1 is stored as the 6th to 9th bits.
In the case of bits ≦ two, we will explain.

In this case, memory 0 is the value y of 5 pits from the beginning of the number Y.
. The address is specified by C2, but if the numerical value Y is normalized (2 is the value of the sign bit S, the second pit is always 100, so in reality (2 is the first As for the bits, it is not necessary to use address designation C2, and the address designation is performed using the 4 bits starting from the second bit.This situation and the stored contents of the memo I710 are shown in FIG. 2C2.

Here, the initial C value Y is a signed binary number 0, 10011
010... Order C: The operation of each part will be explained. First, the second to fifth parts specifying the first part y0 of the numerical value Y.
The pit value 1001 addresses memory 0 via line 1, which receives the binary value 0.100.
Signed binary value 001,101 which is an approximation of the reciprocal of 11
011110 is the initial approximate reciprocal of the numerical value Y (first data)
is output on the line 101 as
01.0010101 as second data (signed binary value)
is output on line 102 as . The subtracter 40 receives the value 1010 as the lower 4 pits of the value α, 00001010, which is the second part y1 of the numerical value Y, through the line 2, and inverts the most significant bit 1 and outputs it as O on the line 401 (2 signed 2). advance value o,
ooooo.

Outputs the value 0010 as the lower 4 bits of 10.

The multiplier 20 receives this value 0010 via the line 401 and also calculates the approximate value (second data) of the first differential coefficient of the function (:y-1-) at the binary value 0.10011c 101°001
0101 via the line 102 and multiplying both C: Correction value of the initial approximation reciprocal of the numerical value Y.

Line 201 C with 111110100 as a signed binary number
Output. Finally, the adder 30 passes through the line 101 the initial approximate reciprocal of the numerical value Y (first data) 001.1010111
10, receive the correction value of the initial approximate reciprocal of the numerical value Y through the X-ray 201, 111110100, and add it with sign extension as required (C: Approximate reciprocal of the desired numerical value Y 001.101010011 It is output from line 301 as a signed binary number.

Next (binary value Y is signed binary number 1.00100101...
In the case of (2), we will explain the operation of each part in turn. First, the value 0010 of the second to fifth bits that defines the first part y0 of the numerical value Y specifies memory 0 via line 1,
Memory 0 receives this and has a binary value of 1.001 on line 101.
The signed binary Ia110.110100001, which is the approximate value (first data) of the reciprocal of 01, is output as the initial approximate reciprocal of Y, and the line 102c2 is a function (: y=
1, an approximate value (second data) of the first differential coefficient of 1.00101 in binary value 110.1001100 is output as a signed binary value. The subtractor 40 is the second part y0 of the number Y, the value o, ooo.

It receives the value 0101 as the lower 4 bits of 0101 on line 2, inverts its most significant bit and outputs the value 1101 as the lower 4 bits of the signed binary value 1.11111101 on line 401. Multiplier 20 receives this value via line 401, and also receives the binary value 1.'001 of the function f: y-,-.
Approximate value of the first differential coefficient at 01 110.1001
100 via line 102 and multiplying them both (
; Correction value of the initial approximate reciprocal of the numerical value Y, 0000010
001 is output on line 201C as a signed binary number. The last≦2 adder 30 receives the initial approximate reciprocal of the numerical value Y via the line 101, 110.110100001, and receives the correction value of the initial approximate reciprocal of the numerical value Y, 0000010 via the X-ray 201.
001, apply sign extension as necessary (; and reciprocal (-)
Adding (approximate inverse value 110 of the desired value Y from 2)
．． 110101010 is output from line 301 as a signed binary number.

It goes without saying that the calculated bit length, decimal point position, etc. of each component output can be determined as appropriate depending on desired conditions.

``Effects of the Invention'' As explained above, the present invention provides a method for determining the initial approximation function value. The simple and small-scale circuit configuration of the addition means has the effect of being able to calculate the approximate function value with a small amount of metal, at high speed, and with high efficiency.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the approximate function value generation circuit of the present invention, and FIG. 2 is a diagram showing the addresses and contents of the memory 10 in FIG. 1. 10: memory, 20: multiplier, 30: adder, 40: subtracter. Patent applicant NEC Corporation Attorney Taku Kusano Procedural amendment (spontaneous) June 4, 1985 Director General of the Patent Office Li1, Indication of case Patent application 1986-574832, Title of invention Approximate function value generation Circuit 3, Person making the amendment Relationship to the case Patent applicant NEC Corporation 4, Agent Sagami Building, 2-21 Shinjuku 4-chome, Shinjuku-ku, Tokyo (03-350-6456) 6, Contents of the amendment ( 11 Specification, page 4, line 9, “Manually operated via line 1” (2)
The same book, page 4, line 17, ``Subtractor 40 is the number Y'' is changed to ``Subtractor 4
0 is the value Y supplied via line 2. that's all

Claims (1)

[Claims] (1) means for extracting a first part having a heavily weighted value y_0 and a second part having a lightly weighted value y_1 from the binary number Y; The weight of the least significant bit of y_0 is 1 of ω_0
The approximate value of the function f at the value y_0+ω_0/2, which is the sum of the value ω_0/2 of
/2) as first data and second data, respectively, and a new signed binary number y'_1 is obtained from the value y_1 of the second part by inverting the most significant bit of y_1. a subtracting means for generating the signed binary number y'_1 and the second data, a multiplication means for calculating and outputting a correction value by multiplying these together; and the first data and An approximation function value generation circuit comprising: an adder that performs correction by inputting the correction values and adding them together, and outputs an approximation function value of the function f for the binary number Y.