JPH04324947A - Semiconductor device - Google Patents

Abstract

PURPOSE:To prevent a short-circuit between leads and a semiconductor chip and a crack in the chip from being generated to improve the reliability of a semiconductor device. CONSTITUTION:In the thickness of a tin-plated layer 4 provided on the surface of an inner lead 3a, a bonding surface part 3a1 is formed into a thickness of 0.3 to 0.6mum, the part other than said part 3a1 is formed into a thickness of 0.3mum or thinner and the thickness of the layer 4 in the vicinity of the part 3a1 is made thinner than that of the part 3a1. An excessive Au and Sn eutectic 7a, which is generated when the lead 3a is bonded on a semiconductor chip, is reduced and the lead 3a is not brought into contact with the chip end of the chip 6 by the eutectic 7a.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device using a film carrier, and more particularly to a semiconductor device that is intended to prevent short circuits between leads and semiconductor chips and cracks in the semiconductor chips.

0002

2. Description of the Related Art FIG. 4 is a plan view for explaining a conventional semiconductor device using a film carrier, and FIG.
6 is an explanatory diagram showing a manufacturing example of the same semiconductor device, FIG. 7 is a sectional view showing the state before the leads of the conventional semiconductor device are connected to the semiconductor chip, and FIG. 8 is a diagram showing the state before the leads of the conventional semiconductor device are connected to the semiconductor chip. FIG. 3 is a cross-sectional view showing a connection state between a lead and a semiconductor chip.

In the figure, 1 is made of an insulating synthetic resin such as polyimide and has a thickness of about 75 to 100 μm and has device holes 2 having an area larger than the surface area of a semiconductor chip 6, which will be described later, arranged at equal intervals in the length direction. It is a film carrier. 3 is the thickness 30~ provided on the film carrier 1
A large number of leads made of copper metal foil each having a width of approximately 40 μm and a width of 50 to 300 μm, some of which protrude into the device hole 2 to become a free end, form an inner lead 3a. The entire surface of the inner lead 3a has a thickness of 0.
A tin plating layer 4 of 3 to 0.6 μm is provided. 5 is a sprocket hole for conveying the film carrier 1.

6 is a semiconductor chip, 6a is a semiconductor chip 7
6b is an insulating protective layer made of phosphorus glass and silicon nitride covering the aluminum electrode 6a, and 7 is a gold bump with a thickness of about 20 μm provided on the surface of the aluminum electrode 6a.

FIG. 6 is an explanatory diagram showing an example of a device for attaching a semiconductor chip 6 to a film carrier 1 as described above. Positioned. on the other hand,
The film carrier 1 guided by the film rail 10 and sent in a direction perpendicular to the plane of the paper by a sprocket stops when its device holes 2 reach the top of the semiconductor chip 6, and the film carrier 1 is guided by a film rail 10 and sent in a direction perpendicular to the plane of the paper by a sprocket. The gold bumps 7 thus formed are aligned with the tips of the inner leads 3a whose surfaces are coated with the tin plating layer 4, respectively. Next, the heated bonding tool 11 is lowered to apply pressure to each inner lead 3a, forming it at a predetermined angle, and forming the tin plating layer 4 on the tip of each inner lead 3a into each aluminum electrode 6a of the semiconductor chip 6. It is fused and connected to the gold bump 7 provided on the . After that, the film carrier 1 is moved, the leads 3 are cut, and then the semiconductor chip 6 and a part of the leads 3 are sealed with a sealing resin, or the semiconductor chip 6 and a part of the leads 3 are sealed. After sealing with a sealing resin, the leads 3 are cut to manufacture a semiconductor device.

[0006]

In the conventional semiconductor device as described above, a tin plating layer 4 having a thickness of 0.3 to 0.6 μm is provided on the entire surface of the inner lead 3a. The tin plating layer 4 on the tip of the gold bump 7 provided on each aluminum electrode 6a of the semiconductor chip 6
Since these are fused by applying pressure and heating, if the thickness of the tin plating layer provided on the surface of Ininaleed 3 is set to 0.3 μm or less, the bonding strength will decrease, and if the tin plating layer is made thick, the bonding strength will decrease excessively. The generated Au/Sn eutectic 7a gathers directly under the tip of the inner lead 3, and as shown in FIG. 8, the excess Au/Sn eutectic 7a contacts the chip end of the semiconductor chip 6, and There was a problem that there was a risk that the semiconductor chip 6 would be short-circuited with the chip end of the semiconductor chip 6.

Furthermore, when the semiconductor chip 6 and a portion of the leads 3 are sealed with a sealing resin while the excess Au/Sn eutectic 7a is in contact with the chip end of the semiconductor chip 6,
The heat of the sealing resin is absorbed by the leads 3, and the heat absorbed by the leads 3 is intensively transmitted to the chip itself via the insulating protective layer 6b of the semiconductor chip 6, the chip end, or the insulating protective film 6b. There is also the problem that thermal stress may cause cracks in the insulating protective layer 6b or the chip itself.

The present invention has been made to solve these problems, and its object is to obtain a highly reliable semiconductor device by preventing short circuits between leads and semiconductor chips and cracks in the semiconductor chips. .

[0009]

[Means for Solving the Problems] A semiconductor device according to the present invention includes a semiconductor chip disposed within a device hole of a film carrier, and gold bumps provided on a large number of aluminum electrodes of the semiconductor chip formed on the film carrier. In a semiconductor device in which the tips of inner leads each having a tin plating layer are bonded to the surface protruding into a device hole of a circuit pattern, the thickness of the tin plating layer provided on the surface of the inner lead is set to 0. 3-0
．． 6μm, and the area other than the bonding surface part is 0.3μm.
It is set to be less than μm.

Further, the thickness of the tin plating layer provided on the surface of the inner lead may be set to 0.3 to 0.6 μm on the bonding surface portion and the base end portion on the bonding surface side, and 0.3 μm or less on the other portions. .

[0011]

[Operation] In the present invention, the thickness of the tin plating layer provided on the surface of the inner lead is set to 0.
3 to 0.6 μm, and the portion other than the bonding surface portion to 0.3 μm or less, or the bonding surface portion and the base end portion on the bonding surface side to 0.3 to 0.6 μm, and the other portion to 0.3 μm or less. 0.3 μm or less, and the thickness of the tin plating layer near the bonding surface portion is thinner than that of the bonding surface portion, so when the inner lead is bonded to the gold bump provided on the aluminum electrode of the semiconductor chip, the bonding surface portion of the inner lead is thinner than the bonding surface portion. The outflow of molten tin plating in the vicinity of the semiconductor chip is reduced compared to before, the excess Au/Sn eutectic is reduced, and the Au/Sn eutectic does not come into contact with the chip edge of the semiconductor chip. . In addition, since the semiconductor chip and a portion of the leads are sealed with resin without the excessive Au/Sn eutectic coming into contact with the chip edge of the semiconductor chip, the heat of the sealing resin is transferred to the insulating protective layer of the semiconductor chip and the chip. Thermal stress is now directly and evenly transmitted to the edges, so the thermal stress is small and does not cause cracks in the insulating protective layer or the chip itself.

0012

[Embodiment] FIG. 1 is a sectional view showing a state in which a lead according to an embodiment of the present invention is connected to a semiconductor chip, and FIG. 2 is a sectional view showing a state in which a lead and a semiconductor chip are connected in the same embodiment. . In the figure, components that are the same as those of the conventional example are given the same reference numerals, and explanations of duplicated components will be omitted. A tin plating layer 4 is provided on the surface of the inner lead 3a. The tin plating layer 4 is the bonding surface portion 3a1 of the inner lead 3a.
is formed to have a thickness of 0.3 to 0.6 .mu.m, which is the same as in the conventional example, and the thickness of the portion other than the bonding surface portion 3a1 is 0.3 .mu.m or less.

In the semiconductor device configured as described above,
In the conventional example, when the inner lead 3a is bonded to the gold bump 7 provided on the aluminum electrode 6a of the semiconductor chip 6, the thickness of the tin plating layer 4 on the portion other than the bonding surface portion 3a1 of the inner lead 3a is 0.3 μm or less. The bonding surface portion 3a of the inner lead 3a is thinner than the tin plating layer 4 of the same bonding surface portion 3a1.
1. The outflow of molten tin plating in the vicinity of 1 is reduced. Therefore, the excess Au/Sn eutectic 7a is reduced, and the Au/Sn eutectic 7a no longer comes into contact with the chip end of the semiconductor chip 6, causing a short circuit between the inner lead 3 and the chip end of the semiconductor chip 6. is prevented.

[0014] Also, after that, the semiconductor chip 6 and the leads 3
Excess Au/Sn also exists when a part of the
This is carried out in a state where the eutectic 7a does not come into contact with the chip end of the semiconductor chip 6. Therefore, the heat of the sealing resin is directly and evenly transmitted to the insulation protection layer 6b of the semiconductor chip 6 and the chip edge, so thermal stress is small and no cracks occur in the insulation protection layer 6b or the chip itself. Ta.

FIG. 3 is a sectional view showing a lead according to another embodiment of the present invention. In this example, the inner lead 3
The tin plating layer 4 provided on the surface of the inner lead 3
The bonding surface portion 3a1 of a and the base end portion 3a2 on the bonding surface side have a thickness of 0.3 to 0.6 μm, which is the same as in the conventional example.
The thickness of the other portions is 0.3 μm or less.

This embodiment also has a bonding surface portion 3a1.
The thickness of the tin plating layer 4 near the bonding surface portion 3a is
It is thinner than 1. Therefore, its operations and effects are similar to those of the embodiment shown in FIG. 1, and a description of the operations and effects of this embodiment will be omitted.

[0017]

As explained above, the present invention has a tin plating layer provided on the surface of the inner lead with a thickness of 0.3 to 0.6 μm on the bonding surface portion, and a thickness of 0.3 to 0.6 μm on the surface other than the bonding surface portion. .3μm or less, or the bonding surface portion and the proximal end portion on the bonding surface side are 0.
．． 3 to 0.6 μm, and 0.3 μm or less in other parts, and the thickness of the tin plating layer near the bonding surface is thinner than that of the bonding surface, so that the inner lead can be attached to the aluminum electrode of the semiconductor chip. When bonded to a gold bump, the flow of molten tin plating in the vicinity of the bonding surface of the inner lead is smaller than before, and the excess Au/Sn eutectic is reduced, and the Au/Sn eutectic is This has the effect that objects do not come into contact with the chip end of the semiconductor chip, and short circuits between the leads and the chip end of the semiconductor chip are prevented.

Furthermore, since the resin sealing of a part of the semiconductor chip and the leads is carried out without contacting the excess Au/Sn eutectic with the chip edge of the semiconductor chip, the heat of the sealing resin is transferred to the insulation of the semiconductor chip. Thermal stress is small as it is directly and evenly transmitted to the protective layer and the chip edge, preventing cracks from occurring in the insulating protective layer and the chip itself, improving the productivity, yield, and reliability of manufactured semiconductor devices. has.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional view showing a state in which a lead according to an embodiment of the present invention is connected to a semiconductor chip.

FIG. 2 is a cross-sectional view showing a connection state between a lead and a semiconductor chip in the same embodiment.

FIG. 3 is a sectional view showing a lead according to another embodiment of the present invention.

FIG. 4 is a plan view for explaining a conventional semiconductor device using a film carrier.

FIG. 5 is a sectional view taken along the line V-V in FIG. 4;

FIG. 6 is an explanatory diagram showing an example of manufacturing the same semiconductor device.

FIG. 7 is a cross-sectional view showing a state before leads of a conventional semiconductor device are connected to a semiconductor chip.

FIG. 8 is a cross-sectional view showing a connection state of lead semiconductor chips of the same semiconductor device.

[Explanation of symbols]

3a Inner lead 3a1 Bonding surface part 4 Tin plating layer 6 Semiconductor chip 6a Aluminum electrode 6b Insulating protective layer 7 Gold bump

Claims (2)

[Claims] Claim 1: A semiconductor chip is disposed within a device hole of a film carrier, and tin is applied to a surface of a circuit pattern formed on the film carrier protruding into the device hole on gold bumps provided on a large number of aluminum electrodes of the semiconductor chip. In a semiconductor device formed by bonding the tips of inner leads each having a plating layer, the tin plating layer provided on the surface of the inner lead has a thickness of 0.3 to 0.6 μm on the bonding surface portion, and the thickness of the tin plating layer provided on the surface of the inner lead is 0.3 to 0.6 μm, and A semiconductor device characterized in that a portion of 0.3 μm or less. 2. A semiconductor chip is disposed within a device hole of a film carrier, and tin is applied to the surface of a circuit pattern formed on the film carrier protruding into the device hole on the gold bumps provided on a large number of aluminum electrodes of the semiconductor chip. In a semiconductor device in which the tips of inner leads each having a plating layer are bonded to each other, the thickness of the tin plating layer provided on the surface of the inner lead is 0.3 to 0.3 to 0.0 on the bonding surface portion and the base end portion on the bonding surface side. 6 μm,
A semiconductor device characterized in that a portion other than these is 0.3 μm or less.