JPH04315432A - Manufacture of electronic device - Google Patents

Manufacture of electronic device

Info

Publication number
JPH04315432A
JPH04315432A JP8244691A JP8244691A JPH04315432A JP H04315432 A JPH04315432 A JP H04315432A JP 8244691 A JP8244691 A JP 8244691A JP 8244691 A JP8244691 A JP 8244691A JP H04315432 A JPH04315432 A JP H04315432A
Authority
JP
Japan
Prior art keywords
insulating film
resist
etching
electronic device
resist pattern
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8244691A
Other languages
Japanese (ja)
Inventor
Wakichi Tsukuda
和吉 佃
Masayoshi Koike
正好 小池
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Eastman Kodak Japan Ltd
Original Assignee
Eastman Kodak Japan Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Eastman Kodak Japan Ltd filed Critical Eastman Kodak Japan Ltd
Priority to JP8244691A priority Critical patent/JPH04315432A/en
Publication of JPH04315432A publication Critical patent/JPH04315432A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To improve device reliability by forming an insulating film having a sloped edge to improve step coverage. CONSTITUTION:An insulating film 12 is formed on a semiconductor substrate, and a resist pattern 14 is formed. The resist pattern is given a sloped edge by baking above 100 deg.C. With this resist pattern used as a mask, the insulating film 12 is etched selectively. The flow rates of etching gases are selected to obtain a selection ratio of 0.8 or 0.4 so that the insulating film can have a sloped edge extending from that of the resist pattern. Since this improves step coverage, metallized interconnections on the insulating film have uniform thickness, thus increasing reliability.

Description

【発明の詳細な説明】[Detailed description of the invention]

【0001】0001

【産業上の利用分野】本発明は電子デバイスの製造方法
、特に選択エッチングを用いて形成される金属配線の信
頼性を向上させる電子デバイス製造方法の改良に関する
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electronic device manufacturing method, and more particularly to an improvement in the electronic device manufacturing method that improves the reliability of metal wiring formed using selective etching.

【0002】0002

【従来の技術】従来より、電子デバイスは各種方法によ
り製造されており、各製造方法においてはいかに歩留ま
りを向上させるかが大きな課題となっている。
2. Description of the Related Art Electronic devices have heretofore been manufactured by various methods, and a major problem in each manufacturing method is how to improve the yield.

【0003】図5には従来の代表的な電子デバイス製造
方法である選択エッチングを用いた方法が示されている
。半導体基板10上に絶縁膜12を形成し(図5(a)
)、更に絶縁膜12上にレジストを積層し、フォトリソ
グラフィー技術によりエッチングしてレジストパターン
14を形成する(図5(b))。
FIG. 5 shows a method using selective etching, which is a typical conventional electronic device manufacturing method. An insulating film 12 is formed on a semiconductor substrate 10 (FIG. 5(a)).
), a resist is further laminated on the insulating film 12, and etched by photolithography to form a resist pattern 14 (FIG. 5(b)).

【0004】そして、このレジストパターン14をマス
クとして絶縁膜12をエッチングする(図5(c))。 このエッチングには面内均一性に優れ、異方性エッチン
グに優れたドライエッチングが主に用いられる。エッチ
ング条件としては選択比の優れた、即ちレジストのエッ
チングレートに比較して絶縁膜のエッチングレートが数
倍高くなるような条件が設定される。
Then, the insulating film 12 is etched using the resist pattern 14 as a mask (FIG. 5(c)). Dry etching, which has excellent in-plane uniformity and excellent anisotropic etching, is mainly used for this etching. The etching conditions are set to have an excellent selectivity, that is, to make the etching rate of the insulating film several times higher than the etching rate of the resist.

【0005】最後に、レジストを除去してエッチングさ
れた絶縁膜12上に配線となる金属16を蒸着等により
形成して電子デバイスが製造される(図5(d))。
Finally, the resist is removed and a metal 16 serving as a wiring is formed on the etched insulating film 12 by vapor deposition or the like to manufacture an electronic device (FIG. 5(d)).

【0006】[0006]

【発明が解決しようとする課題】しかしながら、従来の
電子デバイス製造方法においては、選択比を高く設定し
て絶縁膜をエッチングするためその端部が急峻となり、
図5(d)にAで示した絶縁膜断差部分では金属の厚さ
が他の部分と比べて非常に薄くなっており、従って電流
を流した場合にはこの薄くなった部分で電流密度が過剰
となり、断線のおそれが生じる問題があった。
[Problems to be Solved by the Invention] However, in the conventional electronic device manufacturing method, the insulating film is etched with a high selectivity, resulting in steep edges.
The thickness of the metal in the insulating film gap area indicated by A in Figure 5(d) is very thin compared to other parts, so when current is passed, the current density is increased at this thinner area. There was a problem in that the amount of wire was excessive and there was a risk of wire breakage.

【0007】本発明は上記従来技術の有する課題に鑑み
なされたものであり、その目的は金属配線の絶縁膜端部
におけるステップカバレージを向上させて絶縁膜端部に
おいて金属配線が薄くなるのを防ぎ、断線等を防止して
電子デバイスの信頼性を向上させることが可能な電子デ
バイス製造方法を提供することにある。
The present invention was made in view of the above-mentioned problems of the prior art, and its purpose is to improve the step coverage at the end of the insulating film of the metal wiring and to prevent the metal wiring from becoming thinner at the end of the insulating film. An object of the present invention is to provide an electronic device manufacturing method that can prevent wire breakage and the like and improve the reliability of the electronic device.

【0008】[0008]

【課題を解決するための手段】上記目的を達成するため
に、本発明は基板上に順次絶縁膜及びレジストを形成す
る積層プロセスと、前記レジストをマスクとして前記絶
縁膜を選択エッチングするエッチングプロセスと、エッ
チングされた絶縁膜上に配線用金属を形成する配線形成
プロセスとを含む電子デバイス製造方法において、前記
積層プロセス後に前記マスクとなるレジスト端部に実質
的な傾斜部を形成する傾斜部形成プロセスが設けられ、
かつ前記エッチングプロセスにおける選択エッチングの
選択比を1.0以下に低く設定して前記絶縁膜端部に傾
斜部を形成することを特徴とする。
[Means for Solving the Problems] In order to achieve the above object, the present invention includes a lamination process in which an insulating film and a resist are sequentially formed on a substrate, and an etching process in which the insulating film is selectively etched using the resist as a mask. a wiring forming process of forming a wiring metal on an etched insulating film; and a sloped part forming process of forming a substantial sloped part at the end of the resist that becomes the mask after the lamination process. is established,
Further, the selective etching selectivity in the etching process is set to a low value of 1.0 or less to form a sloped portion at the end portion of the insulating film.

【0009】[0009]

【作用】本発明の電子デバイス製造方法は、レジスト端
部に実質的な傾斜部を形成し、この傾斜部を絶縁膜に反
映されるべく、従来方法とは逆に選択比を低く設定して
選択エッチングを行い、絶縁膜端部に傾斜部を形成する
のである。
[Operation] In the electronic device manufacturing method of the present invention, a substantial slope is formed at the end of the resist, and in order to reflect this slope in the insulating film, the selection ratio is set low, contrary to the conventional method. Selective etching is performed to form a sloped portion at the end of the insulating film.

【0010】このように絶縁膜端部に傾斜部が形成され
ると、その上に形成される配線用金属の絶縁膜端部にお
けるステップカバレージが向上し、ほぼ均一の厚さの金
属を得ることが可能となる。
When the sloped portion is formed at the end of the insulating film in this manner, the step coverage of the wiring metal formed thereon at the end of the insulating film is improved, and it is possible to obtain a metal having a substantially uniform thickness. becomes possible.

【0011】[0011]

【実施例】以下、図面を用いながら本発明に係る電子デ
バイス製造方法の好適な実施例を説明する。
DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the electronic device manufacturing method according to the present invention will be described below with reference to the drawings.

【0012】図1には本実施例の製造方法が示されてい
る。まず、従来の製造方法と同様に半導体基板10上に
SiN等の絶縁膜12を形成し、更にフォトレジストを
塗布する。そして、フォトリソグラフィー技術を用いて
レジストパターン14を形成する。
FIG. 1 shows the manufacturing method of this embodiment. First, as in the conventional manufacturing method, an insulating film 12 such as SiN is formed on a semiconductor substrate 10, and then a photoresist is applied. Then, a resist pattern 14 is formed using photolithography technology.

【0013】次に、本実施例ではこのレジスト端部に傾
斜部14aを形成すべく、120℃のベーキングを行っ
た。周知のごとく、フォトレジストの端部形状は現像後
のベーキング温度に依存し、100℃以上でベーキング
を行うことにより溶融しはじめ、表面張力の作用により
図1(b)に示されるように傾斜部14aが形成される
Next, in this embodiment, baking was performed at 120° C. in order to form a sloped portion 14a at the end of the resist. As is well known, the shape of the edge of a photoresist depends on the baking temperature after development, and when baking is performed at a temperature of 100°C or higher, it begins to melt, and the shape of the edge of the photoresist begins to melt as shown in FIG. 1(b) due to the effect of surface tension. 14a is formed.

【0014】このようにして、レジスト端部に傾斜部1
4aを形成した後、絶縁膜の選択エッチングプロセスに
移行する。本実施例では、ウエットエッチングではサイ
ドエッチングや均一性に問題があるため、ドライエッチ
ング法を用いた。
In this way, the inclined portion 1 is formed at the end of the resist.
After forming 4a, a selective etching process for the insulating film is performed. In this example, a dry etching method was used because wet etching has problems with side etching and uniformity.

【0015】ドライエッチングにおいては、使用するガ
スの流量を変化させることによりエッチングレートが変
化する。図2に反応ガスとしてO2 とCHF3 を用
いた実験例を示す。図において、横軸は反応ガスの流量
比、左縦軸はエッチングレート、そして右縦軸は選択比
(レジストと絶縁膜のエッチングレート比)を表してい
る。 なお、レジストのポストベークは120℃で行った。図
からわかるように、CHF3 に対するO2 の比率が
高くなるにつれてレジストに対するSiNのエッチング
レート、即ち選択比は単調に減少していき、O2 濃度
比が10%の場合で選択比は約2.3、O2 濃度比が
40%で選択比は0.8、O2 濃度比が60%で選択
比は0.5となる。
In dry etching, the etching rate is changed by changing the flow rate of the gas used. FIG. 2 shows an experimental example using O2 and CHF3 as reaction gases. In the figure, the horizontal axis represents the flow rate ratio of the reactant gas, the left vertical axis represents the etching rate, and the right vertical axis represents the selectivity (etching rate ratio between the resist and the insulating film). Note that the resist was post-baked at 120°C. As can be seen from the figure, as the ratio of O2 to CHF3 increases, the etching rate of SiN to resist, that is, the selectivity, decreases monotonically, and when the O2 concentration ratio is 10%, the selectivity is about 2.3. When the O2 concentration ratio is 40%, the selection ratio is 0.8, and when the O2 concentration ratio is 60%, the selection ratio is 0.5.

【0016】前述したように、従来の選択エッチングに
おいては選択比を高くすることによりエッチング精度の
向上化、すなわち精密化を図っているが、本実施例では
従来とは全く逆で選択比を低く設定することによりレジ
スト端部に形成された傾斜部を絶縁膜のエッチング断面
に反映されることとしている。
As mentioned above, in conventional selective etching, etching accuracy is improved, that is, precision is achieved by increasing the selectivity ratio, but in this embodiment, the etching accuracy is improved, that is, precision is achieved by increasing the selectivity ratio. By setting this, the slope formed at the end of the resist is reflected in the etched cross section of the insulating film.

【0017】このため、本実施例では、絶縁膜であるS
iNを200nm、レジスト1μm、ベーキング温度1
20℃で、ドライエッチングの選択比が0.8及び0.
4と設定することにより、絶縁膜端部の傾斜部の傾斜角
をそれぞれ45度及び20度とすることができた。
Therefore, in this embodiment, the insulating film S
iN 200nm, resist 1μm, baking temperature 1
At 20°C, the selectivity of dry etching is 0.8 and 0.
4, the inclination angles of the inclined portions at the ends of the insulating film could be set to 45 degrees and 20 degrees, respectively.

【0018】このようにして、絶縁膜に傾斜部を形成し
た後、配線用の金属を蒸着形成することにより図1(d
)に示されるようにほぼ均一の厚さを有する金属配線を
形成することができる。
After forming the sloped portion in the insulating film in this manner, metal for wiring is formed by vapor deposition, as shown in FIG. 1(d).
), it is possible to form a metal wiring having a substantially uniform thickness.

【0019】なお、上記実施例においてはベーキングを
行うことによりレジスト端部に傾斜部を形成したが、他
の方法を用いて傾斜部を形成することも可能である。
In the above embodiments, the sloped portions were formed at the ends of the resist by baking, but it is also possible to form the sloped portions using other methods.

【0020】図3にはこのような方法の一例が示されて
おり、半導体基板10上に絶縁膜12を形成する。そし
て、レジストパターンを形成する際、図3に示されるよ
うにレジストを階段上に積層して多層とし、レジスト端
部に実質的な傾斜部を形成する。そして、この多層レジ
スト15を用いて絶縁膜12を前述の実施例と同様に選
択比を低く設定することにより絶縁膜端部に傾斜部を形
成することができる。また、図4には更に他の実施例の
製造方法が示されている。この実施例においては、従来
と同様に急峻な端部を有する絶縁膜12を形成した後、
再びレジスト18を塗布する。このとき、レジスト18
と既にエッチングされた絶縁膜12とは断差を有するよ
うにレジスト18を形成する。さらにこのレジスト18
の上にレジスト20を形成し、選択エッチングを行う。
An example of such a method is shown in FIG. 3, in which an insulating film 12 is formed on a semiconductor substrate 10. When forming a resist pattern, the resist is stacked in a multi-layered manner as shown in FIG. 3 to form a multi-layered structure, and a substantial slope is formed at the end of the resist. Then, by using this multilayer resist 15 and setting the selectivity of the insulating film 12 to a low value in the same manner as in the previous embodiment, a sloped portion can be formed at the end of the insulating film. Further, FIG. 4 shows a manufacturing method of still another embodiment. In this embodiment, after forming the insulating film 12 having a steep edge as in the conventional case,
The resist 18 is applied again. At this time, resist 18
The resist 18 is formed so as to have a difference between the resist 18 and the already etched insulating film 12. Furthermore, this resist 18
A resist 20 is formed thereon, and selective etching is performed.

【0021】絶縁膜12及びレジスト18の断差部分で
はレジスト20は傾斜し、従って図中左側がより多くエ
ッチングされるため、絶縁膜12には傾斜部が形成され
ることとなる。
The resist 20 is inclined at the difference between the insulating film 12 and the resist 18, and therefore the left side in the figure is etched more, so that an inclined part is formed in the insulating film 12.

【0022】[0022]

【発明の効果】以上説明したように、本発明に係る電子
デバイス製造方法によれば、絶縁膜端部に傾斜部を形成
し、金属配線を均一化することができ、電子デバイスの
信頼性を向上させることが可能となる。
[Effects of the Invention] As explained above, according to the electronic device manufacturing method according to the present invention, it is possible to form a sloped portion at the end of an insulating film, to make metal wiring uniform, and to improve the reliability of an electronic device. It becomes possible to improve the performance.

【図面の簡単な説明】[Brief explanation of the drawing]

【図1】本発明の一実施例の製造方法の説明図である。FIG. 1 is an explanatory diagram of a manufacturing method according to an embodiment of the present invention.

【図2】同実施例の反応ガスの流量比と選択比の関係を
示すグラフ図である。
FIG. 2 is a graph diagram showing the relationship between the flow rate ratio and selection ratio of reaction gases in the same example.

【図3】本発明の他の実施例の製造方法の説明図である
FIG. 3 is an explanatory diagram of a manufacturing method according to another embodiment of the present invention.

【図4】本発明の他の実施例の製造方法の説明図である
FIG. 4 is an explanatory diagram of a manufacturing method according to another embodiment of the present invention.

【図5】従来の製造方法の説明図である。FIG. 5 is an explanatory diagram of a conventional manufacturing method.

【符号の説明】[Explanation of symbols]

10  半導体基板 12  絶縁膜 14  レジスト 15  多層レジスト 16  金属 18,20  レジスト 10 Semiconductor substrate 12 Insulating film 14 Resist 15 Multilayer resist 16 Metal 18, 20 Resist

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】基板上に順次絶縁膜及びレジストを形成す
る積層プロセスと、前記レジストをマスクとして前記絶
縁膜を選択エッチングするエッチングプロセスと、エッ
チングされた絶縁膜上に配線用金属を形成する配線形成
プロセスとを含む電子デバイス製造方法において、前記
積層プロセス後に前記マスクとなるレジスト端部に実質
的な傾斜部を形成する傾斜部形成プロセスが設けられ、
かつ前記エッチングプロセスにおける選択エッチングの
選択比を1.0以下に低く設定して前記絶縁膜端部に傾
斜部を形成することを特徴とする電子デバイス製造方法
1. A lamination process in which an insulating film and a resist are sequentially formed on a substrate, an etching process in which the insulating film is selectively etched using the resist as a mask, and a wiring in which a wiring metal is formed on the etched insulating film. In the electronic device manufacturing method including a forming process, a slope forming process is provided for forming a substantial slope at an end of the resist that becomes the mask after the lamination process,
A method for manufacturing an electronic device, characterized in that a selection ratio of selective etching in the etching process is set to a low value of 1.0 or less to form a sloped portion at an end portion of the insulating film.
JP8244691A 1991-04-15 1991-04-15 Manufacture of electronic device Pending JPH04315432A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8244691A JPH04315432A (en) 1991-04-15 1991-04-15 Manufacture of electronic device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8244691A JPH04315432A (en) 1991-04-15 1991-04-15 Manufacture of electronic device

Publications (1)

Publication Number Publication Date
JPH04315432A true JPH04315432A (en) 1992-11-06

Family

ID=13774753

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8244691A Pending JPH04315432A (en) 1991-04-15 1991-04-15 Manufacture of electronic device

Country Status (1)

Country Link
JP (1) JPH04315432A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8444867B2 (en) 2009-04-30 2013-05-21 Hynix Semiconductor Inc. Method for fabricating patterns on a wafer through an exposure process

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8444867B2 (en) 2009-04-30 2013-05-21 Hynix Semiconductor Inc. Method for fabricating patterns on a wafer through an exposure process

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