JPH0431163B2 - - Google Patents

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Publication number
JPH0431163B2
JPH0431163B2 JP60207582A JP20758285A JPH0431163B2 JP H0431163 B2 JPH0431163 B2 JP H0431163B2 JP 60207582 A JP60207582 A JP 60207582A JP 20758285 A JP20758285 A JP 20758285A JP H0431163 B2 JPH0431163 B2 JP H0431163B2
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JP
Japan
Prior art keywords
varistor
film
electrode
electrodes
voltage
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Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
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JP60207582A
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Japanese (ja)
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JPS6266605A (en
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Priority to JP60207582A priority Critical patent/JPS6266605A/en
Publication of JPS6266605A publication Critical patent/JPS6266605A/en
Publication of JPH0431163B2 publication Critical patent/JPH0431163B2/ja
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Description

【発明の詳細な説明】 〔発明の属する技術分野〕 本発明は小型電子機器の過電圧保護に適した薄
膜型の電圧非直線抵抗素子に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of the Invention] The present invention relates to a thin film type voltage nonlinear resistance element suitable for overvoltage protection of small electronic devices.

〔従来技術とその問題点〕[Prior art and its problems]

従来、電子機器,電気機器の過電圧保護のため
に、シリコンカーバイト(SiC),セレン(Se),
シリコン(Si)などの電圧非直線抵抗素子(以下
バリスタとする)が利用されてきたが、近年ZnO
を主成分とし、これに種々の添加物を混合して成
形、焼成した焼結体からなる電圧非直線抵抗素子
(以下ZnOバリスタとする)が開発された。ZnO
バリスタは制限電圧が低く、電圧非直線係数が大
きいなどの優れた特徴をもつているので、過電圧
耐量の小さい半導体素子などで構成される機器の
過電圧に対する保護に適しており、SiCバリスタ
などに代つて広く利用されるようになつた。
Conventionally, silicon carbide (SiC), selenium (Se),
Voltage nonlinear resistance elements (hereinafter referred to as varistors) such as silicon (Si) have been used, but in recent years ZnO
A voltage non-linear resistance element (hereinafter referred to as ZnO varistor) was developed, which is made of a sintered body made of ZnO as the main component, mixed with various additives, molded and fired. ZnO
Varistors have excellent features such as a low limiting voltage and a large voltage nonlinearity coefficient, so they are suitable for overvoltage protection of devices made of semiconductor elements with low overvoltage resistance, and are an alternative to SiC varistors. It became widely used.

現在実用に供されているZnOバリスタの一つと
してZnO−Pr6O11系がある。ZnO−Pr6O11系バリ
スタはZnOを主成分とし、副成分としてPrのほ
かにコバルト(Co),マグネシウム(Mg),カル
シウム(Ca),カリウム(K),クロム(Cr)な
どを元素または化合物の形で添加したものを焼成
することによつて製造されることが知られている
(特公昭57−42962号公報参照)。通常ZnOバリス
タは厚さ1mm直径10mm前後の大きさの円板状焼結
体に電極とリード線を付け、樹脂モールドを施し
たものが多く用いられている。
One of the ZnO varistors currently in practical use is the ZnO-Pr 6 O 11 system. ZnO-Pr 6 O 11 -based varistors have ZnO as the main component, and in addition to Pr as subcomponents, elements such as cobalt (Co), magnesium (Mg), calcium (Ca), potassium (K), and chromium (Cr) are also added. It is known that it can be produced by adding it in the form of a compound and firing it (see Japanese Patent Publication No. 42962/1983). ZnO varistors are usually made of a disk-shaped sintered body with a thickness of about 1 mm and a diameter of about 10 mm, attached with electrodes and lead wires, and molded with resin.

一方電子部品の小型,軽量化技術の発展に伴
い、各種小型,軽量の民生用電子機器が開発さ
れ、多くのICやLSIが使用されることから、これ
らIC,LSIを異常電圧から保護することが重要な
課題となつている。しかし、このような用途に対
しては上記の焼結体型のZnOバリスタではその大
きさが適合しない。
On the other hand, with the development of technology to reduce the size and weight of electronic components, various types of small and lightweight consumer electronic devices have been developed, and many ICs and LSIs are used, so it is necessary to protect these ICs and LSIs from abnormal voltages. has become an important issue. However, the size of the sintered ZnO varistor described above is not suitable for such uses.

この問題を解決するために近年アルミナ
(Al2O3)などの絶縁性基板上に薄膜を形成する
ことにより小型のバリスタを作製することが行な
われている(特開昭58−86704号公報参照)。薄膜
を形成する方法はいくつかあるが、ZnOバリスタ
のような多成分系酸化物ではスパツタ法が高品質
の膜が得られるために屡々用いられる。
In order to solve this problem, in recent years, small varistors have been fabricated by forming a thin film on an insulating substrate such as alumina (Al 2 O 3 ) (see Japanese Patent Laid-Open No. 86704/1983). ). There are several methods for forming thin films, but the sputtering method is often used for multi-component oxides such as ZnO varistors because it produces high-quality films.

第9図はスパツタ法により得られた従来のバリ
スタの例を示したものであり第9図aの要部断面
図のように、この素子はAl2O3基板1,白金膜の
下部電極2,ZnOバリスタ膜3,Al膜の上部電
極4がこの順に積層された構造となつており、バ
リスタ膜3は8時間のスパツタにより5μmの膜
厚が得られ、上部電極4と下部電極2間のバリス
タ電圧は約5Vである。バリスタ電圧とはバリス
タに1mAの電流を流したときの端子間電圧のこ
とであり通常imAで表わされる。この素子の
場合上部電極4にプラスの電圧を印加すると、電
流は第9図a中に矢印で方向を示したように単に
上から下に流れるので等価回路は第9図bとな
る。第9図bの5はZnOバリスタを表わす。
FIG. 9 shows an example of a conventional varistor obtained by the sputtering method. As shown in the cross - sectional view of the main part in FIG . , a ZnO varistor film 3, and an Al film upper electrode 4 are laminated in this order.The varistor film 3 has a thickness of 5 μm obtained by sputtering for 8 hours, and there is a gap between the upper electrode 4 and the lower electrode 2. Varistor voltage is approximately 5V. Varistor voltage is the voltage between the terminals when a current of 1 mA flows through the varistor, and is usually expressed in imA. In the case of this element, when a positive voltage is applied to the upper electrode 4, the current simply flows from top to bottom as indicated by the arrow in FIG. 9a, so that the equivalent circuit is as shown in FIG. 9b. 5 in FIG. 9b represents a ZnO varistor.

以上のごとく構成された従来素子では、実用に
供するためにさらにバリスタ電圧を高めたいと
き、バリスタ膜厚を厚くしなければならないが、
スパツタ装置の製膜速度が遅いために、所望のバ
リスタ電圧をもつた薄膜型ZnOバリスタを製造す
るには長時間を要し、製造効率が悪くなるという
問題がある。
In the conventional device configured as described above, when it is desired to further increase the varistor voltage for practical use, the varistor film thickness must be increased.
Since the film forming speed of the sputtering device is slow, it takes a long time to manufacture a thin film ZnO varistor with a desired varistor voltage, resulting in a problem of poor manufacturing efficiency.

〔発明の目的〕[Purpose of the invention]

本発明は上述の点に鑑みてなされたものであ
り、その目的はスパツタ法により短時間に製膜さ
れる薄い膜厚のバリスタ膜で所望のバリスタ電圧
を得られる薄膜型バリスタを提供することにあ
る。
The present invention has been made in view of the above points, and its purpose is to provide a thin-film varistor that can obtain a desired varistor voltage with a thin varistor film formed in a short time by a sputtering method. be.

〔発明の要点〕[Key points of the invention]

本発明はZnOバリスタ膜が非常に優れた電圧非
直線を有しているためほとんどの電流が電極面に
垂直方向に流れるとの認識の下に、絶縁性基板上
に電極を設け、この電極上にバリスタ膜をスパツ
タし、さらにスパツタ膜上に適当な距離をおいて
複数個の電極を設けた素子構成とし、下部電極と
上部電極のうち一方面の電極が対向する他方面の
電極より多い電極数を備え、かつ多い電極数を有
する一方面の電極の電極間に対向する部分に他方
面の電極が少なくとも位置し、さらに他方面の電
極を前記電極間より少なくと大きくし、薄いバリ
スタ膜のものでも、電極の配列を変えることによ
り、所望のバリスタ電圧を有する小型の薄膜型バ
リスタが得られるようにしたものである。
In the present invention, an electrode is provided on an insulating substrate, based on the understanding that most of the current flows perpendicularly to the electrode surface because the ZnO varistor film has excellent voltage non-linearity. A varistor film is sputtered on the sputtered film, and a plurality of electrodes are provided at an appropriate distance on the sputtered film. The electrode on the other side is located at least in a portion facing between the electrodes on the one side having a large number of electrodes, and the electrode on the other side is made smaller and larger than the space between the electrodes, and a thin varistor film is formed. However, by changing the arrangement of the electrodes, a small thin-film varistor having a desired varistor voltage can be obtained.

〔発明の実施例〕[Embodiments of the invention]

以下本発明を実施例に基づき説明する。 The present invention will be explained below based on examples.

第1図は本発明による構成のZnOバリスタの一
例を示し、第1図aは要部断面図,第1図bは等
価回路図であり、それぞれ第9図aおよび第9図
bと同一機能をもつ部分を同一符号で表わしてあ
る。
Fig. 1 shows an example of a ZnO varistor configured according to the present invention, Fig. 1a is a sectional view of the main part, and Fig. 1b is an equivalent circuit diagram, and has the same function as Fig. 9a and Fig. 9b, respectively. The parts with the same reference numerals are used.

第1図aに示す素子は次のように作製したもの
である。鏡面研摩したAl2O3基板1上にスパツタ
により下部電極2として白金膜を形成し、次いで
主成分のZnOに、Pr,Coなどを添加した焼結体
をターゲツトとして下部電極2の白金膜上にバリ
スタ膜3を形成する。スパツタ装置はマグネトロ
ン型の高周波スパツタ装置であり、製膜条件は電
力約4W/cm2,使用ガスArと酸素の割合が90:10
の混合ガス,ガス圧0.01Torr,基板温度を300℃
である。かくして8時間のスパツタにより膜厚
5μのZnOバリスタ膜3が得られるが、そのときの
製膜速度は1時間当りおよび0.6μmである。この
ものを1100℃で30分間大気中で熱処理を施した
後、バリスタ膜3上にマスクを用いて真空蒸着に
よりAl膜の二つの上部電極4a,4bを後述す
る適当な距離を隔てて形成する。なお電子顕微鏡
を用いて観察すると熱処理後のバリスタ膜3の粒
径は約2μmであつた。電圧非直線性は熱処理温
度が800℃以上で生じるサージ耐量の点を考慮す
れば1000℃以上とするのが実用的である。しかし
熱処理温度が1400℃以上になると、バリスタ膜3
の添加物の一部が蒸発し電圧非直線性が著しく低
下する。第1図bは後述する等価回路図である。
The device shown in FIG. 1a was manufactured as follows. A platinum film is formed as the lower electrode 2 on a mirror-polished Al 2 O 3 substrate 1 by sputtering, and then a sintered body containing ZnO as the main component with Pr, Co, etc. added is used as a target to deposit the platinum film on the lower electrode 2. A varistor film 3 is then formed. The sputtering device is a magnetron-type high-frequency sputtering device, and the film forming conditions are approximately 4 W/cm 2 of power and a ratio of Ar and oxygen used gases of 90:10.
mixed gas, gas pressure 0.01Torr, substrate temperature 300℃
It is. In this way, the film thickness was increased by sputtering for 8 hours.
A ZnO varistor film 3 with a thickness of 5 μm is obtained, and the film forming rate is 0.6 μm per hour. After heat-treating this material at 1100° C. for 30 minutes in the atmosphere, two upper electrodes 4a and 4b of Al film are formed on the varistor film 3 by vacuum evaporation using a mask, separated by an appropriate distance as will be described later. . When observed using an electron microscope, the grain size of the varistor film 3 after the heat treatment was approximately 2 μm. It is practical to set the voltage nonlinearity to 1000°C or higher, considering the surge resistance that occurs when the heat treatment temperature is 800°C or higher. However, when the heat treatment temperature exceeds 1400℃, the varistor film 3
Part of the additive evaporates and voltage nonlinearity decreases significantly. FIG. 1b is an equivalent circuit diagram to be described later.

一方第1図aに示したバリスタ膜3上の上部電
極4a,4bの適切な間隔を決めるために、微細
加工技術を用いて上部電極4a,4bの間隔を2
〜100μmの範囲で変化させ、このとき素子本体
をどの程度電流が流れるかを確認した。そのため
の素子構成断面と配線状態を第2図に示す。第2
図において白金下部電極2の中央巾約20μmの溝
を設けて分離しこの間に電流計A−1を設け、電
源は定電流電源6を用い、電源電流のモニターと
して電流計A−2を接続し、常に1mAの電流が
流れるようにした。かくして2個のAl上部電極
4a,4bの電極間隔と電流計A−1の電流との
関係として第3図に示す線図が得られる。第3図
にはバリスタ膜厚5μmのときの曲線イとともに
バリスタ膜厚が10μmの場合も示してある。第3
図から曲線イでは上部電極間隔が6μm以上であ
るとほとんどの電流が素子に流れ曲線ロでは上部
電極間隔が12μm以上になるとほとんどの電流が
素子に流れることがわかる。このことは、ZnOバ
リスタ膜がα=18という優れた電圧非直線係数を
有するため、電流は電圧に大きく依存するので電
圧分担が1.2倍、すなわちバリスタ膜厚の約1.2倍
の電極間距離があれば表面を流れる電流はほとん
どないということができる。
On the other hand, in order to determine the appropriate spacing between the upper electrodes 4a and 4b on the varistor film 3 shown in FIG.
The current was varied within a range of ~100 μm, and it was confirmed how much current flows through the element body at this time. FIG. 2 shows a cross section of the element structure and wiring state for this purpose. Second
In the figure, a groove with a width of approximately 20 μm is provided at the center of the platinum lower electrode 2 to separate it, and an ammeter A-1 is installed between the grooves, a constant current power source 6 is used as the power source, and an ammeter A-2 is connected as a monitor of the power supply current. , so that a current of 1 mA always flows. In this way, the diagram shown in FIG. 3 is obtained as the relationship between the electrode spacing between the two Al upper electrodes 4a and 4b and the current of the ammeter A-1. FIG. 3 also shows the curve A when the varistor film thickness is 5 μm, as well as the curve A when the varistor film thickness is 10 μm. Third
From the figure, it can be seen that in curve A, most of the current flows to the element when the upper electrode interval is 6 μm or more, and in curve B, most of the current flows to the element when the upper electrode interval is 12 μm or more. This means that since the ZnO varistor film has an excellent voltage nonlinear coefficient of α=18, the current is highly dependent on the voltage, so the voltage sharing is 1.2 times, that is, the distance between the electrodes is about 1.2 times the varistor film thickness. It can be said that almost no current flows through the surface.

本発明の素子構成を示す第1図aが従来素子の
第9図aと異なる点は、両図の比較から明らかな
ように、第1図aでは二つの上部電極4a,4b
をバリスタ膜厚のほぼ1.2倍の間隔をもつて備え
ていることである。かくして上部電極4aにプラ
スの電圧を印加したとき流れる電流の方向は第1
図aに矢印で示したように、従来素子第9図aの
ごとく単に上から下に流れるのではなく、上部電
極4a,バリスタ膜3,下部電極2,バリスタ膜
3,上部電極4bの順に流れ、この素子の等価回
路は二つのZnO素子5が直列に接続された第1図
bであり、下部電極2は電極というより寧ろリー
ド線の役割をもつている。
The difference between FIG. 1a showing the device configuration of the present invention and FIG. 9a of the conventional device is that in FIG. 1a, the two upper electrodes 4a and 4b are
The spacing is approximately 1.2 times the varistor film thickness. Thus, when a positive voltage is applied to the upper electrode 4a, the direction of the current flowing is the first
As shown by the arrow in Figure a, the flow does not simply flow from top to bottom as in Figure 9a of the conventional device, but flows in the order of upper electrode 4a, varistor film 3, lower electrode 2, varistor film 3, and upper electrode 4b. The equivalent circuit of this element is shown in FIG. 1b, in which two ZnO elements 5 are connected in series, and the lower electrode 2 has the role of a lead wire rather than an electrode.

このように作製した本発明のZnOバリスタのバ
リスタ膜3上の2個のAl上部電極4a,4b間
のバリスタ電圧は約10V,電圧非直線係数αは18
である。このことは従来素子と同じ製膜時間とバ
リスタ膜厚を有する本発明の素子は従来素子に比
べて2倍のバリスタ電圧が得られるものであり、
逆に従来素子で本発明と同じバリスタ電圧とする
ためには2倍の膜厚の製膜時間が必要になること
を意味する。
The varistor voltage between the two Al upper electrodes 4a and 4b on the varistor film 3 of the ZnO varistor of the present invention manufactured in this way is approximately 10 V, and the voltage nonlinear coefficient α is 18
It is. This means that the device of the present invention, which has the same film forming time and varistor film thickness as the conventional device, can obtain twice the varistor voltage compared to the conventional device.
Conversely, this means that in order to obtain the same varistor voltage as in the present invention with a conventional element, it is necessary to form a film twice as thick as the film.

また前述のように電極間隔はバリスタ膜厚の約
1.2倍程度でほとんど表面を流れる電流はないが、
もし電極間隔をバリスタ膜厚の1.2倍以内とした
ときは、例えば第1図aの素子では矢印方向にほ
とんどの電流が流れるようにエツチングなどによ
つて第4図,第5図に示したようにバリスタ膜3
の電極4a,4b間に溝を設ければよい。第4
図,第5図はいずれも第1図aに対応する素子断
面であつて第4図は溝Bが下部電極2まで達して
おり、第5図は溝Cが下部電極2まで貫通するこ
となく一部を残した場合である。
Also, as mentioned above, the electrode spacing is approximately the same as the varistor film thickness.
There is almost no current flowing on the surface at about 1.2 times, but
If the electrode spacing is set to within 1.2 times the varistor film thickness, for example, in the device shown in Fig. 1a, most of the current flows in the direction of the arrow, as shown in Figs. 4 and 5 by etching, etc. Varistor film 3
A groove may be provided between the electrodes 4a and 4b. Fourth
5 and 5 are device cross sections corresponding to FIG. 1 a. In FIG. 4, the groove B reaches the lower electrode 2, and in FIG. 5, the groove C does not penetrate to the lower electrode 2. This is the case when some parts are left behind.

次に第6図は第1図aに示したのと同じ製造方
法によりバリスタ膜の厚さが5μmでバリスタ電
圧が2倍すなわち20Vを有し、従来素子第9図a
の4倍の値となる素子構成を示した要部断面図で
ある。第6図が第1図aと異なる点は3個の上部
電極4c,4d,4eと2個の下部電極2a,2
bを備えていることである。前述の電極間隔とバ
リスタ膜厚との関係は下部電極に関しても同様で
あるから、第6図におけるAl上部電極4cと4
d間,4dと4e間,白金下部電極2aと2b間
はそれぞれ電極間隔をZnOバリスタ膜3の厚さの
1.2倍以上にする必要がある。このようにすると
電流は矢印で示した通り、上部電極4e,バリス
タ膜3,下部電極2a,バリスタ膜3,上部電極
4d,バリスタ膜3,下部電極2b,バリスタ膜
3,上部電極4eの順に流れ、第1図aの場合よ
り電流経路を増すことができる。
Next, FIG. 6 shows a conventional device in which the thickness of the varistor film is 5 μm and the varistor voltage is twice that of 20 V, using the same manufacturing method as shown in FIG. 1a.
FIG. 3 is a cross-sectional view of a main part showing an element configuration in which the value is four times as large as . The difference between FIG. 6 and FIG. 1a is that there are three upper electrodes 4c, 4d, 4e and two lower electrodes 2a, 2.
b. Since the above-mentioned relationship between the electrode spacing and the varistor film thickness is the same for the lower electrode, the Al upper electrodes 4c and 4 in FIG.
The electrode spacing between d, between 4d and 4e, and between platinum lower electrodes 2a and 2b is the same as the thickness of the ZnO varistor film 3.
It needs to be 1.2 times or more. In this way, the current flows in the order of upper electrode 4e, varistor film 3, lower electrode 2a, varistor film 3, upper electrode 4d, varistor film 3, lower electrode 2b, varistor film 3, and upper electrode 4e, as shown by the arrow. , the number of current paths can be increased compared to the case of FIG. 1a.

第7図は第6図と同様の手法により、第1図a
の場合の3倍のバリスタ電圧すなわち30Vが得ら
れる素子構成の要部断面であり、4個のAl上部
電極4f,4g,4h,4iと3個の白金下部電
極2c,2d,2eとを備えており、電極間隔を
それぞれバリスタ膜3の1.2倍以上としてある。
電流は矢印の方向に流れるから、第6図の場合よ
りさらに電流経路を増すことができる。
Figure 7 was created using the same method as Figure 6.
This is a cross section of the main part of the element configuration that can obtain a varistor voltage three times that of the case of 30 V, which is 3 times higher than that in the case of The electrode spacing is set to be 1.2 times or more that of the varistor film 3, respectively.
Since the current flows in the direction of the arrow, the number of current paths can be further increased than in the case of FIG.

以上のように本発明の素子は電極数と電極間隔
を適切に決めることにより、バリスタ膜厚を一定
にしたままバリスタ電圧を高めることができる
が、これらの決定に当つてはバリスタ膜の所定の
大きさ内で電極形成の難易などを勘案して最適と
なるようにするのがよい。
As described above, the device of the present invention can increase the varistor voltage while keeping the varistor film thickness constant by appropriately determining the number of electrodes and the electrode spacing. It is preferable to optimize the size by taking into consideration the difficulty of electrode formation.

なお以上述べてきた例では各図に示したよう
に、上部電極の左右端を端子としてあるが、素子
の用途に応じて第8図のごとく下部電極を端子と
しても同様の効果が得られ、この場合の電流経路
は矢印のようになる。
In the examples described above, the left and right ends of the upper electrode are used as terminals as shown in each figure, but the same effect can be obtained by using the lower electrode as a terminal as shown in FIG. 8, depending on the application of the device. In this case, the current path looks like an arrow.

また本実施例ではスパツタ膜を形成する基板を
Al2O3板としているが、基板は熱処理温度に耐え
ることのできる絶縁性材料ならばAl2O3に限るこ
となく、石英,ベリリウム(Be)を添加した炭
化珪素もしくはマグネシア(MgO)などを用い
てもよい。下部電極材料として用いた白金につい
ても熱処理温度に耐えることのできる貴金属例え
ばAuなどでもよい。上部電極にはあまり制約は
なく、AlのほかにAg,Au,Cuなど導電性金属
も使用することができる。
In addition, in this example, the substrate on which the sputtered film is formed is
Although the substrate is made of an Al 2 O 3 plate, it is not limited to Al 2 O 3 as long as it is an insulating material that can withstand the heat treatment temperature, but it can also be made of quartz, silicon carbide doped with beryllium (Be), or magnesia (MgO). May be used. The platinum used as the lower electrode material may also be a noble metal such as Au, which can withstand the heat treatment temperature. There are not many restrictions on the upper electrode, and in addition to Al, conductive metals such as Ag, Au, and Cu can also be used.

さらにバリスタ膜はこれまでZnOバリスタ膜と
して説明したが、電圧非直線性を有する膜であれ
ばZnOバリスタ膜に限ることなく、BaTiO3バリ
スタ膜,SrTiO3バリスタ膜などを用いても本発
明の効果が認められる。
Furthermore, although the varistor film has been described as a ZnO varistor film, the effects of the present invention are not limited to ZnO varistor films as long as they have voltage nonlinearity, and the effects of the present invention can also be achieved using BaTiO 3 varistor films, SrTiO 3 varistor films, etc. is recognized.

以上説明してきたように、本発明は薄いバリス
タ膜厚のまま、電極の配列を変えるだけで所望の
バリスタ電圧を有する小型の薄膜型バリスタとし
たものである。
As described above, the present invention provides a small thin-film varistor that has a desired varistor voltage by simply changing the arrangement of electrodes while maintaining a small varistor film thickness.

〔発明の効果〕〔Effect of the invention〕

電子機器などの異常電圧保護に用いられる小
型・薄膜型バリスタは、従来バリスタ膜にただ1
個の上部電極と下部電極を備えており、電流は単
に上から下に流れるので薄いスパツタ膜で所望の
バリスタ電圧を得られらないときはバリスタ膜厚
を厚くしなければならなかつたのに対し、本発明
によれば実施例で説明したように、下部電極と上
部電極のうち一方面の電極が対向する他方面の電
極より多い電極数を備え、かつ多い電極数を有す
る一方面の電極の電極間に対向する部分に他方面
の電極が少なくとも位置し、さらに他方面の電極
を前記電極間より少なくとも大きくし、電極間隔
をバリスタ膜厚の1.2倍程度とし、電流経路が上
部電極−バリスタ膜−下部電極−バリスタ膜−上
部電極となるように電極を配置して、複数個のバ
リスタを直列に接続した電気的等価回路をもつよ
うにしたため、スパツタによる薄いバリスタ膜の
まま電極の配列条件を最適に設定することによ
り、所望のバリスタ電圧を得ることができ、製膜
が短時間で行なわれ、製造効率が高く、使用機器
の小型・軽量化に適した薄膜型バリスタとしたも
のである。
Compact, thin-film varistors used for abnormal voltage protection in electronic equipment, etc., are the only conventional varistor films.
The current flows simply from top to bottom, so if the desired varistor voltage could not be obtained with a thin sputtered film, the varistor film had to be made thicker. According to the present invention, as explained in the embodiment, the electrode on one side of the lower electrode and the upper electrode has a larger number of electrodes than the electrode on the other opposing side, and the electrode on one side has a larger number of electrodes. At least the electrode on the other side is located in the part facing between the electrodes, and the electrode on the other side is made at least larger than the gap between the electrodes, the electrode spacing is about 1.2 times the varistor film thickness, and the current path is between the upper electrode and the varistor film. By arranging the electrodes as follows: - lower electrode - varistor film - upper electrode, we created an electrical equivalent circuit in which multiple varistors were connected in series. By setting it optimally, the desired varistor voltage can be obtained, the film can be formed in a short time, the manufacturing efficiency is high, and the thin film type varistor is suitable for reducing the size and weight of the equipment used.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明によるZnOバリスタを示しaは
面部断面図、bは等価回路図、第2図は第1図a
の上部電極間隔と素子本体を流れる電流の関係を
得るための素子断面と回路配線図、第3図は上部
電極間隔と素子本体を流れる電流との関係を表わ
す線図、第4図、第5図はいずれも第1図aの上
部電極間に溝を設け、第4図は溝が下部電極まで
貫通し、第5図は溝が下部電極に達しないものの
断面図、第6図は第1図aの2倍のバリスタ電圧
を有する素子の構成を示す断面図、第7図は第1
図aの3倍のバリスタ電圧を有する素子の構成を
示す断面図、第8図は下部電極を端子とする場合
の例を示す本発明の素子断面図、第9図は従来の
ZnOバリスタを示し、aは要部断面図、bは等価
回路図である。 1……基板、2,2a,2b,2c,2d,2
e,2f,2g,2h……下部電極、3……バリ
スタ膜、4,4a,4b,4c,4d,4e,4
f,4g,4h,4i,4j,4k……上部電
極、5……ZnOバリスタ、6……定電流電源、A
−1,A−2……電流計、B,C……溝。
Fig. 1 shows a ZnO varistor according to the present invention, a is a cross-sectional view of the surface, b is an equivalent circuit diagram, and Fig. 2 is the same as Fig. 1 a.
Figure 3 is a diagram showing the relationship between the upper electrode interval and the current flowing through the element body; Figures 4 and 5 are diagrams showing the relationship between the upper electrode interval and the current flowing through the element body. In each figure, a groove is provided between the upper electrodes in Figure 1a, in Figure 4 the groove penetrates to the lower electrode, in Figure 5 the groove does not reach the lower electrode, and in Figure 6 it is a cross-sectional view of the groove between the upper electrodes. A cross-sectional view showing the structure of an element having twice the varistor voltage as in Figure a, Figure 7 is
A cross-sectional view showing the configuration of an element having a varistor voltage three times that in Figure a, Figure 8 is a cross-sectional view of the element of the present invention showing an example in which the lower electrode is used as a terminal, and Figure 9 is a conventional element configuration.
A ZnO varistor is shown, in which a is a sectional view of a main part and b is an equivalent circuit diagram. 1...Substrate, 2, 2a, 2b, 2c, 2d, 2
e, 2f, 2g, 2h... lower electrode, 3... varistor film, 4, 4a, 4b, 4c, 4d, 4e, 4
f, 4g, 4h, 4i, 4j, 4k... Upper electrode, 5... ZnO varistor, 6... Constant current power supply, A
-1, A-2... Ammeter, B, C... Groove.

Claims (1)

【特許請求の範囲】 1 絶縁性基板上に下部電極,電圧非直線性を有
するバリスタ膜,上部電極をこの順に積層し、下
部電極と上部電極とがバリスタ膜を介在して対向
してなる薄膜型電圧非直線抵抗素子において、前
記下部電極と前記上部電極のうち一方面の電極が
対向する他方面の電極より多い電極数を備え、か
つ多い電極数を有する一方面の電極の電極間に対
向する部分に他方面の電極が少なくとも位置し、
さらに他方面の電極が前記電極間より少なくとも
大きいことを特徴とする薄膜型電圧非直線抵抗素
子。 2 特許請求の範囲第1項記載の素子において、
バリスタ膜としてZnOバリスタ膜を用いることを
特徴とする薄膜型電圧非直線抵抗素子。 3 特許請求の範囲第1項記載の素子において、
バリスタ膜としてBaTiO3バリスタ膜を用いるこ
とを特徴とする薄膜型電圧非直線抵抗素子。 4 特許請求の範囲第1項記載の素子において、
バリスタ膜としてSrTiO3バリスタ膜を用いるこ
とを特徴とするとする薄膜型電圧非直線抵抗素
子。 5 特許請求の範囲第1項ないし第4項記載の素
子において、上部電極間隔および下部電極間隔を
バリスタ膜厚の約1.2倍とすることを特徴とする
薄膜型電圧非直線抵抗素子。 6 特許請求の範囲第1項ないし第4項記載の素
子において、上記電極間のバリスタ膜に溝を設け
ることを特徴とする薄膜型電圧非直線抵抗素子。
[Claims] 1. A thin film in which a lower electrode, a varistor film having voltage nonlinearity, and an upper electrode are laminated in this order on an insulating substrate, and the lower electrode and the upper electrode face each other with the varistor film interposed. type voltage nonlinear resistance element, in which the electrode on one side of the lower electrode and the upper electrode has a greater number of electrodes than the electrode on the other opposing side, and the electrodes on the one side having the larger number of electrodes are opposed to each other. the electrode on the other side is located at least in the part where the
Furthermore, the thin film type voltage nonlinear resistance element is characterized in that the electrode on the other side is at least larger than the gap between the electrodes. 2. In the device according to claim 1,
A thin film type voltage nonlinear resistance element characterized by using a ZnO varistor film as a varistor film. 3. In the device according to claim 1,
A thin film type voltage nonlinear resistance element characterized by using a BaTiO 3 varistor film as a varistor film. 4. In the device according to claim 1,
A thin film type voltage nonlinear resistance element characterized in that a SrTiO 3 varistor film is used as a varistor film. 5. A thin film voltage non-linear resistance element according to claims 1 to 4, characterized in that the upper electrode interval and the lower electrode interval are approximately 1.2 times the varistor film thickness. 6. A thin film voltage nonlinear resistance element according to any one of claims 1 to 4, characterized in that a groove is provided in the varistor film between the electrodes.
JP60207582A 1985-09-19 1985-09-19 Voltage nonlinear resistance element Granted JPS6266605A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60207582A JPS6266605A (en) 1985-09-19 1985-09-19 Voltage nonlinear resistance element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60207582A JPS6266605A (en) 1985-09-19 1985-09-19 Voltage nonlinear resistance element

Publications (2)

Publication Number Publication Date
JPS6266605A JPS6266605A (en) 1987-03-26
JPH0431163B2 true JPH0431163B2 (en) 1992-05-25

Family

ID=16542141

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60207582A Granted JPS6266605A (en) 1985-09-19 1985-09-19 Voltage nonlinear resistance element

Country Status (1)

Country Link
JP (1) JPS6266605A (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW524671B (en) * 2000-06-14 2003-03-21 Koninkl Philips Electronics Nv Device for monitoring a vital sign
JP4697528B2 (en) * 2004-06-02 2011-06-08 太陽誘電株式会社 Elastic wave device
JP5079632B2 (en) * 2008-08-12 2012-11-21 立山科学工業株式会社 ESD protection element

Also Published As

Publication number Publication date
JPS6266605A (en) 1987-03-26

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