JPH0430161B2 - - Google Patents

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Publication number
JPH0430161B2
JPH0430161B2 JP58079329A JP7932983A JPH0430161B2 JP H0430161 B2 JPH0430161 B2 JP H0430161B2 JP 58079329 A JP58079329 A JP 58079329A JP 7932983 A JP7932983 A JP 7932983A JP H0430161 B2 JPH0430161 B2 JP H0430161B2
Authority
JP
Japan
Prior art keywords
thick film
layer
conductors
film resistor
conductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP58079329A
Other languages
Japanese (ja)
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JPS59204201A (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
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Priority to JP58079329A priority Critical patent/JPS59204201A/en
Publication of JPS59204201A publication Critical patent/JPS59204201A/en
Publication of JPH0430161B2 publication Critical patent/JPH0430161B2/ja
Granted legal-status Critical Current

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  • Apparatuses And Processes For Manufacturing Resistors (AREA)
  • Non-Adjustable Resistors (AREA)

Description

【発明の詳細な説明】 (技術分野) 本発明は厚膜抵抗体アレイならびにその製造方
法に関するものであり、特に抵抗体を高密度に配
列することのできる厚膜抵抗体アレイならびにそ
の製造方法に関するものである。
DETAILED DESCRIPTION OF THE INVENTION (Technical Field) The present invention relates to a thick film resistor array and a method for manufacturing the same, and particularly relates to a thick film resistor array in which resistors can be arranged in high density and a method for manufacturing the same. It is something.

(従来技術) 第1図は従来の厚膜抵抗体アレイの構成を説明
する平面図である。1はセラミツク基板、2は電
極、3は厚膜抵抗体である。図示するようにセラ
ミツク基板1上に厚膜印刷法により、厚膜抵抗体
3の両端2′,2′で電極2,2が接続されるよ
う、セラミツク基板1上に一重構造で被着されて
横方向に複数配列される構成であつた。しかるに
厚膜印刷法によるこのような構成では、隣接の導
体間のピツチは、図上4に示されるものである
が、実現できるのは0.2mm程度であつて電子機器
の小型化等に伴ない厚膜抵抗体アレイを更に高密
度化することが困難であるという欠点があつた。
(Prior Art) FIG. 1 is a plan view illustrating the configuration of a conventional thick film resistor array. 1 is a ceramic substrate, 2 is an electrode, and 3 is a thick film resistor. As shown in the figure, the thick film resistor 3 is coated in a single layer structure on the ceramic substrate 1 by a thick film printing method so that the electrodes 2, 2 are connected at both ends 2', 2' of the thick film resistor 3. It had a configuration in which a plurality of them were arranged in the horizontal direction. However, in such a configuration using the thick film printing method, the pitch between adjacent conductors, as shown in 4 in the diagram, can only be achieved at around 0.2 mm, and as electronic devices become smaller, A drawback is that it is difficult to further increase the density of the thick film resistor array.

(発明の目的) 本発明の目的は、前記の欠点を解決しようとす
るものであつて、厚膜抵抗体の両電極を二層構造
となるように構成し、各層の電極より引出しする
とともに、配列を高密度化したことを特徴とする
厚膜抵抗体アレイならびにその製造方法を得るよ
うにしたものであり、以下図面により詳細説明す
る。
(Objective of the Invention) The object of the present invention is to solve the above-mentioned drawbacks, by configuring both electrodes of a thick-film resistor to have a two-layer structure, leading out from the electrodes of each layer, and A thick film resistor array characterized by a high density array and a method for manufacturing the same are obtained, and will be described in detail below with reference to the drawings.

(発明の構成) 本発明の厚膜抵抗体アレイは、厚膜印刷法によ
り基板上に複数の電極導体を、所定の間隔を設け
て千鳥状に形成した2列の第1層導体と、該第1
層導体表面と該導体に隣接する基板表面との所定
部分上に形成した絶縁層と、前記基板表面の所定
部分の絶縁層上に、第1層導体と所定の距離をも
つて対向する複数の電極導体を千鳥状に形成した
第2層導体と、前記第1および第2層導体のそれ
ぞれの端部に接続された複数の厚膜抵抗体とから
構成されるものであり、その製造方法は厚膜印刷
法により、基板上に、千鳥状に2列の第1層導体
を形成する第1工程と、該第1層導体表面上と、
それに隣接する基板表面上とに絶縁層を形成する
第2工程と、該絶縁層上の所定部分に第2層導体
を形成する第3工程と、第1および第2層導体の
各電極導体の端部を一体的に接続する厚膜抵抗体
を形成する第4工程と、該厚膜抵抗体を切断し、
個別の厚膜抵抗体に分離する第5工程とにより構
成される。
(Structure of the Invention) The thick film resistor array of the present invention includes two rows of first layer conductors formed by forming a plurality of electrode conductors in a staggered manner at predetermined intervals on a substrate by a thick film printing method; 1st
an insulating layer formed on a predetermined portion of the layer conductor surface and a substrate surface adjacent to the conductor; and a plurality of insulating layers formed on the predetermined portion of the substrate surface facing the first layer conductor at a predetermined distance. It is composed of a second layer conductor in which electrode conductors are formed in a staggered pattern, and a plurality of thick film resistors connected to the respective ends of the first and second layer conductors, and the manufacturing method thereof is as follows. A first step of forming two rows of first layer conductors in a staggered manner on the substrate by a thick film printing method, and on the surface of the first layer conductors,
a second step of forming an insulating layer on the surface of the substrate adjacent thereto; a third step of forming a second layer conductor on a predetermined portion of the insulating layer; a fourth step of forming a thick film resistor whose ends are integrally connected; and cutting the thick film resistor;
and a fifth step of separating into individual thick film resistors.

(実施例) 第2図は本発明の1実施例の構成を説明する平
面図である。第3図は第2図のA−A′の切断図
である。第4図は本発明の1実施例の製造方法の
説明図で、同図aは第1程を示し、イはB−
B′断面図、ロはC−C′断面図である。以下、bは
第2工程および、その断面図、cは第3工程およ
び、その断面図、dは第4工程およびその断面図
で、第5工程はdの18にそつて厚膜抵抗体15
を個別厚膜抵抗体15′に切断分離する工程であ
る。
(Embodiment) FIG. 2 is a plan view illustrating the configuration of an embodiment of the present invention. FIG. 3 is a cutaway view taken along line A-A' in FIG. FIG. 4 is an explanatory diagram of a manufacturing method according to an embodiment of the present invention, in which a shows the first step, and a shows B-
B' is a sectional view, and B is a C-C' sectional view. Hereinafter, b is the second step and its sectional view, c is the third step and its sectional view, d is the fourth step and its sectional view, and the fifth step is the thick film resistor 15 along 18 of d.
This is a step of cutting and separating the thick film resistors 15' into individual thick film resistors 15'.

第2図、第3図、第4図において、11はセラ
ミツク基板、12は第1層導体、12′は第1層
導体の電極部分、13は絶縁層、14は第2層導
体、15は厚膜抵抗体、15′は個別厚膜抵抗体、
18は個別厚膜抵抗体間の中心である。
2, 3, and 4, 11 is a ceramic substrate, 12 is a first layer conductor, 12' is an electrode portion of the first layer conductor, 13 is an insulating layer, 14 is a second layer conductor, and 15 is a Thick film resistor, 15' is individual thick film resistor,
18 is the center between individual thick film resistors.

セラミツク基板11上に厚膜抵抗体15の片側
の電極として、第1層導体12を、第4図aに示
す第1工程のように、厚膜印刷法によつて千鳥状
に形成した後、結晶化ガラスの絶縁層13を第4
図bの第2工程に示すように、厚膜印刷法によ
り、第1層導体12上に一体的に形成する。この
時第1層導体12の電極部分12′は露出するよ
うにする。つぎに、厚膜印刷法により、厚膜抵抗
体15の他の側の電極として第1層導体12のた
て方向延長線上で、第4図cの第3工程に示す如
く、第1層導体12に対応するように第2層導体
14を絶縁層13上に形成する。
After forming the first layer conductor 12 as an electrode on one side of the thick film resistor 15 on the ceramic substrate 11 in a staggered manner by a thick film printing method as in the first step shown in FIG. 4a, The fourth insulating layer 13 of crystallized glass
As shown in the second step of FIG. b, it is integrally formed on the first layer conductor 12 by a thick film printing method. At this time, the electrode portion 12' of the first layer conductor 12 is exposed. Next, as shown in the third step of FIG. 4c, a first layer conductor is printed on the vertical extension line of the first layer conductor 12 as an electrode on the other side of the thick film resistor 15 by a thick film printing method. A second layer conductor 14 is formed on the insulating layer 13 so as to correspond to the second layer conductor 12 .

つぎに、第4図dの第4工程に示す如く、厚膜
抵抗体15を、厚膜印刷法により、第1層導体1
2の電極部分12′と第2層導体14の電極部分
に接続するように一体的に全面に被着させる。
Next, as shown in the fourth step in FIG.
The second layer conductor 14 is integrally coated on the entire surface so as to be connected to the second electrode portion 12' and the second layer conductor 14.

つぎに、第5工程として、第4図dの個別厚膜
抵抗体間の中心18にそつて、レーザー光もしく
はダイシングソーによる切断方法によつて、一体
的に全面に被着した部分の厚膜抵抗体15を個別
の厚膜抵抗体15′に分離して、基板上に設けた
第1層導体12と該第1層導体12のたて方向延
長線上で基板上に設けた絶縁層13上の第2層導
体14とを連結してなる個別厚膜抵抗体15′を、
互に隣接して複数個配列した厚膜抵抗体アレイを
製造することができた。
Next, as a fifth step, the thick film of the part that is integrally adhered to the entire surface is cut along the center 18 between the individual thick film resistors shown in FIG. The resistor 15 is separated into individual thick film resistors 15', and the first layer conductor 12 provided on the substrate and the insulating layer 13 provided on the substrate on the vertical extension line of the first layer conductor 12 are separated. An individual thick film resistor 15' formed by connecting the second layer conductor 14 of
It was possible to manufacture a thick film resistor array in which a plurality of thick film resistors were arranged adjacent to each other.

なお上記の切断方法での各個別厚膜抵抗体間の
中心18での切断幅はレーザー光、ダイシングソ
ー共に約20μm程度であつた。又抵抗値の調整を
必要とする場合にはレーザートリミング装置によ
りトリミングが可能である。
In addition, the cutting width at the center 18 between each individual thick film resistor in the above cutting method was about 20 μm for both the laser beam and the dicing saw. Further, if the resistance value needs to be adjusted, trimming can be performed using a laser trimming device.

かくして、本実施例においては以上の構成をと
つたので第1図に示した従来の厚膜抵抗体アレイ
においては隣接の導体間のピツチ4が0.2mm程度
であつたものが、本実施例では第2図に示すピツ
チ20が0.2mm程度であるので、ピツチ21は0.1
mm程度となり、従来の半分程度となり、厚膜抵抗
体アレイの高密度化を構成することが可能となつ
た。
Thus, since this embodiment has the above configuration, the pitch 4 between adjacent conductors was approximately 0.2 mm in the conventional thick film resistor array shown in FIG. Since the pitch 20 shown in Fig. 2 is about 0.2 mm, the pitch 21 is about 0.1 mm.
mm, which is about half of the conventional value, making it possible to construct a high-density thick film resistor array.

(発明の効果) 以上詳細に説明したように厚膜抵抗体アレイの
電極を2層構造とすることにより、厚膜抵抗体の
ピツチを従来のものの半分程度に形成できるの
で、高密度の厚膜抵抗体アレイが形成できるとい
う効果がある。
(Effects of the Invention) As explained in detail above, by forming the electrodes of the thick film resistor array into a two-layer structure, the pitch of the thick film resistors can be formed to about half that of the conventional one. This has the advantage that a resistor array can be formed.

また電極の取り出し方も第1層導体を千鳥状配
置に、第2層導体を絶縁層上としたためどの厚膜
抵抗体の電極も片側は第1層導体、他の側は第2
層導体となるので抵抗値のバラツキを小さくでき
るという効果がある。
In addition, the method of taking out the electrodes is such that the first layer conductor is arranged in a staggered manner and the second layer conductor is placed on the insulating layer, so that the electrode of any thick film resistor has the first layer conductor on one side and the second layer conductor on the other side.
Since it becomes a layered conductor, it has the effect of reducing variations in resistance value.

また本発明は、厚膜抵抗体アレイの電極を2層
構造とし第1層導体を千鳥状配置に第2層導体を
絶縁層上としたため高密度で抵抗値バラツキの小
さい厚膜抵抗体アレイが形成できるので、チツプ
抵抗および厚膜ハイブリツドIC等に利用するこ
とができるという効果がある。
In addition, the present invention has a two-layer structure for the electrodes of the thick film resistor array, with the first layer conductors arranged in a staggered manner and the second layer conductors placed on the insulating layer. Since it can be formed, it has the advantage that it can be used for chip resistors, thick film hybrid ICs, etc.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は従来の厚膜抵抗体アレイの平面図、第
2図は本発明の1実施例の平面図、第3図は第2
図のA−A′の切断図、第4図は本発明の1実施
例の製造方法の説明図である。 1:セラミツク基板、2:電極、3:厚膜抵抗
体、11:セラミツク基板、12:第1層導体、
12′:第1層導体の電極部分、13:絶縁層、
14:第2層導体、15:厚膜抵抗体、15′:
個別厚膜抵抗体、18:個別厚膜抵抗体間の中
心。
Fig. 1 is a plan view of a conventional thick film resistor array, Fig. 2 is a plan view of an embodiment of the present invention, and Fig. 3 is a plan view of a conventional thick film resistor array.
FIG. 4, which is a cutaway view taken along line A-A' in the figure, is an explanatory diagram of a manufacturing method according to an embodiment of the present invention. 1: Ceramic substrate, 2: Electrode, 3: Thick film resistor, 11: Ceramic substrate, 12: First layer conductor,
12': electrode part of first layer conductor, 13: insulating layer,
14: Second layer conductor, 15: Thick film resistor, 15':
Individual thick film resistor, 18: Center between individual thick film resistors.

Claims (1)

【特許請求の範囲】 1 厚膜抵抗体とその電極導体を厚膜印刷法によ
り基板上に形成するようにした厚膜抵抗体アレイ
において、 基板上に2列に設けられた複数の第1層導体
と、該第1層導体の端部を除くその他の部分上及
び、前記第1層導体のそれぞれの列方向に沿つた
前記各第1層導体と隣接する基板表面の所定部分
上に少なくとも設けられた絶縁層と、 基板表面の前記所定部分上の前記絶縁層上に設
けられ、且つ、前記各第1層導体と所定の距離を
もつて相対向して設けられた複数の第2層導体
と、 相対向する前記各第1層導体と、絶縁層上の前
記各第2層導体とを連結するように設けられた複
数の厚膜抵抗体とを備え、 前記第1層導体及び絶縁層上の前記第2層導体
がともに千鳥状に配列され、且つ前記第1層導体
と絶縁層上の前記第2層導体とが互いに隣接して
横方向に交互に配列される構成としたことを特徴
とする厚膜抵抗体アレイ。 2 基板上に厚膜抵抗体とその電極を厚膜印刷法
により形成するようにした厚膜抵抗体アレイの製
造方法において、複数の第1層導体を基板上に千
鳥状に2列に配列するようにした第1工程と、 つぎに、前記の複数の第1層導体の端部に露出
部分を設けるとともに、その他の部分の上面に絶
縁層を被着するようにした第2工程と、 つぎに、前記の複数の第1層導体の夫々のたて
方向延長線上の所定の距離の前記絶縁層上に、第
2層導体を設けるようにした第3工程と、 つぎに、前記の複数の第1層導体の端部と、前
記第2層導体の端部とが連結されるよう厚膜抵抗
体を一体的に被着するようにした第4工程と、 つぎに、レーザー光もしくは、ダイシングソー
による切断方法により、前記厚膜抵抗体を個別の
抵抗体に分離形成する第5工程とからなる厚膜抵
抗体アレイの製造方法 3 前記絶縁層が、前記第1層導体のそれぞれの
列対応に帯状に被着されることを特徴とする特許
請求の範囲第2項記載の厚膜抵抗体アレイの製造
方法。
[Claims] 1. A thick film resistor array in which thick film resistors and their electrode conductors are formed on a substrate by a thick film printing method, including a plurality of first layers provided in two rows on the substrate. Provided at least on the conductor and other parts other than the ends of the first layer conductor, and on a predetermined portion of the substrate surface adjacent to each of the first layer conductors along the column direction of each of the first layer conductors. a plurality of second layer conductors provided on the insulating layer on the predetermined portion of the substrate surface and facing each of the first layer conductors at a predetermined distance; and a plurality of thick film resistors provided to connect each of the first layer conductors facing each other and each of the second layer conductors on an insulating layer, and the first layer conductor and the insulating layer. The second layer conductors on the top are both arranged in a staggered manner, and the first layer conductors and the second layer conductors on the insulating layer are arranged adjacent to each other and alternately in the lateral direction. Features a thick film resistor array. 2. In a method for manufacturing a thick film resistor array in which thick film resistors and their electrodes are formed on a substrate by a thick film printing method, a plurality of first layer conductors are arranged in two staggered rows on the substrate. a first step in which exposed portions are provided at the ends of the plurality of first layer conductors, and an insulating layer is deposited on the upper surfaces of the other portions; a third step of providing a second layer conductor on the insulating layer at a predetermined distance on the vertical extension line of each of the plurality of first layer conductors; A fourth step of integrally depositing a thick film resistor so that the end of the first layer conductor and the end of the second layer conductor are connected; and then laser beam or dicing. 3. Method 3 of manufacturing a thick film resistor array, comprising a fifth step of separating and forming the thick film resistor into individual resistors by cutting with a saw. The insulating layer corresponds to each column of the first layer conductor. 3. The method of manufacturing a thick film resistor array according to claim 2, wherein the thick film resistor array is deposited in a strip shape.
JP58079329A 1983-05-09 1983-05-09 Thick film resistor array and method of producing same Granted JPS59204201A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58079329A JPS59204201A (en) 1983-05-09 1983-05-09 Thick film resistor array and method of producing same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58079329A JPS59204201A (en) 1983-05-09 1983-05-09 Thick film resistor array and method of producing same

Publications (2)

Publication Number Publication Date
JPS59204201A JPS59204201A (en) 1984-11-19
JPH0430161B2 true JPH0430161B2 (en) 1992-05-21

Family

ID=13686841

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58079329A Granted JPS59204201A (en) 1983-05-09 1983-05-09 Thick film resistor array and method of producing same

Country Status (1)

Country Link
JP (1) JPS59204201A (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6453506A (en) * 1987-08-25 1989-03-01 Rohm Co Ltd Manufacture of printed circuit

Also Published As

Publication number Publication date
JPS59204201A (en) 1984-11-19

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