JPH09115706A - Manufacture of chip resistor - Google Patents

Manufacture of chip resistor

Info

Publication number
JPH09115706A
JPH09115706A JP7269576A JP26957695A JPH09115706A JP H09115706 A JPH09115706 A JP H09115706A JP 7269576 A JP7269576 A JP 7269576A JP 26957695 A JP26957695 A JP 26957695A JP H09115706 A JPH09115706 A JP H09115706A
Authority
JP
Japan
Prior art keywords
resistor
surface electrode
insulating substrate
chip resistor
chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7269576A
Other languages
Japanese (ja)
Inventor
Zenichi Tamaki
善一 玉木
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Rohm Co Ltd
Original Assignee
Rohm Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Rohm Co Ltd filed Critical Rohm Co Ltd
Priority to JP7269576A priority Critical patent/JPH09115706A/en
Publication of JPH09115706A publication Critical patent/JPH09115706A/en
Pending legal-status Critical Current

Links

Abstract

PROBLEM TO BE SOLVED: To provide a methode for manufacturing a chip resistor having a structure not affected by the displacement between electrodes and resistor elements. SOLUTION: First, plural surface-mount electrode arrays 2 are formed on a large-sized insulating substrate 1. Secondly, plural resistor elements 3 are so formed that they bridges the plural surface-mount electrode arrays 2. And lastly, scribed grooves 4 are formed in the plural surface-mount electrode arrays 2 so that they may scribe unit areas 5 which correspond to the resistor elements 3.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【発明の属する技術分野】本発明はチップ型抵抗器の製
造方法に関し、詳しくはチップ型抵抗器の表面電極の形
成方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a chip resistor, and more particularly to a method for forming a surface electrode of a chip resistor.

【0002】[0002]

【従来の技術】従来のチップ型抵抗器は、図3にその工
程を示す製造方法により製造されている。 先ず、表面にブレーキング用の縦横のスクライブ溝
11を型押し等により格子状に形成したアルミナ等より
なる基板を焼成して絶縁基板12を得ている。(図3
(a)) 次に、絶縁基板12の表面に形成された格子状のス
クライブ溝11により区画される複数の単位領域13毎
に銀、パラジウムを含む導電性ペーストを印刷及び焼成
して表面電極14を形成している。この表面電極14は
各単位領域13内で対向するように、スクライブ溝11
のうちの横方向の溝を横断しないように、且つ縦方向の
溝を横断する如く形成されている。(図3(b)) 更に、表面電極14に対応する基板裏面の位置に裏面の
電極(図示せず)を同様に印刷及び焼成して形成してい
る。 次に、各単位領域13毎の表面電極14の間に、縦
方向に隣接する単位領域13の抵抗体と電気的に絶縁す
るように、それぞれ抵抗体15を印刷及び焼成して形成
している。(図3(c)) そして、単位領域13毎の各抵抗体15を覆うよう
にガラス保護膜を印刷及び焼成した後、形成した各抵抗
体15の抵抗値をトリミング等により調整し、特公昭6
3−32602号公報や、実公平3−56004号公報
に記載されているような基板分割装置を使用して絶縁基
板12をスクライブ溝11に沿って押圧し、単位領域1
3毎にブレーキングして個別にチップ化された抵抗素子
基板を得ている。(図示せず) この後、各チップ化された絶縁基板に表面の電極14と
裏面の電極を接続するように側面電極を形成してチップ
型抵抗器を製造している。
2. Description of the Related Art A conventional chip resistor is manufactured by a manufacturing method whose process is shown in FIG. First, an insulating substrate 12 is obtained by firing a substrate made of alumina or the like on the surface of which vertical and horizontal scribe grooves 11 for braking are formed in a lattice shape by embossing or the like. (Fig. 3
(A)) Next, a conductive paste containing silver and palladium is printed and fired on each of the plurality of unit regions 13 defined by the grid-shaped scribe grooves 11 formed on the surface of the insulating substrate 12, and the surface electrode 14 is then printed. Is formed. The surface electrodes 14 face each other in each unit area 13 so that the scribe groove 11 is formed.
Of these, it is formed so as not to cross the lateral groove and to cross the longitudinal groove. (FIG. 3B) Further, an electrode (not shown) on the back surface is similarly formed by printing and firing at a position on the back surface of the substrate corresponding to the front surface electrode 14. Next, the resistors 15 are formed between the surface electrodes 14 of the respective unit regions 13 by printing and firing so as to be electrically insulated from the resistors of the unit regions 13 adjacent in the vertical direction. . (FIG. 3C) Then, after printing and baking a glass protective film so as to cover each resistor 15 in each unit region 13, the resistance value of each resistor 15 formed is adjusted by trimming or the like, and 6
The insulating substrate 12 is pressed along the scribed groove 11 by using a substrate dividing device as described in Japanese Utility Model Publication No. 3-32602 or Japanese Utility Model Publication No. 3-56004.
The resistance element substrates are individually broken into chips by braking every three. After that, side surface electrodes are formed so as to connect the electrodes 14 on the front surface and the electrodes on the back surface to each of the chipped insulating substrates to manufacture a chip resistor.

【0003】[0003]

【発明が解決しようとする課題】近年、電子技術の進歩
につれて抵抗値の高精度なチップ型抵抗器が要求される
ようになってきている。しかしながら、上述のチップ型
抵抗器の製造方法では、表面電極14が横方向のスクラ
イブ溝に跨らないように形成され、その後に抵抗体15
の形成が別の工程で行われているので、表面電極14及
び抵抗体15の工程での印刷に用いられるスクリーンの
誤差や、絶縁基板に対するスクリーンの位置決めのずれ
により、表面電極14と抵抗体15は相対的な位置ズレ
が生じ易い。
In recent years, as electronic technology has advanced, a chip resistor having a high resistance value has been required. However, in the above-described method for manufacturing the chip resistor, the surface electrode 14 is formed so as not to straddle the lateral scribe groove, and then the resistor 15 is formed.
Is formed in a separate step, the surface electrode 14 and the resistor 15 may be misaligned due to an error in the screen used for printing in the step of forming the surface electrode 14 and the resistor 15 and a misalignment of the screen with respect to the insulating substrate. Is likely to cause relative displacement.

【0004】それにより、図4に示すように表面電極1
4と抵抗体15の重なる面積にばらつきが生じ、各単位
領域13の抵抗体15の抵抗値のばらつきが大きくなっ
てしまい、トリミングに要する手間が増加するだけでな
く、絶縁基板12上で表面電極14と抵抗体15との間
に幅方向にずれが生じた場合には、トリミングを行って
も抵抗値を所望の範囲に調整することが不可能な場合も
発生してしまうおそれがあった。
As a result, as shown in FIG. 4, the surface electrode 1
4 and the resistor 15 vary in the overlapping area, and the resistance value of the resistor 15 in each unit region 13 varies greatly, which not only increases the time and effort required for trimming, but also increases the surface electrode on the insulating substrate 12. If a shift occurs in the width direction between the resistor 14 and the resistor 15, there is a possibility that the resistance value cannot be adjusted to a desired range even if trimming is performed.

【0005】本発明は、上述の問題に鑑み表面電極と抵
抗体の位置ズレの影響をより受けにくい構造にしたチッ
プ型抵抗器の製造方法を提供することを目的とする。
In view of the above problems, it is an object of the present invention to provide a method of manufacturing a chip resistor having a structure that is less susceptible to the positional deviation between the surface electrode and the resistor.

【0006】[0006]

【課題を解決するための手段】前述の問題点を解決する
ために、本願の請求項1に記載した発明は、チップ型抵
抗器の製造方法に関し、大判の絶縁基板の表面に複数の
表面電極列を形成する工程と、前記複数の表面電極列の
間を橋絡するように複数の抵抗体を形成する工程と、前
記抵抗体に対応する単位領域を画成するように前記複数
の表面電極列にスクライブ溝を形成する工程を有するこ
とを特徴とする。
In order to solve the above-mentioned problems, the invention described in claim 1 of the present application relates to a method of manufacturing a chip type resistor, and a plurality of surface electrodes are provided on the surface of a large-sized insulating substrate. Forming a row, forming a plurality of resistors so as to bridge between the plurality of surface electrode rows, and the plurality of surface electrodes so as to define a unit region corresponding to the resistors It is characterized by having a step of forming scribed grooves in the rows.

【0007】[0007]

【発明の実施の形態】以下本発明のチップ型抵抗器の製
造方法を図1を用いて説明する。 スクライブ溝の形成されていないアルミナよりなる
大判の絶縁基板1の一方の面に、複数の表面電極列2を
銀、パラジウムを含むペーストを印刷及び焼成して形成
する。(図1(a)) この表面電極列2は後述のように複数の抵抗体を接続す
るために、平面視で帯状(図中で縦長)に形成する。 次に、対向する表面電極列2間を橋絡するように
(図中で横方向に)酸化ルテニウムを含むペーストを印
刷及び焼成して抵抗体3を複数、矩形状に形成する。
(図1(b)) 次に、ダイヤモンドブレードを有するダイシング装
置により絶縁基板1の表面にスクライブ溝4を格子状に
形成することにより表面電極列2を分離すると共に複数
の単位領域5を画成する。
DETAILED DESCRIPTION OF THE INVENTION A method of manufacturing a chip resistor according to the present invention will be described below with reference to FIG. A plurality of front surface electrode rows 2 are formed by printing and firing a paste containing silver and palladium on one surface of a large-sized insulating substrate 1 made of alumina in which scribed grooves are not formed. (FIG. 1A) The surface electrode array 2 is formed in a strip shape (longitudinal in the figure) in plan view in order to connect a plurality of resistors as described later. Next, a paste containing ruthenium oxide is printed and fired so as to bridge between the front surface electrode rows 2 facing each other (in the horizontal direction in the drawing) to form a plurality of resistors 3 in a rectangular shape.
(FIG. 1B) Next, the scribe grooves 4 are formed in a lattice pattern on the surface of the insulating substrate 1 by a dicing device having a diamond blade to separate the surface electrode rows 2 and define a plurality of unit regions 5. To do.

【0008】このように画成された各単位領域5はその
中央に形成された一つの抵抗体と、この抵抗体3を挟ん
で対向するように接続された表面電極2’とを有する。
これらの表面電極2’は表面電極列2を絶縁基板1の
表面に格子状に形成したスクライブ溝4により分離され
て各単位領域5毎に長手横方向に対向し、幅方向に相互
に独立するように形成されている。(図1(c)) これらのスクライブ溝4の形成深さは単位領域5を画成
する縦横方向のいずれか一方を絶縁基板1の厚さ寸法の
半分程度まで切断し、他方を絶縁基板1の厚さ寸法の全
体を切断するように形成しても良い。つまり、絶縁基板
1にスリットが部分的に形成されるようにスクライブし
ても良い。
Each unit region 5 thus defined has one resistor formed in the center thereof and a surface electrode 2'connected so as to face each other with the resistor 3 interposed therebetween.
These surface electrodes 2'are separated from each other by the scribe grooves 4 formed on the surface of the insulating substrate 1 in a grid pattern on the surface of the insulating substrate 1 so as to oppose each unit region 5 in the longitudinal and lateral directions and to be independent from each other in the width direction. Is formed. (FIG. 1C) The formation depth of these scribed grooves 4 is obtained by cutting one of the vertical and horizontal directions that define the unit region 5 to about half the thickness of the insulating substrate 1 and cutting the other one. You may form so that the whole thickness dimension of may be cut. That is, the scribe may be performed so that the slits are partially formed in the insulating substrate 1.

【0009】又、スクライブ溝4の幅は後述の工程で単
位領域5毎にチップ化するときのブレーキング溝を兼ね
ているので、従来の基板に形成されていたブレーキング
溝の幅と同様に形成すれば良い。 次に、各単位領域5に分離された各抵抗体3上にト
リミングが施される領域が覆われるように、第1保護層
6を硼硅酸鉛ガラスを含むガラスグレーズ系ペーストを
印刷及び焼成して形成する。(図1(d)) 次に、抵抗体3を第1保護層6を介して、レーザー
トリミングすることによりトリミング溝7を形成して抵
抗値の調整をする。(図1(e)) 次に、トリミング溝7と共に抵抗体3及び第1保護
層6を覆うように、第2保護層をエポキシ系樹脂を印刷
しこれを加熱して硬化させて形成し、この後、従来と同
様に絶縁基板をスクライブ溝4で単位領域5毎に分割
し、対向する表裏面電極間を接続する側面電極を形成し
てチップ型抵抗器を製造する。(図示せず) この実施例において、複数の表面電極列2は第1保護層
6を形成する前に表面電極2’に分離したが、各抵抗体
3の抵抗値を測定する前であればいつでもよく特に第1
保護層6を形成する前に限定されるものではなく、図1
(c)のプロセスは図1(a)の後で、且つ図1(e)
の前であれば何処で行っても良い。
Further, since the width of the scribe groove 4 also serves as a braking groove when chips are formed for each unit area 5 in a process described later, it is similar to the width of the braking groove formed on the conventional substrate. It should be formed. Next, the first protective layer 6 is printed and fired with a glass glaze paste containing lead borosilicate glass so that the regions to be trimmed are covered on the resistors 3 separated into the unit regions 5. To form. (FIG. 1D) Next, the resistor 3 is laser-trimmed through the first protective layer 6 to form a trimming groove 7 to adjust the resistance value. (FIG. 1E) Next, a second protective layer is formed by printing an epoxy resin and heating and curing it so as to cover the resistor 3 and the first protective layer 6 together with the trimming groove 7. After that, the insulating substrate is divided into the unit regions 5 by the scribe groove 4 as in the conventional case, and the side surface electrodes that connect the opposed front and back electrodes are formed to manufacture the chip resistor. (Not shown) In this embodiment, the plurality of front surface electrode rows 2 are separated into front surface electrodes 2 ′ before forming the first protective layer 6, but if the resistance value of each resistor 3 is not measured. Always well especially first
It is not limited before forming the protective layer 6,
The process of (c) follows the process of FIG. 1 (a), and FIG.
You can go anywhere before.

【0010】又、この実施例では表面電極列2を分離す
るスクライブをダイヤモンドブレード有するダイシング
装置により行ったが、トリミング溝の幅寸法が確保でき
るものであればとくにダイヤモンドブレードに限定され
るものではなく、ワイヤーを用いたダイシング装置を用
いても若しくはレーザーカッターを用いても良い。尚、
本発明は前述の実施例に記載の内容の材料、構造等に特
に限定されるものではない。
Further, in this embodiment, the scribing for separating the front surface electrode array 2 is performed by the dicing device having the diamond blade, but it is not particularly limited to the diamond blade as long as the width dimension of the trimming groove can be secured. A dicing device using a wire or a laser cutter may be used. still,
The present invention is not particularly limited to the materials, structures, etc. described in the above embodiments.

【0011】[0011]

【発明の効果】本発明のような構成を採ることにより、
絶縁基板の端縁部分の表面の幅方向を全体的に覆うよう
に表面電極が対向状に形成された形状で抵抗体と接続さ
れたチップ型抵抗器が製造される。それにより、抵抗体
の形成位置にズレが生じた場合であっても抵抗体と表面
電極との重なる面積は一定となり、分割形成されたチッ
プ型抵抗器の抵抗値のばらつきを防止でき、トリミング
作業の効率化が図れるだけでなく、チップ型抵抗器の長
手方向(図2に示すX方向)に極端なズレが生じた場合
であっても、絶縁基板の端縁部分で基板表面が露出する
ことがないので、抵抗体が表面電極に重ならなくなりト
リミングをしても抵抗体の抵抗値の調整が不可能になる
ことを防止できるという効果を有する。
By adopting the configuration as in the present invention,
A chip-type resistor is manufactured in which surface electrodes are formed so as to face each other so as to entirely cover the surface of the edge portion of the insulating substrate in the width direction, and the chip resistor is connected to the resistor. As a result, the overlapping area of the resistor and the surface electrode becomes constant even if the position where the resistor is formed is deviated, and it is possible to prevent variations in the resistance value of the chip-type resistors that are divided and formed. Not only can the efficiency of the chip be improved, but the substrate surface must be exposed at the edge of the insulating substrate even if there is an extreme misalignment in the longitudinal direction of the chip resistor (X direction shown in FIG. 2). Since the resistor does not overlap the front surface electrode, it is possible to prevent the resistance value of the resistor from becoming impossible to adjust even after trimming.

【0012】又、本発明の製造方法により製造されたチ
ップ型抵抗器は、その抵抗体に接続された対向状の表面
電極が絶縁基板の端縁部分の表面の幅方向を全体的に覆
うように形成されている。それにより、製造工程で表面
電極に対して抵抗体が幅方向(図2に示すY方向)にず
れて形成された場合であっても、抵抗体と表面電極との
重なる面積は変わることなく、従ってチップ型抵抗器の
抵抗値が常にほぼ一定となるという効果を有する。
Further, in the chip resistor manufactured by the manufacturing method of the present invention, the opposing surface electrodes connected to the resistor cover the entire width direction of the surface of the edge portion of the insulating substrate. Is formed in. As a result, even when the resistor is formed in the width direction (Y direction shown in FIG. 2) with respect to the surface electrode in the manufacturing process, the overlapping area of the resistor and the surface electrode does not change, Therefore, there is an effect that the resistance value of the chip type resistor is always almost constant.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明のチップ型抵抗器の製造方法を示す説明
FIG. 1 is an explanatory view showing a method for manufacturing a chip resistor according to the present invention.

【図2】本発明のチップ型抵抗器の表面電極と抵抗体と
の位置関係を示す平面図
FIG. 2 is a plan view showing a positional relationship between a surface electrode and a resistor of the chip resistor of the present invention.

【図3】従来のチップ型抵抗器の製造方法を示す説明図FIG. 3 is an explanatory view showing a method of manufacturing a conventional chip resistor.

【図4】従来のチップ型抵抗器の表面電極と抵抗体間の
ズレを示す平面図
FIG. 4 is a plan view showing a deviation between a surface electrode and a resistor of a conventional chip resistor.

【符号の説明】[Explanation of symbols]

1・・・・絶縁基板 2・・・・表面電極列 3・・・・抵抗体 4・・・・スクライブ溝 5・・・・単位領域 6・・・・第1保護層 7・・・・トリミング溝 1 ... Insulating substrate 2 ... Surface electrode array 3 ... Resistor 4 ... Scribing groove 5 ... Unit area 6 ... First protective layer 7 ... Trimming groove

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 大判の絶縁基板の表面に複数の表面電極
列を形成する工程と、 前記複数の表面電極列の間を橋絡するように複数の抵抗
体を形成する工程と、 前記抵抗体に対応する単位領域を画成するように前記複
数の表面電極列にスクライブ溝を形成する工程を有する
ことを特徴とするチップ型抵抗器の製造方法。
1. A step of forming a plurality of front surface electrode rows on the surface of a large-sized insulating substrate, a step of forming a plurality of resistor bodies so as to bridge the plurality of front surface electrode rows, and the resistor body. And a step of forming scribed grooves in the plurality of front surface electrode rows so as to define a unit area corresponding to.
JP7269576A 1995-10-18 1995-10-18 Manufacture of chip resistor Pending JPH09115706A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7269576A JPH09115706A (en) 1995-10-18 1995-10-18 Manufacture of chip resistor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7269576A JPH09115706A (en) 1995-10-18 1995-10-18 Manufacture of chip resistor

Publications (1)

Publication Number Publication Date
JPH09115706A true JPH09115706A (en) 1997-05-02

Family

ID=17474294

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7269576A Pending JPH09115706A (en) 1995-10-18 1995-10-18 Manufacture of chip resistor

Country Status (1)

Country Link
JP (1) JPH09115706A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006140430A (en) * 2004-10-12 2006-06-01 Shin Etsu Polymer Co Ltd Conduction noise suppressor and electronic component with conduction noise suppressor
WO2012070336A1 (en) * 2010-11-22 2012-05-31 Tdk株式会社 Chip thermistor and thermistor assembly board

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006140430A (en) * 2004-10-12 2006-06-01 Shin Etsu Polymer Co Ltd Conduction noise suppressor and electronic component with conduction noise suppressor
JP4611758B2 (en) * 2004-10-12 2011-01-12 信越ポリマー株式会社 Conductive noise suppressor and electronic component with conductive noise suppressor
WO2012070336A1 (en) * 2010-11-22 2012-05-31 Tdk株式会社 Chip thermistor and thermistor assembly board
US9076576B2 (en) 2010-11-22 2015-07-07 Tdk Corporation Chip thermistor and thermistor assembly board
JP5778690B2 (en) * 2010-11-22 2015-09-16 Tdk株式会社 Chip thermistor and thermistor assembly board

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