JP4227821B2 - Manufacturing method of chip resistor - Google Patents

Manufacturing method of chip resistor Download PDF

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Publication number
JP4227821B2
JP4227821B2 JP2003080492A JP2003080492A JP4227821B2 JP 4227821 B2 JP4227821 B2 JP 4227821B2 JP 2003080492 A JP2003080492 A JP 2003080492A JP 2003080492 A JP2003080492 A JP 2003080492A JP 4227821 B2 JP4227821 B2 JP 4227821B2
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groove
resistor
divided
ceramic substrate
primary
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JP2004288968A (en
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健太郎 松本
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Koa Corp
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Koa Corp
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Description

【0001】
【発明の属する技術分野】
本発明は、大判のセラミック基板を格子状に延びる複数本の一次分割溝および二次分割溝に沿って分割することで多数個取りされるチップ抵抗器の製造方法に関する。
【0002】
【従来の技術】
この種のチップ抵抗器の製造方法として知られている従来例を図5を参照して説明すると、まず、図5(a)に示すように、大判のセラミック基板20の上面に縦横の格子状に延びる複数本の一次分割溝21および二次分割溝22を形成する。これらの分割溝21,22は、セラミック基板20の焼成前に型押し等によって形成してもよいし、焼成後のセラミック基板20にレーザスクライブやダイシング等によって形成してもよい。次に、図5(b)に示すように、隣り合う二次分割溝22どうしの間で一次分割溝21を跨ぐ位置にそれぞれ上面電極(表面電極)23を形成する。同様に、セラミック基板20の下面で上面電極23と対応する領域にそれぞれ図示せぬ下面電極(裏面電極)を形成する。次いで、図5(c)に示すように、セラミック基板20の上面で縦横の分割溝21,22に囲まれた各領域内に、両端部が上面電極23と重なり合うように抵抗体24を形成する。こうしてセラミック基板20上に分散して配置された各抵抗体24は、その両端の上面電極23にプローブを接触させるなどして抵抗値を測定できるので、所望の抵抗値となるようにトリミングされる。この後、図5(d)に示すように、各抵抗体24をオーバーコート層25によって被覆してから、セラミック基板20を一次分割溝21に沿ってブレイクして短冊状分割片26となす。そして、短冊状分割片26の長手方向に沿う両側面に図示せぬ端面電極を形成した後、この短冊状分割片26を二次分割溝22に沿ってブレイクして図示せぬ個々のチップ単体となし、これらチップ単体の電極部分をめっき処理することにより、完成品である図示せぬチップ抵抗器を多数個一括して製造することができる。
【0003】
しかしながら、このようにして製造されるチップ抵抗器の小型化が促進されると、大判のセラミック基板20上にそれぞれ異なるマスクを用いてスクリーン印刷される上面電極23と抵抗体24とが位置ずれを起こしやすくなるため、縦横の分割溝21,22に囲まれた各領域内で上面電極23と抵抗体24とが重なり合う面積が大きくばらついてしまい、それゆえ各抵抗体24のトリミング作業が煩雑化して生産性が悪化するという問題が発生する。
【0004】
そこで、他の従来例として、大判のセラミック基板上に、直線状に延びる縞状に配列された複数の帯状電極と、隣り合う帯状電極間を橋絡する複数の抵抗体とを形成した後に、縦横の格子状に延びる複数本の分割溝をダイシングやレーザスクライブで形成するというチップ抵抗器の製造方法が提案されている(例えば、特許文献1参照)。
【0005】
この場合において、一次分割溝は各帯状電極の幅方向略中央を通過して長手方向に延びるように形成され、二次分割溝は複数の帯状電極を幅方向に沿って横断して各帯状電極を複数の上面電極に分割するように形成される。このようにすると、縦横の分割溝に囲まれた各領域の両側部には必ず上面電極が存在することになるので、上面電極と抵抗体とが多少の位置ずれを起こしたとしても、各領域内で上面電極と抵抗体とが重なり合う面積はほぼ一定となって抵抗値のばらつきが抑えられ、それゆえ各抵抗体のトリミング作業を効率よく行うことができて生産性の向上が期待できる。
【0006】
【特許文献1】
特開平9−115706号公報(第2〜3頁、図1)
【0007】
【発明が解決しようとする課題】
上述した従来例のように、大判のセラミック基板上に帯状電極と抵抗体とを形成した後に分割溝を形成するという手法を採用すると、チップ抵抗器の小型化が促進されても抵抗値のばらつきが抑えられるため、各抵抗体のトリミング作業が効率化されるという利点を有するが、その反面、帯状電極に縦横の分割溝を刻設する際に生じる残渣が該分割溝内に滞留して短絡要因となりやすいため、トリミングに先立つ抵抗値の測定を正確に行えなくなってしまう危険性があった。すなわち、ダイヤモンドブレード等を用いて行われるダイシングであれレーザ光を照射して行われるレーザスクライブであれ、帯状電極に分割溝を刻設する際には、電極材料である残渣が該分割溝内に若干量滞留するので、チップ抵抗器の小型化に伴って分割溝が幅狭になると、分割溝を介して絶縁されたはずの隣接する上面電極どうしが、導電性の残渣をブリッジとして短絡されてしまう可能性が高まる。そのため、製造されたチップ抵抗器の抵抗値に誤差が生じやすくなり、高信頼性が得にくいという問題があった。
【0008】
本発明は、このような従来技術の実情に鑑みてなされたもので、その目的は、生産性が良好で高信頼性も確保しやすいチップ抵抗器の製造方法を提供することにある。
【0009】
【課題を解決するための手段】
上述した目的を達成するために、本発明によるチップ抵抗器の製造方法では、多数個分のチップ抵抗器に対応する大判のセラミック基板の表面に所定の間隔を存して直線状に延びる複数の一次分割溝を形成する一次分割溝形成工程と、前記セラミック基板の表面に幅方向中央を通過して長手方向に延びる二等分線が前記一次分割溝と略合致するように複数の帯状電極を形成する帯状電極形成工程と、前記各帯状電極を複数の上面電極に分割するように、前記セラミック基板の表面に前記一次分割溝と直交するように所定の間隔を存して直線状に延びる複数の二次分割溝を形成する二次分割溝形成工程と、前記一次分割溝と直交する方向に沿って隣り合う前記上面電極どうしを橋絡するように複数の抵抗体を形成する抵抗体形成工程と、前記各抵抗体の抵抗値を調整する抵抗体トリミング工程と、前記抵抗体トリミング工程の後に前記セラミック基板を前記一次分割溝および前記二次分割溝に沿って順次ブレイクするブレイク工程とを備え、前記二次分割溝形成工程において、1回目のレーザ光照射で刻設した分割溝に2回目のレーザ光照射を施して前記二次分割溝を形成するようになし、この2回目のレーザ光照射時に1回目のレーザ光照射時よりも幅広で浅い溝を形成することにより、該1回目のレーザ光照射で刻設した分割溝の開口端側に溝奥側よりも傾斜が緩やかな面取り部を形成するようにした。
【0010】
このように各帯状電極を複数の上面電極に分割する二次分割溝を形成する際にレーザスクライブを2回行うという手法を採用すると、1回目のレーザ光照射によって刻設した分割溝内に導電性の残渣が滞留しても、2回目のレーザ光照射によって該残渣は除去されてしまうので、該残渣をブリッジとして上面電極どうしが短絡されてしまう心配がなくなり、トリミングに先立つ各抵抗体の抵抗値測定を常に正確に行うことができる。また、帯状電極を複数の上面電極に分割するという手法なので、縦横の分割溝に囲まれた各領域内で上面電極と抵抗体とが重なり合う面積はほぼ一定となって抵抗値のばらつきが抑えられ、各抵抗体のトリミング作業を効率よく行うことができる。しかも、2回目のレーザ光照射時には1回目のレーザ光照射時よりも幅広で浅い溝が形成されるように設定しておき、該2回目のレーザ光照射によって、該1回目のレーザ光照射で刻設した分割溝の開口端側に溝奥側よりも傾斜が緩やかな面取り部を形成するようにしたので、1回目のレーザ光照射によって分割溝に隣接する帯状電極やセラミック基板が若干脆くなったとしても、この脆弱部分を2回目のレーザ光照射によって除去することができ、製造されたチップ抵抗器のエッジ部分に欠けが生じにくくなる。それゆえ、抵抗値の誤差が少ない高信頼性のチップ抵抗器を効率よく製造することが可能となる。
【0011】
かかる製造方法において、一次分割溝は二次分割溝と同様にレーザスクライブによって形成してもよいが、セラミック基板の焼成前に型押しを行うなどして形成してもよい。ただし、一次分割溝に沿ってブレイクして露出するセラミック基板の端面が上面電極と接続される端面電極の形成面であることを考慮すると、帯状電極形成工程は一次分割溝形成工程の後に行うことが好ましい。
【0013】
【発明の実施の形態】
以下、発明の実施の形態について図面を参照して説明すると、図1,2は本実施形態例に係るチップ抵抗器の製造方法を工程順に示す説明図であり、図1は二次分割溝を形成するまでの工程を示し、図2は抵抗体を形成した後の工程を示している。また、図3は該チップ抵抗器の完成品の断面図、図4は図1(d)のA−A線に沿う要部断面図である。
【0014】
まず、図3に示すチップ抵抗器10の構成について説明する。このチップ抵抗器10にあっては、アルミナ等からなるセラミック基体11の上面に、抵抗体12と該抵抗体12の両端部に重なり合う一対の上面電極13とが設けられていると共に、保護膜として、抵抗体12を覆うガラスコート層14と該ガラスコート層14を覆うオーバーコート層15とが設けられている。セラミック基体11の下面には上面電極13と対応する領域に一対の下面電極16が設けられており、また、セラミック基体11の長手方向両端面にはそれぞれ上面電極13と下面電極16とを橋絡する端面電極17が設けられている。これら上面電極13と下面電極16および端面電極17はチップ抵抗器10の下地電極層を構成しており、この下地電極層はニッケルめっき層18と半田めっき層(または錫めっき層)19という2層のめっき層によって被覆されている。
【0015】
このように構成されるチップ抵抗器10の製造方法を図1および図2に基づいて説明すると、まず、アルミナ等からなるグリーンシートを焼成してセラミック基板1を形成する。このセラミック基板1は、後工程で多数個分のチップ抵抗器10のセラミック基体11に分割される大判基板である。そして、このセラミック基板1の上面にレーザ光を照射するレーザスクライブを行って、図1(a)に示すように、所定の間隔を存して直線状に延びる複数本の一次分割溝2を形成する(一次分割溝形成工程)。なお、セラミック基板1の焼成前に型押しを行うなどして一次分割溝2を形成してもよい。
【0016】
次に、セラミック基板1の上面にAgやAg−Pd等のペーストをスクリーン印刷して焼成することにより、図1(b)に示すように、直線状に延びる縞状に配列された複数の帯状電極3を形成する(上面側帯状電極形成工程)。ここで、各帯状電極3は、その幅方向中央を通過して長手方向に延びる二等分線が一次分割溝2と略合致するように設定されている。同様に、セラミック基板1の下面にもAgやAg−Pd等のペーストをスクリーン印刷して焼成することにより、帯状電極3と対応する領域に同形状の図示せぬ帯状電極を形成する(下面側帯状電極形成工程)。これら上下両面の帯状電極はいずれを先に形成してもよい。
【0017】
この後、一次分割溝2に対して直交する向き(帯状電極3を幅方向に横切る向き)に1回目のレーザスクライブを行うことにより、図1(c)に示すように、所定の間隔を存して直線状に延びる複数本の幅狭分割溝4aを形成し、次いで各幅狭分割溝4aをなぞるように2回目のレーザスクライブを行うことにより、図1(d)に示すように、幅狭分割溝4aをやや幅広な二次分割溝4に仕上げる(二次分割溝形成工程)。その際、レーザビームの焦点位置とセラミック基板1との間隔を適宜調整し、2回目のレーザスクライブ時には1回目のレーザスクライブ時よりも幅広で浅い溝が形成されるように設定しておくことにより、図4に示すように、二次分割溝4は開口端側に面取り部4bを有する断面形状となる。つまり、レーザスクライブを2回施すことにより、幅狭分割溝4aの開口端側に溝奥側よりも傾斜が緩やかな面取り部4bが形成され、やや幅広な二次分割溝4に仕上げられる。こうして形成された二次分割溝4は帯状電極3を幅方向に横切って延びているので、この二次分割溝形成工程によって各帯状電極3は複数の上面電極13に分割される。また、1回目のレーザスクライブで刻設した幅狭分割溝4a内には帯状電極3の残渣が滞留している可能性があるが、2回目のレーザスクライブによって該残渣は除去されてしまうので、該残渣をブリッジとして上面電極13どうしが短絡されてしまう心配はない。
【0018】
次に、セラミック基板1の上面に酸化ルテニウム等の抵抗ペーストをスクリーン印刷して焼成することにより、図2(a)に示すように、隣り合う二次分割溝4どうしの間に位置して両端部が上面電極13と重なり合う抵抗体12を複数形成する(抵抗体形成工程)。ただし、この抵抗体形成工程を二次分割溝形成工程や帯状電極形成工程よりも前に実施してもよく、二次分割溝形成工程の1回目のレーザスクライブと2回目のレーザスクライブの途中で抵抗体形成工程を実施することも可能である。
【0019】
次に、セラミック基板1の上面に各抵抗体12を被覆するガラスコート層14をスクリーン印刷、焼成により形成した後、上面電極13に図示せぬプローブを接触させて各抵抗体12の抵抗値を測定し、その測定値に基づいて各抵抗体12をレーザトリミングする。これにより、各抵抗体12は図2(b)に示すトリミング溝5によって抵抗値が調整される(抵抗体トリミング工程)。なお、前述したように、隣接する上面電極13どうしを短絡するような導電性の残渣が二次分割溝4内に存在する可能性は極めて低いため、レーザトリミングに先立つ各抵抗体12の抵抗値の測定は常に正確に行うことができる。
【0020】
次に、セラミック基板1の上面にガラスコート層14およびトリミング溝5を被覆するオーバーコート層15をスクリーン印刷、焼成により形成した後、このセラミック基板1を一次分割溝2に沿ってブレイクすることにより、図2(c)に示すような短冊状分割片6を得る(一次ブレイク工程)。なお、この一次ブレイク工程によって、セラミック基板1の下面側の帯状電極は一次分割溝2に沿って二等分される。しかる後、短冊状分割片6の長手方向に沿う側端面それぞれにNi−Cr等をスパッタすることにより、該側端面に各上面電極13と下面側の帯状電極とを橋絡する端面電極17を形成する(端面電極形成工程)。
【0021】
次に、各短冊状分割片6を二次分割溝4に沿ってブレイクすることにより、図2(d)に示すようなチップ単体7が多数個得られる(二次ブレイク工程)。なお、この二次ブレイク工程によって、下面側の帯状電極が下面電極16に分割されると共に、前記セラミック基体11が形成される。そして、多数個のチップ単体7を一括してめっき処理することにより、前記下地電極層(上面電極13と下面電極16および端面電極17)を被覆する2層構造のめっき層18,19を形成する(めっき層形成工程)。これにより、図3に示すような完成品のチップ抵抗器10を多数個一括して製造することができる。
【0022】
このようにチップ抵抗器10の製造過程で、各帯状電極3を複数の上面電極13に分割する二次分割溝4を形成する際にレーザスクライブを2回行うという手法を採用すると、1回目のレーザ光照射によって刻設した幅狭分割溝4a内に導電性の残渣が滞留しても、2回目のレーザ光照射によって該残渣は除去されてしまうので、該残渣をブリッジとして上面電極13どうしが短絡されてしまう心配がなくなり、トリミングに先立つ各抵抗体12の抵抗値測定を常に正確に行うことができる。そのため、製造されたチップ抵抗器10の抵抗値に誤差が生じにくくなり、その信頼性が向上する。また、このように帯状電極3を二次分割溝4によって複数の上面電極13に分割するという手法を採用すると、セラミック基板1の上面で縦横の分割溝2,4に囲まれた各領域の両側部には必ず上面電極13が存在することになるので、上面電極13と抵抗体12とが多少の位置ずれを起こしたとしても、各領域内で上面電極13と抵抗体12とが重なり合う面積はほぼ一定となって抵抗値のばらつきが抑えられる。そのため、抵抗値を調整するトリミング作業を効率よく行うことができ、生産性の向上が期待できる。
【0023】
また、本実施形態例においては、二次分割溝形成工程で行う2回目のレーザ光照射によって、1回目のレーザ光照射で刻設した幅狭分割溝4aの開口端側に面取り部4bが形成されるので、1回目のレーザ光照射によって幅狭分割溝4aに隣接する帯状電極3やセラミック基板1が若干脆くなったとしても、この脆弱部分を2回目のレーザ光照射によって除去することができる。そのため、製造されたチップ抵抗器10のエッジ部分に欠けが生じにくくなり、自動実装等に支障をきたす心配がない。
【0025】
また、上記実施形態例では、一次分割溝形成工程の後に帯状電極形成工程を実施した場合について説明したが、帯状電極3を形成した後にレーザスクライブ等によって一次分割溝2を形成することも可能である。ただしその場合、帯状電極3は一次分割溝2に隣接して後工程で端面電極17と接続される部分が若干脆くなってしまうので、信頼性の低下を防止するために、一次分割溝形成工程においてもレーザスクライブを2回行って帯状電極3の該脆弱部分を除去しておくことが好ましい。
【0026】
【発明の効果】
本発明は、以上説明したような形態で実施され、以下に記載されるような効果を奏する。
【0027】
チップ抵抗器の製造過程で、各帯状電極を複数の上面電極に分割する二次分割溝を形成する際にレーザスクライブを2回行い、1回目のレーザ光照射によって刻設した分割溝内に導電性の残渣が滞留しても2回目のレーザ光照射によって該残渣が除去できるようにしてあるため、該残渣に起因する上面電極どうしの短絡が確実に防止されることとなり、よってトリミングに先立つ各抵抗体の抵抗値測定を常に正確に行うことができる。また、帯状電極を複数の上面電極に分割するという手法なので、縦横の分割溝に囲まれた各領域内で上面電極と抵抗体とが重なり合う面積はほぼ一定となって抵抗値のばらつきが抑えられ、各抵抗体のトリミング作業を効率よく行うことができる。しかも、2回目のレーザ光照射時には1回目のレーザ光照射時よりも幅広で浅い溝が形成されるように設定しておき、該2回目のレーザ光照射によって、該1回目のレーザ光照射で刻設した分割溝の開口端側に溝奥側よりも傾斜が緩やかな面取り部を形成するようにしたので、1回目のレーザ光照射によって分割溝に隣接する帯状電極やセラミック基板が若干脆くなったとしても、この脆弱部分を2回目のレーザ光照射によって除去することができ、製造されたチップ抵抗器のエッジ部分に欠けが生じにくくなる。それゆえ、抵抗値の誤差が少ない高信頼性のチップ抵抗器を効率よく製造することが可能となる。
【図面の簡単な説明】
【図1】本発明の実施形態例に係るチップ抵抗器の製造過程で二次分割溝を形成するまでの工程を示す説明図である。
【図2】該チップ抵抗器の製造過程で抵抗体を形成した後の工程を示す説明図である。
【図3】該チップ抵抗器の完成品の断面図である。
【図4】図1(d)のA−A線に沿う要部断面図である。
【図5】従来例に係るチップ抵抗器の製造方法を示す説明図である。
【符号の説明】
1 セラミック基板
2 一次分割溝
3 帯状電極
4 二次分割溝
4a 幅狭分割溝
4b 面取り部
5 トリミング溝
6 短冊状分割片
7 チップ単体
10 チップ抵抗器
11 セラミック基体
12 抵抗体
13 上面電極
14 ガラスコート層
15 オーバーコート層
16 下面電極
17 端面電極
18,19 めっき層
[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method of manufacturing a chip resistor in which a large-sized ceramic substrate is obtained by dividing a large-sized ceramic substrate along a plurality of primary division grooves and secondary division grooves extending in a lattice shape.
[0002]
[Prior art]
A conventional example known as a manufacturing method of this type of chip resistor will be described with reference to FIG. 5. First, as shown in FIG. 5A, vertical and horizontal grids are formed on the upper surface of a large-sized ceramic substrate 20. A plurality of primary dividing grooves 21 and secondary dividing grooves 22 extending in a straight line are formed. These dividing grooves 21 and 22 may be formed by embossing or the like before firing of the ceramic substrate 20, or may be formed on the fired ceramic substrate 20 by laser scribing or dicing. Next, as shown in FIG. 5B, upper surface electrodes (surface electrodes) 23 are respectively formed at positions across the primary division grooves 21 between adjacent secondary division grooves 22. Similarly, a lower surface electrode (back surface electrode) (not shown) is formed in a region corresponding to the upper surface electrode 23 on the lower surface of the ceramic substrate 20. Next, as shown in FIG. 5C, the resistor 24 is formed in each region surrounded by the vertical and horizontal dividing grooves 21 and 22 on the upper surface of the ceramic substrate 20 so that both end portions overlap the upper surface electrode 23. . Since the resistance values of the resistors 24 distributed on the ceramic substrate 20 can be measured by bringing the probes into contact with the upper surface electrodes 23 at both ends thereof, they are trimmed so as to have a desired resistance value. . Thereafter, as shown in FIG. 5 (d), each resistor 24 is covered with an overcoat layer 25, and then the ceramic substrate 20 is broken along the primary dividing grooves 21 to form strip-shaped divided pieces 26. Then, after forming end face electrodes (not shown) on both side surfaces along the longitudinal direction of the strip-shaped divided pieces 26, the strip-shaped divided pieces 26 are broken along the secondary divided grooves 22 to form individual chips (not shown). As a result, by plating the electrode portions of these single chips, a large number of chip resistors (not shown) which are finished products can be manufactured at once.
[0003]
However, when miniaturization of the chip resistor manufactured in this way is promoted, the upper surface electrode 23 and the resistor 24, which are screen-printed using different masks on the large-sized ceramic substrate 20, are displaced. Since it easily occurs, the area where the upper surface electrode 23 and the resistor 24 overlap each other in each region surrounded by the vertical and horizontal dividing grooves 21 and 22 greatly varies, and therefore the trimming operation of each resistor 24 becomes complicated. The problem that productivity deteriorates occurs.
[0004]
Therefore, as another conventional example, on a large ceramic substrate, after forming a plurality of strip electrodes arranged in a stripe extending in a straight line and a plurality of resistors bridging between adjacent strip electrodes, There has been proposed a chip resistor manufacturing method in which a plurality of dividing grooves extending in a vertical and horizontal grid pattern are formed by dicing or laser scribing (see, for example, Patent Document 1).
[0005]
In this case, the primary dividing groove is formed so as to extend in the longitudinal direction through substantially the center in the width direction of each band electrode, and the secondary division groove crosses the plurality of band electrodes along the width direction to form each band electrode. Is divided into a plurality of upper surface electrodes. In this case, since the upper surface electrode always exists on both sides of each region surrounded by the vertical and horizontal dividing grooves, even if the upper surface electrode and the resistor are slightly misaligned, In this case, the area where the upper electrode and the resistor overlap each other is almost constant, and variation in resistance value is suppressed. Therefore, the trimming operation of each resistor can be performed efficiently, and improvement in productivity can be expected.
[0006]
[Patent Document 1]
JP-A-9-115706 (pages 2 and 3, FIG. 1)
[0007]
[Problems to be solved by the invention]
As in the conventional example described above, if a method of forming a dividing groove after forming a strip electrode and a resistor on a large ceramic substrate is employed, variation in resistance value is achieved even if chip resistors are reduced in size. Therefore, the trimming work of each resistor is made more efficient, but on the other hand, the residue generated when the vertical and horizontal dividing grooves are engraved in the strip electrode stays in the dividing grooves and is short-circuited. Since it tends to be a factor, there is a risk that the resistance value cannot be accurately measured prior to trimming. That is, whether dicing performed using a diamond blade or laser scribing performed by irradiating a laser beam, when a dividing groove is engraved in a strip electrode, a residue as an electrode material is placed in the dividing groove. When the dividing groove becomes narrower as the chip resistor is reduced in size, the adjacent upper surface electrodes that should have been insulated through the dividing groove are short-circuited with a conductive residue as a bridge. The possibility that it will end up increases. Therefore, there is a problem that an error is likely to occur in the resistance value of the manufactured chip resistor and it is difficult to obtain high reliability.
[0008]
The present invention has been made in view of such a state of the prior art, and an object of the present invention is to provide a method of manufacturing a chip resistor that has good productivity and easily secures high reliability.
[0009]
[Means for Solving the Problems]
In order to achieve the above-described object, in the method of manufacturing a chip resistor according to the present invention, a plurality of linearly extending plurality of chip resistors corresponding to a large number of chip resistors are linearly provided on the surface of the large-sized ceramic substrate. A plurality of strip-like electrodes so that a bisector extending in the longitudinal direction passing through the center in the width direction on the surface of the ceramic substrate substantially coincides with the primary dividing groove; A strip electrode forming step to be formed, and a plurality of strips extending linearly at predetermined intervals on the surface of the ceramic substrate so as to be perpendicular to the primary dividing grooves so as to divide each strip electrode into a plurality of upper surface electrodes. A secondary divided groove forming step for forming the secondary divided groove, and a resistor forming step for forming a plurality of resistors so as to bridge the upper surface electrodes adjacent to each other along a direction orthogonal to the primary divided groove And each of the above A resistor trimming step for adjusting the resistance value of the antibody; and a break step for sequentially breaking the ceramic substrate along the primary dividing groove and the secondary dividing groove after the resistor trimming step, In the groove forming step, the divided grooves formed by the first laser beam irradiation are irradiated with the second laser beam to form the secondary divided grooves, and the first laser beam irradiation is performed during the second laser beam irradiation. By forming a groove that is wider and shallower than that at the time of laser light irradiation, a chamfered portion with a gentler slope than that at the back of the groove is formed on the opening end side of the divided groove formed by the first laser light irradiation. did.
[0010]
When the technique of performing laser scribing twice when forming the secondary divided groove for dividing each strip electrode into a plurality of upper surface electrodes in this way, the conductive material is formed in the divided grooves formed by the first laser beam irradiation. Since the residue is removed by the second laser beam irradiation, there is no fear that the upper surface electrodes are short-circuited by using the residue as a bridge, and the resistance of each resistor prior to trimming is reduced. Value measurement can always be performed accurately. In addition, since the strip electrode is divided into a plurality of upper surface electrodes, the area where the upper surface electrode and the resistor overlap in each region surrounded by the vertical and horizontal dividing grooves is almost constant, thereby suppressing variations in resistance value. The trimming operation of each resistor can be performed efficiently. In addition, a groove that is wider and shallower than that at the first laser light irradiation is set to be formed at the second laser light irradiation, and the first laser light irradiation is performed by the second laser light irradiation. Since the chamfered portion with a gentler slope than the depth side of the groove is formed on the opening end side of the engraved dividing groove, the strip electrode or ceramic substrate adjacent to the dividing groove becomes slightly brittle by the first laser light irradiation. Even so, the fragile portion can be removed by the second laser beam irradiation, and the edge portion of the manufactured chip resistor is less likely to be chipped. Therefore, it is possible to efficiently manufacture a highly reliable chip resistor with little resistance error.
[0011]
In such a manufacturing method, the primary dividing groove may be formed by laser scribing in the same manner as the secondary dividing groove, but may be formed by embossing before firing the ceramic substrate. However, considering that the end face of the ceramic substrate that breaks and is exposed along the primary dividing groove is the forming face of the end face electrode connected to the upper surface electrode, the strip electrode forming step should be performed after the primary dividing groove forming step. Is preferred.
[0013]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIGS. 1 and 2 are explanatory views showing a method of manufacturing a chip resistor according to the present embodiment in order of steps, and FIG. The process until formation is shown, and FIG. 2 shows the process after the resistor is formed. FIG. 3 is a cross-sectional view of the finished chip resistor, and FIG. 4 is a cross-sectional view of a main part taken along line AA in FIG.
[0014]
First, the configuration of the chip resistor 10 shown in FIG. 3 will be described. In this chip resistor 10, a resistor 12 and a pair of upper surface electrodes 13 overlapping both ends of the resistor 12 are provided on the upper surface of a ceramic substrate 11 made of alumina or the like, and as a protective film. A glass coat layer 14 covering the resistor 12 and an overcoat layer 15 covering the glass coat layer 14 are provided. A pair of lower surface electrodes 16 are provided in a region corresponding to the upper surface electrode 13 on the lower surface of the ceramic substrate 11, and the upper surface electrode 13 and the lower surface electrode 16 are bridged on both end surfaces in the longitudinal direction of the ceramic substrate 11. An end face electrode 17 is provided. The upper surface electrode 13, the lower surface electrode 16 and the end surface electrode 17 constitute a base electrode layer of the chip resistor 10, and this base electrode layer has two layers, a nickel plating layer 18 and a solder plating layer (or tin plating layer) 19. It is covered with a plating layer.
[0015]
The manufacturing method of the chip resistor 10 configured as described above will be described with reference to FIGS. 1 and 2. First, the ceramic substrate 1 is formed by firing a green sheet made of alumina or the like. This ceramic substrate 1 is a large-sized substrate that is divided into a large number of ceramic substrates 11 of chip resistors 10 in a later step. Then, laser scribing to irradiate the upper surface of the ceramic substrate 1 with laser light is performed to form a plurality of primary division grooves 2 extending linearly at predetermined intervals as shown in FIG. (Primary division groove forming step). The primary dividing grooves 2 may be formed by embossing before firing the ceramic substrate 1.
[0016]
Next, a paste such as Ag or Ag-Pd is screen-printed on the upper surface of the ceramic substrate 1 and fired to form a plurality of strips arranged in stripes extending linearly as shown in FIG. The electrode 3 is formed (upper surface side strip electrode forming step). Here, each strip electrode 3 is set so that a bisector extending in the longitudinal direction through the center in the width direction substantially coincides with the primary dividing groove 2. Similarly, a strip-shaped electrode (not shown) having the same shape is formed in the region corresponding to the strip-shaped electrode 3 by screen-printing and baking a paste such as Ag or Ag-Pd on the bottom surface of the ceramic substrate 1 (bottom surface side). Strip electrode forming step). Any of these upper and lower strip electrodes may be formed first.
[0017]
Thereafter, by performing the first laser scribing in a direction orthogonal to the primary dividing groove 2 (direction crossing the strip electrode 3 in the width direction), a predetermined interval is maintained as shown in FIG. Then, a plurality of narrow divided grooves 4a extending in a straight line are formed, and then a second laser scribing is performed so as to trace each narrow divided groove 4a. The narrow divided groove 4a is finished into a slightly wider secondary divided groove 4 (secondary divided groove forming step). At that time, the distance between the focal position of the laser beam and the ceramic substrate 1 is adjusted as appropriate, and a groove that is wider and shallower than that at the first laser scribe is formed at the second laser scribe. As shown in FIG. 4, the secondary dividing groove 4 has a cross-sectional shape having a chamfered portion 4b on the opening end side. That is, by performing laser scribing twice, a chamfered portion 4b having a gentler inclination than the groove rear side is formed on the opening end side of the narrow divided groove 4a, and the secondary divided groove 4 having a slightly wider width is finished. Since the secondary divided grooves 4 formed in this way extend across the band-shaped electrode 3 in the width direction, each band-shaped electrode 3 is divided into a plurality of upper surface electrodes 13 by this secondary divided groove forming step. Further, there is a possibility that the residue of the strip-shaped electrode 3 stays in the narrow dividing groove 4a carved by the first laser scribe, but the residue is removed by the second laser scribe. There is no fear that the upper surface electrodes 13 are short-circuited by using the residue as a bridge.
[0018]
Next, a resistance paste such as ruthenium oxide is screen-printed on the upper surface of the ceramic substrate 1 and baked, thereby being positioned between adjacent secondary divided grooves 4 as shown in FIG. A plurality of resistors 12 whose portions overlap with the upper surface electrode 13 are formed (resistor forming step). However, this resistor forming step may be performed before the secondary divided groove forming step or the strip electrode forming step, and during the first laser scribe and the second laser scribe in the secondary divided groove forming step. It is also possible to perform a resistor forming step.
[0019]
Next, after a glass coat layer 14 for covering each resistor 12 is formed on the upper surface of the ceramic substrate 1 by screen printing and firing, a probe (not shown) is brought into contact with the upper surface electrode 13 to determine the resistance value of each resistor 12. Measurement is performed, and each resistor 12 is laser trimmed based on the measured value. Thereby, the resistance value of each resistor 12 is adjusted by the trimming groove 5 shown in FIG. 2B (resistor trimming step). As described above, since there is a very low possibility that a conductive residue that short-circuits the adjacent upper surface electrodes 13 exists in the secondary dividing groove 4, the resistance value of each resistor 12 prior to laser trimming. Measurements can always be made accurately.
[0020]
Next, an overcoat layer 15 that covers the glass coat layer 14 and the trimming grooves 5 is formed on the upper surface of the ceramic substrate 1 by screen printing and firing, and then the ceramic substrate 1 is broken along the primary division grooves 2. Then, a strip-shaped divided piece 6 as shown in FIG. 2C is obtained (primary breaking step). Note that the strip electrode on the lower surface side of the ceramic substrate 1 is divided into two equal parts along the primary dividing groove 2 by this primary breaking step. Thereafter, by sputtering Ni—Cr or the like on each of the side end faces along the longitudinal direction of the strip-shaped segment 6, end face electrodes 17 that bridge the upper surface electrodes 13 and the lower side strip electrodes are formed on the side end faces. Form (end face electrode forming step).
[0021]
Next, by breaking the strip-shaped divided pieces 6 along the secondary divided grooves 4, a large number of single chips 7 as shown in FIG. 2D are obtained (secondary breaking step). By this secondary breaking step, the strip-like electrode on the lower surface side is divided into the lower electrode 16 and the ceramic substrate 11 is formed. Then, a large number of single chips 7 are collectively plated to form two-layered plating layers 18 and 19 that cover the base electrode layer (upper surface electrode 13, lower surface electrode 16, and end surface electrode 17). (Plating layer forming step). Thereby, a large number of finished chip resistors 10 as shown in FIG. 3 can be manufactured at once.
[0022]
In this way, in the manufacturing process of the chip resistor 10, when the technique of performing laser scribing twice when forming the secondary division grooves 4 that divide each strip electrode 3 into a plurality of upper surface electrodes 13 is adopted for the first time. Even if a conductive residue stays in the narrow divided groove 4a carved by the laser beam irradiation, the residue is removed by the second laser beam irradiation. There is no fear of being short-circuited, and it is possible to always accurately measure the resistance value of each resistor 12 prior to trimming. Therefore, an error is less likely to occur in the resistance value of the manufactured chip resistor 10, and the reliability is improved. In addition, when the method of dividing the strip electrode 3 into the plurality of upper surface electrodes 13 by the secondary dividing grooves 4 in this way is adopted, both sides of each region surrounded by the vertical and horizontal dividing grooves 2 and 4 on the upper surface of the ceramic substrate 1. Since the upper surface electrode 13 always exists in the portion, even if the upper surface electrode 13 and the resistor 12 are slightly misaligned, the area where the upper surface electrode 13 and the resistor 12 overlap in each region is as follows. It becomes almost constant and variation in resistance value is suppressed. Therefore, trimming work for adjusting the resistance value can be performed efficiently, and improvement in productivity can be expected.
[0023]
In the present embodiment, the chamfered portion 4b is formed on the opening end side of the narrow divided groove 4a formed by the first laser light irradiation by the second laser light irradiation performed in the secondary divided groove forming step. Therefore, even if the belt-like electrode 3 and the ceramic substrate 1 adjacent to the narrow dividing groove 4a become slightly brittle by the first laser light irradiation, this fragile portion can be removed by the second laser light irradiation. . Therefore, chipping is less likely to occur at the edge portion of the manufactured chip resistor 10, and there is no fear of hindering automatic mounting or the like.
[0025]
In the above embodiment, the case where the strip electrode forming process is performed after the primary split groove forming process has been described. However, the primary split groove 2 can be formed by laser scribing or the like after the strip electrode 3 is formed. is there. However, in that case, the strip electrode 3 is adjacent to the primary division groove 2 and the portion connected to the end face electrode 17 in the subsequent process becomes slightly brittle. Therefore, in order to prevent a decrease in reliability, the primary division groove formation step Also, it is preferable to remove the fragile portion of the strip electrode 3 by performing laser scribing twice.
[0026]
【The invention's effect】
The present invention is implemented in the form as described above, and has the following effects.
[0027]
In the manufacturing process of the chip resistor, when forming the secondary divided groove for dividing each strip electrode into a plurality of upper surface electrodes, laser scribing is performed twice, and conductive is conducted in the divided groove formed by the first laser light irradiation. Even if a residual residue remains, the residue can be removed by the second laser beam irradiation, so that short-circuiting between the top electrodes due to the residue is surely prevented. The resistance value of the resistor can always be measured accurately. In addition, since the strip electrode is divided into a plurality of upper surface electrodes, the area where the upper surface electrode and the resistor overlap in each region surrounded by the vertical and horizontal dividing grooves is almost constant, thereby suppressing variations in resistance value. The trimming operation of each resistor can be performed efficiently. In addition, a groove that is wider and shallower than that at the first laser light irradiation is set to be formed at the second laser light irradiation, and the first laser light irradiation is performed by the second laser light irradiation. Since the chamfered portion with a gentler slope than the depth side of the groove is formed on the opening end side of the engraved dividing groove, the strip electrode or ceramic substrate adjacent to the dividing groove becomes slightly brittle by the first laser light irradiation. Even so, the fragile portion can be removed by the second laser beam irradiation, and the edge portion of the manufactured chip resistor is less likely to be chipped. Therefore, it is possible to efficiently manufacture a highly reliable chip resistor with little resistance error.
[Brief description of the drawings]
BRIEF DESCRIPTION OF DRAWINGS FIG. 1 is an explanatory diagram showing processes until a secondary dividing groove is formed in a manufacturing process of a chip resistor according to an embodiment of the present invention.
FIG. 2 is an explanatory view showing a process after a resistor is formed in the manufacturing process of the chip resistor.
FIG. 3 is a cross-sectional view of a finished product of the chip resistor.
FIG. 4 is a cross-sectional view of a main part taken along line AA in FIG.
FIG. 5 is an explanatory view showing a method of manufacturing a chip resistor according to a conventional example.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Ceramic substrate 2 Primary division | segmentation groove | channel 3 Band-shaped electrode 4 Secondary division | segmentation groove | channel 4a Narrow division | segmentation groove | channel 4b Chamfering part 5 Trimming groove | channel 6 Strip-shaped division | segmentation piece 7 Chip single-piece | unit 10 Chip resistor 11 Ceramic base body 12 Resistor 13 Upper surface electrode 14 Glass coating Layer 15 Overcoat layer 16 Lower surface electrode 17 End surface electrode 18, 19 Plating layer

Claims (2)

多数個分のチップ抵抗器に対応する大判のセラミック基板の表面に所定の間隔を存して直線状に延びる複数の一次分割溝を形成する一次分割溝形成工程と、
前記セラミック基板の表面に幅方向中央を通過して長手方向に延びる二等分線が前記一次分割溝と略合致するように複数の帯状電極を形成する帯状電極形成工程と、
前記各帯状電極を複数の上面電極に分割するように、前記セラミック基板の表面に前記一次分割溝と直交するように所定の間隔を存して直線状に延びる複数の二次分割溝を形成する二次分割溝形成工程と、
前記一次分割溝と直交する方向に沿って隣り合う前記上面電極どうしを橋絡するように複数の抵抗体を形成する抵抗体形成工程と、
前記各抵抗体の抵抗値を調整する抵抗体トリミング工程と、
前記抵抗体トリミング工程の後に前記セラミック基板を前記一次分割溝および前記二次分割溝に沿って順次ブレイクするブレイク工程とを備え、
前記二次分割溝形成工程において、1回目のレーザ光照射で刻設した分割溝に2回目のレーザ光照射を施して前記二次分割溝を形成するようになし、この2回目のレーザ光照射時に1回目のレーザ光照射時よりも幅広で浅い溝を形成することにより、該1回目のレーザ光照射で刻設した分割溝の開口端側に溝奥側よりも傾斜が緩やかな面取り部を形成するようにしたことを特徴とするチップ抵抗器の製造方法。
A primary divided groove forming step of forming a plurality of primary divided grooves extending linearly on the surface of a large ceramic substrate corresponding to a large number of chip resistors, with a predetermined interval;
A strip electrode forming step of forming a plurality of strip electrodes so that a bisector extending in the longitudinal direction passing through the center in the width direction on the surface of the ceramic substrate substantially matches the primary dividing groove;
A plurality of secondary divided grooves extending linearly at predetermined intervals are formed on the surface of the ceramic substrate so as to divide each strip electrode into a plurality of upper surface electrodes. Secondary dividing groove forming step;
A resistor forming step of forming a plurality of resistors so as to bridge the upper surface electrodes adjacent to each other along a direction orthogonal to the primary dividing groove;
A resistor trimming step for adjusting the resistance value of each resistor;
A break step of sequentially breaking the ceramic substrate along the primary division grooves and the secondary division grooves after the resistor trimming step;
In the secondary divided groove forming step, the second divided groove is formed by performing the second laser light irradiation on the divided groove formed by the first laser light irradiation, and this second laser light irradiation. Sometimes, by forming a groove that is wider and shallower than at the time of the first laser light irradiation, a chamfered portion with a gentler slope than the groove rear side is formed at the opening end side of the divided groove formed by the first laser light irradiation. A method of manufacturing a chip resistor, characterized in that it is formed .
請求項1の記載において、前記帯状電極形成工程を前記一次分割溝形成工程の後に行うことを特徴とするチップ抵抗器の製造方法。  2. The method of manufacturing a chip resistor according to claim 1, wherein the strip electrode forming step is performed after the primary dividing groove forming step.
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JP2005317927A (en) * 2004-03-31 2005-11-10 Mitsubishi Materials Corp Chip resistor
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JP4602738B2 (en) * 2004-10-29 2010-12-22 太陽社電気株式会社 Manufacturing method of chip resistor
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