JPH11168003A - Chip component and manufacture thereof - Google Patents

Chip component and manufacture thereof

Info

Publication number
JPH11168003A
JPH11168003A JP9334409A JP33440997A JPH11168003A JP H11168003 A JPH11168003 A JP H11168003A JP 9334409 A JP9334409 A JP 9334409A JP 33440997 A JP33440997 A JP 33440997A JP H11168003 A JPH11168003 A JP H11168003A
Authority
JP
Japan
Prior art keywords
chip
substrate
exterior
extraction
recess
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP9334409A
Other languages
Japanese (ja)
Inventor
Koichiro Tsujiku
浩一郎 都竹
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Taiyo Yuden Co Ltd
Original Assignee
Taiyo Yuden Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Taiyo Yuden Co Ltd filed Critical Taiyo Yuden Co Ltd
Priority to JP9334409A priority Critical patent/JPH11168003A/en
Publication of JPH11168003A publication Critical patent/JPH11168003A/en
Withdrawn legal-status Critical Current

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  • Apparatuses And Processes For Manufacturing Resistors (AREA)
  • Non-Adjustable Resistors (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a chip component wherein local bulges are prevented. SOLUTION: All of a resistive film 2, pull-out electrodes 3, and an outer package 4 are embedded within a recess 1a of a chip 1, and the resistive film 2 is located under the pull-out electrodes 3, and moreover the surface height of the extraction electrodes and the surface height of the outer package 14 match with each other and are flush with the upper surface of the chip 1, so that the outward bulge of one part of the component due to the effects of the thickness of he resistive film 2 and the outer package 4 with not occur.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、チップ抵抗器等の
チップ部品と、該チップ部品の製造方法に関するもので
ある。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a chip component such as a chip resistor and a method for manufacturing the chip component.

【0002】[0002]

【従来の技術】チップ部品として代表的なチップ抵抗器
は、角柱形状のチップと、チップ一面中央に形成された
抵抗膜と、抵抗膜の両端部それぞれと接続するようにチ
ップ一面に形成された一対の引出電極と、抵抗膜の全部
と引出電極の少なくとも一部を覆うようにチップ一面に
形成された外装と、引出電極それぞれと接続するように
チップ両端部に形成された一対の外部電極とを備えてい
る。
2. Description of the Related Art A typical chip resistor as a chip component is formed on one surface of a chip so as to be connected to a prismatic chip, a resistance film formed at the center of one surface of the chip, and both ends of the resistance film. A pair of extraction electrodes, an exterior formed on one surface of the chip so as to cover all of the resistive film and at least a part of the extraction electrodes, and a pair of external electrodes formed on both ends of the chip so as to be connected to each of the extraction electrodes. It has.

【0003】このチップ抵抗器は、一般に、多数個取り
可能な大きさを有する基板の一面に所定配列で抵抗膜,
引出電極及び外装を順に形成した後、チップ一面に1つ
の抵抗膜と一対の引出電極が残るように基板を個々のチ
ップに分断し、分断されたチップの両端部それぞれに外
部電極を形成することにより製造されている。
[0003] In general, a chip resistor has a resistive film, which is formed in a predetermined arrangement on one surface of a substrate having a size capable of taking a large number.
After forming the extraction electrode and the exterior in order, the substrate is divided into individual chips such that one resistive film and a pair of extraction electrodes remain on one surface of the chip, and external electrodes are formed on both ends of the divided chip. It is manufactured by.

【0004】[0004]

【発明が解決しようとする課題】前記従来のチップ抵抗
器は、チップ一面に抵抗膜が形成され、これを覆うよう
に外装が形成されているため、この抵抗膜と外装の厚み
の影響によって一部分が外側に膨らんだ形状となってし
まう。このような形状を持つチップ抵抗器は、回路基板
への搭載時に表裏向きを揃える必要を生じると共に、近
年注目されているバルク供給方式、つまりバルク状に貯
蔵されたチップ部品を整列して供給する方式に適応させ
ることができない。この不具合は、同じような構成及び
形状を有する他種のチップ部品にも生じ得る。
In the conventional chip resistor, a resistive film is formed on one surface of the chip, and an outer package is formed so as to cover the resistive film. Will bulge outward. A chip resistor having such a shape needs to be turned upside down when mounted on a circuit board, and a bulk supply method which has attracted attention in recent years, that is, chip components stored in a bulk form are arranged and supplied. Cannot adapt to the scheme. This defect can also occur in other types of chip components having similar configurations and shapes.

【0005】本発明は前記事情に鑑みてなされたもの
で、その目的とするところは、局部的な膨らみを防止し
たチップ部品と、該チップ部品を的確に製造できるチッ
プ部品の製造方法を提供することにある。
The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a chip component in which local swelling is prevented and a method for manufacturing the chip component capable of accurately manufacturing the chip component. It is in.

【0006】[0006]

【課題を解決するための手段】前記目的を達成するた
め、本発明のチップ部品は、請求項1に記載のように、
一面中央に凹部を有するチップと、凹部内に埋設された
回路部と、回路部の両端部それぞれと接続するようにチ
ップに設けられた一対の引出電極と、引出電極の接続部
分を除く回路部の表面を覆うようにチップに設けられた
外装と、引出電極それぞれと接続するようにチップに設
けられた一対の外部電極とを備え、回路部が引出電極の
下側に位置し、引出電極の表面高さと外装の表面高さと
が一致している、ことをその特徴とする。このチップ部
品によれば、回路部が引出電極の下側に位置し、しかも
引出電極の表面高さと外装の表面高さとが一致している
ため、回路部と外装の厚みの影響によって部品の一部分
が外側に膨らんでしまうことはない。
In order to achieve the above object, a chip component according to the present invention has the following features.
A chip having a concave portion in the center of one surface, a circuit portion embedded in the concave portion, a pair of extraction electrodes provided on the chip so as to be connected to both ends of the circuit portion, and a circuit portion excluding a connection portion of the extraction electrode An exterior provided on the chip so as to cover the surface of the chip, and a pair of external electrodes provided on the chip so as to be connected to each of the extraction electrodes, the circuit portion is located below the extraction electrode, The feature is that the surface height and the surface height of the exterior are the same. According to this chip component, since the circuit portion is located below the extraction electrode and the surface height of the extraction electrode matches the surface height of the exterior, a part of the component is affected by the thickness of the circuit portion and the exterior. Does not bulge outward.

【0007】一方、本発明のチップ部品の製造方法は、
請求項3に記載のように、少なくとも1つの直線状凹部
を一面に有する基板を用意する工程と、基板の凹部内に
間隔をおいて回路部を埋設する工程と、各回路部の両端
部それぞれと接続するように基板に間隔をおいて引出電
極を形成する工程と、各回路部の露出部分を覆うよう
に、且つ自らの表面高さが引出電極の表面高さと一致す
るように基板に外装を形成する工程と、チップ一面中央
に凹部が残るように基板を個々のチップに分断する工程
と、引出電極それぞれと接続するようにチップに一対の
外部電極を形成する工程とを備えた、ことをその特徴と
する。この製造方法によれば請求項1に記載のチップ部
品を好適に製造できる。
On the other hand, the method for manufacturing a chip component of the present invention
A step of preparing a substrate having at least one linear concave portion on one surface, a step of embedding circuit portions at intervals in the concave portion of the substrate, and both end portions of each circuit portion. Forming extraction electrodes at intervals on the substrate so that they are connected to the substrate; and covering the substrate so that the exposed portions of each circuit section are covered and its own surface height matches the surface height of the extraction electrodes. Forming, a step of dividing the substrate into individual chips so that a concave portion remains in the center of one surface of the chip, and a step of forming a pair of external electrodes on the chip so as to be connected to each of the extraction electrodes. Is its feature. According to this manufacturing method, the chip component described in claim 1 can be suitably manufactured.

【0008】[0008]

【発明の実施の形態】[第1実施形態]図1乃至図3は
本発明をチップ抵抗器に適用した第1実施形態を示すも
ので、図1はチップ抵抗器の平面図、図2は図1のY−
Y線断面図、図3は図1のX−X線断面図である。
DESCRIPTION OF THE PREFERRED EMBODIMENTS [First Embodiment] FIGS. 1 to 3 show a first embodiment in which the present invention is applied to a chip resistor. FIG. 1 is a plan view of a chip resistor, and FIG. Y- in FIG.
FIG. 3 is a sectional view taken along line XX of FIG. 1.

【0009】図中の1は角柱形状を成すチップで、周知
の絶縁材料、例えばアルミナセラミクスから成る。この
チップ1の上面の長さ方向中央には、所定の深さ及び長
さ寸法を有する縦断面略コ字形の凹部1aが設けられて
いる。また、凹部1aの長さ方向両端部それぞれには、
凹部深さの約1/2の高さ寸法を有する段部1bが設け
られている。
Reference numeral 1 in the drawing denotes a prism-shaped chip, which is made of a known insulating material, for example, alumina ceramics. At the center of the upper surface of the chip 1 in the length direction, a concave portion 1a having a substantially U-shaped vertical cross section having a predetermined depth and length is provided. In addition, at each of both ends in the longitudinal direction of the concave portion 1a,
A step 1b having a height dimension of about 1/2 of the depth of the recess is provided.

【0010】2は平面形状が矩形を成す抵抗膜で、周知
の抵抗材料、例えば酸化ルテニウムから成る。この抵抗
膜2は、チップ1の凹部1a内に埋設されている。抵抗
膜2の幅寸法はチップ1(凹部1a)の幅寸法よりも小
さく、また厚み寸法は凹部1aの底面から段部1bの上
面までの寸法に一致し、さらに長さ寸法は凹部1aの段
部1b間距離に一致している。
Reference numeral 2 denotes a resistance film having a rectangular planar shape, which is made of a known resistance material, for example, ruthenium oxide. The resistance film 2 is embedded in the recess 1 a of the chip 1. The width dimension of the resistive film 2 is smaller than the width dimension of the chip 1 (recess 1a), the thickness dimension corresponds to the dimension from the bottom surface of the recess 1a to the upper surface of the step 1b, and the length dimension is the height of the step of the recess 1a. It corresponds to the distance between the parts 1b.

【0011】3は平面形状が矩形を成す一対の引出電極
で、周知の電極材料、例えば銀から成る。各引出電極3
は、その長さ方向一端部が抵抗膜2の両端部それぞれと
重なって接続するようにチップ1の凹部1a内の長手方
向両端部(段部1bの上側箇所)に埋設されている。各
引出電極3の幅寸法は抵抗膜2の幅寸法と一致し、また
厚み寸法は段部1bの上面から凹部1aの開口縁までの
寸法に一致し、さらに長さ寸法は段部1b上面の長さ寸
法よりも僅かに大きい。
Reference numeral 3 denotes a pair of extraction electrodes having a rectangular planar shape, which is made of a known electrode material, for example, silver. Each extraction electrode 3
Are embedded at both ends in the longitudinal direction (upper portions of the step portion 1b) in the concave portion 1a of the chip 1 so that one end in the length direction overlaps and connects to both ends of the resistive film 2. The width dimension of each extraction electrode 3 matches the width dimension of the resistive film 2, the thickness dimension corresponds to the dimension from the upper surface of the step 1b to the opening edge of the recess 1a, and the length dimension is the upper surface of the step 1b. Slightly larger than the length dimension.

【0012】4は平面形状が概ね矩形を成す外装で、周
知の外装材料、例えば石英ガラスから成る。この外装4
は、引出電極3の接続部分を除く抵抗膜2の表面全部と
各引出電極3の内側端面を覆うようにチップ1の凹部1
a内に埋設されている。外装4の幅寸法はチップ1の幅
寸法と一致し、また抵抗膜2よりも上側の厚み寸法は引
出電極3のそれと一致し、さらに長さ寸法は引出電極3
間部分では引出電極3間の距離と一致し他の部分では凹
部1aの長さ寸法と一致している。
Reference numeral 4 denotes an exterior having a substantially rectangular planar shape, which is made of a known exterior material, for example, quartz glass. This exterior 4
The concave portion 1 of the chip 1 covers the entire surface of the resistive film 2 except for the connection portion of the extraction electrode 3 and the inner end surface of each extraction electrode 3.
It is buried in a. The width of the package 4 matches the width of the chip 1, the thickness above the resistive film 2 matches that of the extraction electrode 3, and the length dimension of the extraction electrode 3
In the intervening portion, the distance matches the distance between the extraction electrodes 3, and in other portions, the length matches the length of the concave portion 1a.

【0013】つまり、前記の抵抗膜2,引出電極3及び
外装4は全てチップ1の凹部1a内に埋設されており、
抵抗膜2の厚み寸法と該抵抗膜2の上側の外装4の厚み
寸法の和は凹部1aの深さ寸法と一致している。また、
引出電極3の厚み寸法と抵抗膜2の上側の外装4の厚み
寸法とが一致することから、引出電極3の表面高さと外
装4の表面高さは互いに一致しチップ1の上面と面一の
状態にある。
That is, the resistance film 2, the extraction electrode 3 and the exterior 4 are all buried in the recess 1 a of the chip 1.
The sum of the thickness of the resistive film 2 and the thickness of the outer case 4 above the resistive film 2 matches the depth of the recess 1a. Also,
Since the thickness dimension of the extraction electrode 3 and the thickness dimension of the outer package 4 on the upper side of the resistance film 2 match, the surface height of the extraction electrode 3 and the surface height of the exterior 4 match each other and are flush with the upper surface of the chip 1. In state.

【0014】5は一対の外部電極で、周知の電極材料、
例えば銀から成る。各外部電極5は、引出電極3の表面
全部と外装4の表面両端部を覆うようにチップ1の両端
部に設けられ引出電極3と接続している。
Reference numeral 5 denotes a pair of external electrodes, which are well-known electrode materials;
For example, it is made of silver. Each external electrode 5 is provided at both ends of the chip 1 so as to cover the entire surface of the extraction electrode 3 and both ends of the surface of the exterior 4 and is connected to the extraction electrode 3.

【0015】ここで、図1乃至図3に示したチップ抵抗
器の製造手順を図4乃至図9を参照して説明する。尚、
図示例では6個取りの基板を用いて製造方法を説明して
あるが、実際のものは、これよりも多数の部品取りが可
能な大きさの基板が用いられる。
Here, a manufacturing procedure of the chip resistor shown in FIGS. 1 to 3 will be described with reference to FIGS. still,
In the illustrated example, the manufacturing method is described using a six-piece board, but in actuality, a board having a size capable of taking a larger number of components than this is used.

【0016】まず、図4に示すように、一面に直線状凹
部LGを所定間隔で平行に有する基板、例えばアルミナ
基板CSを用意する。この基板CSは、アルミナ粉末含
有のセラミクススラリーを材料としてドクターブレード
等の手法を利用して所定の厚みのグリーンシートを作成
するステップと、これから単位形状のグリーンシート
(未焼成セラミクス基板)を型抜き等の手法によって得
るステップと、このグリーンシートに型押し等の手法に
よって直線状凹部LGを形成するステップと、このグリ
ーンシートを所定温度で焼成するステップとを経て作成
される。
First, as shown in FIG. 4, a substrate having, for example, an alumina substrate CS having parallel linear recesses LG at predetermined intervals on one surface is prepared. This substrate CS is formed by using a ceramic slurry containing alumina powder as a material and using a method such as a doctor blade to form a green sheet having a predetermined thickness, and from this, a unit-shaped green sheet (unfired ceramic substrate) is die-cut. And the like, a step of forming a linear concave portion LG in the green sheet by a method such as embossing, and a step of firing the green sheet at a predetermined temperature.

【0017】次に、図5に示すように、基板CSの各凹
部LG内に、酸化ルテニウム粉末を含有した抵抗ペース
トをスクリーン印刷等の手法を利用して所定の形状及び
厚みで、且つ凹部LGに沿って等間隔で塗布し、これを
所定温度で焼き付けて抵抗膜RFを形成する。
Next, as shown in FIG. 5, a resist paste containing a ruthenium oxide powder is formed in each concave portion LG of the substrate CS in a predetermined shape and thickness using a method such as screen printing or the like. Is applied at regular intervals along the line and is baked at a predetermined temperature to form a resistive film RF.

【0018】次に、図6に示すように、基板CSの各凹
部LG内の各抵抗膜RFの両側に、銀粉末を含有した電
極ペーストをスクリーン印刷等の手法を利用して所定の
形状及び厚みで、且つ凹部LGに沿って等間隔で塗布
し、これを所定温度で焼き付けて引出電極ECを形成す
る。
Next, as shown in FIG. 6, an electrode paste containing silver powder is formed on both sides of each resistive film RF in each concave portion LG of the substrate CS by using a method such as screen printing or the like. The lead electrode EC is formed with a thickness and applied at regular intervals along the concave portion LG and baked at a predetermined temperature.

【0019】次に、図7に示すように、基板CSの各凹
部LG内に、石英ガラスを主体とした外装ペーストをス
クリーン印刷等の手法を利用して所定の形状及び厚みで
塗布し、これを所定温度で焼き付けて外装AFを形成す
る。
Next, as shown in FIG. 7, an exterior paste mainly composed of quartz glass is applied to each recess LG of the substrate CS in a predetermined shape and thickness by using a method such as screen printing. At a predetermined temperature to form an exterior AF.

【0020】次に、図8に示すように、ダイヤモンドブ
レード等の切断工具を用い、基板CSを図中破線で示す
ラインに沿って切断し、個々のチップCCに分断する。
Next, as shown in FIG. 8, using a cutting tool such as a diamond blade, the substrate CS is cut along the lines shown by broken lines in the figure, and divided into individual chips CC.

【0021】次に、図9に示すように、各チップCCの
両端部に、銀粉末を含有した電極ペーストをディップ等
の手法を利用して所定の形状及び厚みで塗布し、これを
所定温度で焼き付けて外部電極EEを形成する。
Next, as shown in FIG. 9, an electrode paste containing silver powder is applied to both ends of each chip CC in a predetermined shape and thickness by using a technique such as dipping, and is applied to a predetermined temperature. To form external electrodes EE.

【0022】本実施形態のチップ抵抗器は、抵抗膜2,
引出電極3及び外装4が全てチップ1の凹部1a内に埋
設されると共に、抵抗膜2が引出電極3よりも下側に位
置し、しかも引出電極3の表面高さと外装4の表面高さ
とが互いに一致しチップ1の上面と面一の状態にあるた
め、抵抗膜2と外装4の厚みの影響によって部品の一部
分が外側に膨らんでしまうことがない。つまり、部品自
体の形状が、長手方向,幅方向及び厚み方向のそれぞれ
でほぼ対称で、表裏等の方向制限のない形状となるた
め、従来のように回路基板への搭載時に表裏向きを揃え
る面倒がなくなると共に、近年注目されているバルク供
給方式への適応が可能となる。
The chip resistor according to the present embodiment has a resistance film 2
The extraction electrode 3 and the exterior 4 are all buried in the recess 1 a of the chip 1, the resistive film 2 is located below the extraction electrode 3, and the surface height of the extraction electrode 3 and the surface of the exterior 4 are different. Since they match each other and are flush with the upper surface of the chip 1, a part of the component does not bulge outward due to the influence of the thickness of the resistive film 2 and the outer package 4. In other words, since the shape of the component itself is substantially symmetrical in the longitudinal direction, the width direction, and the thickness direction, and has no direction limitation such as front and back, it is troublesome to align the front and back when mounting on a circuit board as in the related art. Is eliminated, and adaptation to a bulk supply method that has been attracting attention in recent years becomes possible.

【0023】また、本実施形態の製造方法によれば、直
線状凹部LGを有する基板CSを、単位形状のグリーン
シート(未焼成セラミクス基板)に型押し等の手法によ
って直線状凹部LGを形成してから、該未焼成セラミク
ス基板を焼成することにより作成しているので、焼成後
の基板に研削加工によって同様の凹部を形成する場合に
比べて、凹部LGの内面を滑らかに仕上げ、且つ凹部L
Gの寸法ばらつきを抑制することができ、これにより凹
部LG内に埋設される抵抗膜RFの寸法精度を高めるこ
とができる。
Further, according to the manufacturing method of the present embodiment, the substrate CS having the linear concave portions LG is formed in a unit-shaped green sheet (unfired ceramics substrate) by embossing or the like to form the linear concave portions LG. After that, since the unfired ceramics substrate is formed by firing, the inner surface of the recess LG is more smoothly finished and the recess L is compared with a case where similar recesses are formed by grinding in the fired substrate.
The dimensional variation of G can be suppressed, whereby the dimensional accuracy of the resistive film RF embedded in the concave portion LG can be increased.

【0024】尚、部品製造過程において引出電極ECを
形成した後に、抵抗膜2の抵抗値調整のためのトリミン
グを適宜実施してもよい。具体的には、抵抗膜両側の引
出電極ECに検出端子を接触させた状態で、赤外領域の
レーザビームを抵抗膜RFの表面に照射して該抵抗膜R
Fにスリットを形成する方法が抵抗値調整法として採用
できる。
After the extraction electrode EC is formed in the component manufacturing process, trimming for adjusting the resistance value of the resistance film 2 may be appropriately performed. Specifically, in a state where the detection terminal is brought into contact with the extraction electrode EC on both sides of the resistive film, the surface of the resistive film RF is irradiated with a laser beam in the infrared region to irradiate the resistive film R.
A method of forming a slit in F can be adopted as a resistance value adjusting method.

【0025】[第2実施形態]図10乃至図12は本発
明をチップ抵抗器に適用した第2実施形態を示すもの
で、図10はチップ抵抗器の平面図、図11は図10の
Y−Y線断面図、図12は図10のX−X線断面図であ
る。
Second Embodiment FIGS. 10 to 12 show a second embodiment in which the present invention is applied to a chip resistor. FIG. 10 is a plan view of the chip resistor, and FIG. FIG. 12 is a sectional view taken along line XX of FIG. 10.

【0026】図中の11は角柱形状を成すチップで、周
知の絶縁材料、例えばアルミナセラミクスから成る。こ
のチップ11の上面の長さ方向中央には、所定の深さ及
び長さ寸法を有する縦断面コ字形の凹部11aが設けら
れている。
In the drawing, reference numeral 11 denotes a prism-shaped chip, which is made of a known insulating material, for example, alumina ceramics. At the center in the longitudinal direction of the upper surface of the chip 11, a concave section 11a having a U-shaped vertical section having a predetermined depth and length is provided.

【0027】12は平面形状が矩形を成す抵抗膜で、周
知の抵抗材料、例えば酸化ルテニウムから成る。この抵
抗膜12は、チップ11の凹部11a内に埋設されてい
る。抵抗膜12の幅寸法はチップ11(凹部11a)の
幅寸法よりも小さく、また厚み寸法は凹部11aの深さ
寸法に一致し、さらに長さ寸法は凹部11aの長さ寸法
に一致している。
Reference numeral 12 denotes a resistance film having a rectangular planar shape, which is made of a known resistance material, for example, ruthenium oxide. The resistance film 12 is embedded in the recess 11 a of the chip 11. The width dimension of the resistive film 12 is smaller than the width dimension of the chip 11 (the concave section 11a), the thickness dimension corresponds to the depth dimension of the concave section 11a, and the length dimension coincides with the length dimension of the concave section 11a. .

【0028】13は平面形状が矩形を成す一対の引出電
極で、周知の電極材料、例えば銀から成る。各引出電極
13は、その長さ方向一端縁がチップ端縁と一致し、且
つの長さ方向他端部が抵抗膜12の両端部それぞれと重
なって接続するようにチップ11の上面両端部に設けら
れている。各引出電極13の幅寸法は抵抗膜12の幅寸
法と一致している。
Reference numeral 13 denotes a pair of extraction electrodes having a rectangular planar shape, which is made of a known electrode material, for example, silver. Each of the extraction electrodes 13 is provided at both ends of the upper surface of the chip 11 such that one end in the longitudinal direction thereof coincides with the end of the chip, and the other end in the longitudinal direction overlaps and connects to both ends of the resistive film 12. Is provided. The width of each extraction electrode 13 matches the width of the resistance film 12.

【0029】14は平面形状が概ね矩形を成す外装で、
周知の外装材料、例えば石英ガラスから成る。この外装
14は、引出電極13の接続部分を除く抵抗膜12の表
面全部と各引出電極13の内側端面を覆うようにチップ
11の凹部11a内から上面にかけて設けられている。
外装14の幅寸法はチップ11の幅寸法と一致し、また
抵抗膜12よりも上側の厚み寸法は引出電極13のそれ
と一致し、さらに長さ寸法は引出電極13間部分では引
出電極13間の距離と一致し他の部分ではチップ11の
長さ寸法と一致している。
14 is an exterior having a substantially rectangular planar shape.
It is made of a known exterior material, for example, quartz glass. The exterior 14 is provided from the inside of the concave portion 11 a of the chip 11 to the upper surface so as to cover the entire surface of the resistive film 12 except for the connection portion of the extraction electrode 13 and the inner end surface of each extraction electrode 13.
The width of the outer case 14 matches the width of the chip 11, the thickness above the resistive film 12 matches that of the extraction electrode 13, and the length between the extraction electrodes 13 at the portion between the extraction electrodes 13. The distance coincides with the length of the chip 11 at other portions.

【0030】つまり、前記の抵抗膜12はチップ11の
凹部11a内に埋設されており、抵抗膜12の厚み寸法
は凹部11aの深さ寸法と一致している。また、引出電
極13の厚み寸法と抵抗膜12の上側の外装14の厚み
寸法とが一致することから、引出電極13の表面高さと
外装14の表面高さは互いに一致している。
That is, the resistance film 12 is embedded in the recess 11a of the chip 11, and the thickness of the resistance film 12 matches the depth of the recess 11a. Further, since the thickness dimension of the extraction electrode 13 and the thickness dimension of the exterior 14 above the resistance film 12 match, the surface height of the extraction electrode 13 and the surface height of the exterior 14 match each other.

【0031】15は一対の外部電極で、周知の電極材
料、例えば銀から成る。各外部電極15は、引出電極1
3の表面全部と外装14の表面両端部を覆うようにチッ
プ11の両端部に形成され引出電極13と接続してい
る。
Reference numeral 15 denotes a pair of external electrodes, which are made of a known electrode material, for example, silver. Each external electrode 15 is an extraction electrode 1
3 are formed on both ends of the chip 11 so as to cover the entire surface of the chip 3 and both ends of the surface of the exterior 14, and are connected to the extraction electrodes 13.

【0032】ここで、図10乃至図12に示したチップ
抵抗器の製造手順を図13乃至図18を参照して説明す
る。尚、図示例では6個取りの基板を用いて製造方法を
説明してあるが、実際のものは、これよりも多数の部品
取りが可能な大きさの基板が用いられる。
Here, a manufacturing procedure of the chip resistor shown in FIGS. 10 to 12 will be described with reference to FIGS. In the illustrated example, the manufacturing method is described using a six-piece board. However, in the actual example, a board having a size capable of taking a larger number of components is used.

【0033】まず、図13に示すように、一面に直線状
凹部LGを所定間隔で平行に有する基板、例えばアルミ
ナ基板CSを用意する。この基板CSは、アルミナ粉末
含有のセラミクススラリーを材料としてドクターブレー
ド等の手法を利用して所定の厚みのグリーンシートを作
成するステップと、これから単位形状のグリーンシート
(未焼成セラミクス基板)を型抜き等の手法によって得
るステップと、このグリーンシートに型押し等の手法に
よって直線状凹部LGを形成するステップと、このグリ
ーンシートを所定温度で焼成するステップとを経て作成
される。
First, as shown in FIG. 13, a substrate, for example, an alumina substrate CS having parallel linear concave portions LG on one surface at predetermined intervals is prepared. This substrate CS is formed by using a ceramic slurry containing alumina powder as a material and using a method such as a doctor blade to form a green sheet having a predetermined thickness, and from this, a unit-shaped green sheet (unfired ceramic substrate) is die-cut. And the like, a step of forming a linear concave portion LG in the green sheet by a method such as embossing, and a step of firing the green sheet at a predetermined temperature.

【0034】次に、図14に示すように、基板CSの各
凹部LG内に、酸化ルテニウム粉末を含有した抵抗ペー
ストをスクリーン印刷等の手法を利用して所定の形状及
び厚みで、且つ凹部LGに沿って等間隔で塗布し、これ
を所定温度で焼き付けて抵抗膜RFを形成する。
Next, as shown in FIG. 14, a resist paste containing a ruthenium oxide powder is formed in each concave portion LG of the substrate CS in a predetermined shape and thickness by using a method such as screen printing. Is applied at regular intervals along the line and is baked at a predetermined temperature to form a resistive film RF.

【0035】次に、図15に示すように、基板一面の各
抵抗膜RFの両側に、銀粉末を含有した電極ペーストを
スクリーン印刷等の手法を利用して所定の形状及び厚み
で、且つ凹部LGに沿って等間隔で塗布し、これを所定
温度で焼き付けて引出電極ECを形成する。
Next, as shown in FIG. 15, an electrode paste containing silver powder is formed on both sides of each resistive film RF on the entire surface of the substrate in a predetermined shape and thickness using a technique such as screen printing or the like. It is applied at equal intervals along the LG, and is baked at a predetermined temperature to form the extraction electrode EC.

【0036】次に、図16に示すように、基板CSの各
凹部LG内と基板一面に、石英ガラスを主体とした外装
ペーストをスクリーン印刷等の手法を利用して所定の形
状及び厚みで塗布し、これを所定温度で焼き付けて外装
AFを形成する。
Next, as shown in FIG. 16, an exterior paste mainly composed of quartz glass is applied to the inside of each recess LG of the substrate CS in a predetermined shape and thickness using a method such as screen printing. Then, this is baked at a predetermined temperature to form the exterior AF.

【0037】次に、図17に示すように、ダイヤモンド
ブレード等の切断工具を用い、基板CSを図中破線で示
すラインに沿って切断し、個々のチップCCに分断す
る。
Next, as shown in FIG. 17, using a cutting tool such as a diamond blade, the substrate CS is cut along the lines shown by broken lines in the figure, and divided into individual chips CC.

【0038】次に、図18に示すように、各チップCC
の両端部に、銀粉末を含有した電極ペーストをディップ
等の手法を利用して所定の形状及び厚みで塗布し、これ
を所定温度で焼き付けて外部電極EEを形成する。
Next, as shown in FIG.
An electrode paste containing silver powder is applied in a predetermined shape and thickness by using a technique such as dipping on both ends of the electrode paste, and is baked at a predetermined temperature to form an external electrode EE.

【0039】本実施形態のチップ抵抗器は、抵抗膜12
がチップ11の凹部11a内に埋設されると共に、抵抗
膜12が引出電極13よりも下側に位置し、しかも引出
電極13の表面高さと外装14の表面高さとが互いに一
致しているため、抵抗膜12と外装14の厚みの影響に
よって部品の一部分が外側に膨らんでしまうことがな
い。つまり、部品自体の形状が、長手方向,幅方向及び
厚み方向のそれぞれでほぼ対称で、表裏等の方向制限の
ない形状となるため、従来のように回路基板への搭載時
に表裏向きを揃える面倒がなくなると共に、近年注目さ
れているバルク供給方式への適応が可能となる。
The chip resistor of the present embodiment has a resistance film 12
Is embedded in the recess 11a of the chip 11, the resistance film 12 is located below the extraction electrode 13, and the surface height of the extraction electrode 13 and the surface height of the exterior 14 match each other. A part of the component does not bulge outward due to the influence of the thickness of the resistive film 12 and the exterior 14. In other words, since the shape of the component itself is substantially symmetrical in the longitudinal direction, the width direction, and the thickness direction, and has no direction limitation such as front and back, it is troublesome to align the front and back when mounting on a circuit board as in the related art. Is eliminated, and adaptation to a bulk supply method that has been attracting attention in recent years becomes possible.

【0040】また、本実施形態の製造方法によれば、第
1実施形態と同様に、直線状凹部LGを有する基板CS
を、単位形状のグリーンシート(未焼成セラミクス基
板)に型押し等の手法によって直線状凹部LGを形成し
てから、該未焼成セラミクス基板を焼成することにより
作成しているので、焼成後の基板に研削加工によって同
様の凹部を形成する場合に比べて、凹部LGの内面を滑
らかに仕上げ、且つ凹部LGの寸法ばらつきを抑制する
ことができ、これにより凹部LG内に埋設される抵抗膜
RFの寸法精度を高めることができる。
According to the manufacturing method of this embodiment, as in the first embodiment, the substrate CS having the linear concave portions LG is formed.
Is formed by forming a linear concave portion LG in a unit-shaped green sheet (unfired ceramics substrate) by a method such as embossing and then firing the unfired ceramics substrate. As compared with the case where the same recess is formed by grinding, the inner surface of the recess LG can be finished more smoothly and the dimensional variation of the recess LG can be suppressed, whereby the resistance film RF embedded in the recess LG can be formed. The dimensional accuracy can be improved.

【0041】尚、部品製造過程において基板CSと一緒
に電極ECと外装AFを切断するものを示したが、外装
AFを抵抗膜単位で個々に形成すれば外装に切断面のな
いチップ抵抗器を得ることができ、また引出電極ECを
抵抗膜単位で2個ずつ形成すれば、引出電極に切断面の
ないチップ抵抗器を得ることができる。
Although the electrode EC and the exterior AF are cut together with the substrate CS in the component manufacturing process, a chip resistor having no cut surface on the exterior can be obtained by forming the exterior AF individually in units of resistive films. If two extraction electrodes EC are formed for each resistive film, a chip resistor having no cut surface in the extraction electrode can be obtained.

【0042】また、部品製造過程において引出電極EC
を形成した後に、抵抗膜2の抵抗値調整のためのトリミ
ングを適宜実施してもよい。具体的には、抵抗膜両側の
引出電極ECに検出端子を接触させた状態で、赤外領域
のレーザビームを抵抗膜RFの表面に照射して該抵抗膜
RFにスリットを形成する方法が抵抗値調整法として採
用できる。
In the part manufacturing process, the extraction electrode EC is used.
After the formation, the trimming for adjusting the resistance value of the resistance film 2 may be appropriately performed. Specifically, a method of forming a slit in the resistive film RF by irradiating the surface of the resistive film RF with a laser beam in the infrared region while the detection terminal is in contact with the extraction electrode EC on both sides of the resistive film is known. It can be adopted as a value adjustment method.

【0043】以上、前述の各実施形態では、本発明をチ
ップ抵抗器に適用したものを示したが、本発明は、抵抗
膜以外の回路部とこれを覆う外装を有する他種のチップ
部品にも幅広く適用でき、同様の効果を得ることができ
る。
As described above, in each of the above embodiments, the present invention is applied to a chip resistor. However, the present invention is applied to other types of chip parts having a circuit portion other than a resistive film and an exterior covering the circuit portion. Can be widely applied, and the same effect can be obtained.

【0044】[0044]

【発明の効果】以上詳述したように、本発明のチップ部
品によれば、回路部と外装の厚みの影響によって部品の
一部分が外側に膨らんでしまうことがなく、部品自体の
形状を表裏等の方向制限のない形状とすることができる
ので、回路基板への搭載時に従来のように表裏向きを揃
える面倒がなくなると共に、近年注目されているバルク
供給方式への適応が可能となる等、部品の取り扱い性を
格段高めることができる。また、本発明のチップ部品の
製造方法によれば、前記のチップ部品を好適に、しかも
安定して製造できる。
As described above in detail, according to the chip component of the present invention, a part of the component does not bulge outward due to the influence of the thickness of the circuit portion and the outer package, and the shape of the component itself can be changed from front to back. It can be made into a shape without any direction restrictions, so that it does not have to be face-to-face as in the past when mounting on a circuit board, and it is possible to adapt to the bulk supply method that has been attracting attention recently. Can be greatly improved. Further, according to the method of manufacturing a chip component of the present invention, the above-mentioned chip component can be suitably and stably manufactured.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の第1実施形態を示すチップ抵抗器の平
面図
FIG. 1 is a plan view of a chip resistor according to a first embodiment of the present invention.

【図2】図1のY−Y線断面図FIG. 2 is a sectional view taken along line YY of FIG.

【図3】図1のX−X線断面図FIG. 3 is a sectional view taken along line XX of FIG. 1;

【図4】第1実施形態のチップ抵抗器の製造手順を示す
FIG. 4 is a diagram showing a manufacturing procedure of the chip resistor according to the first embodiment;

【図5】第1実施形態のチップ抵抗器の製造手順を示す
FIG. 5 is a diagram showing a manufacturing procedure of the chip resistor according to the first embodiment;

【図6】第1実施形態のチップ抵抗器の製造手順を示す
FIG. 6 is a diagram showing a manufacturing procedure of the chip resistor according to the first embodiment;

【図7】第1実施形態のチップ抵抗器の製造手順を示す
FIG. 7 is a view showing a manufacturing procedure of the chip resistor according to the first embodiment;

【図8】第1実施形態のチップ抵抗器の製造手順を示す
FIG. 8 is a diagram showing a manufacturing procedure of the chip resistor according to the first embodiment;

【図9】第1実施形態のチップ抵抗器の製造手順を示す
FIG. 9 is a diagram showing a manufacturing procedure of the chip resistor according to the first embodiment;

【図10】本発明の第2実施形態を示すチップ抵抗器の
平面図
FIG. 10 is a plan view of a chip resistor according to a second embodiment of the present invention.

【図11】図10のY−Y線断面図11 is a sectional view taken along line YY of FIG.

【図12】図10のX−X線断面図FIG. 12 is a sectional view taken along line XX of FIG. 10;

【図13】第2実施形態のチップ抵抗器の製造手順を示
す図
FIG. 13 is a diagram showing a manufacturing procedure of the chip resistor of the second embodiment.

【図14】第2実施形態のチップ抵抗器の製造手順を示
す図
FIG. 14 is a view showing a manufacturing procedure of the chip resistor according to the second embodiment;

【図15】第2実施形態のチップ抵抗器の製造手順を示
す図
FIG. 15 is a view showing a manufacturing procedure of the chip resistor according to the second embodiment;

【図16】第2実施形態のチップ抵抗器の製造手順を示
す図
FIG. 16 is a diagram showing a manufacturing procedure of the chip resistor according to the second embodiment;

【図17】第2実施形態のチップ抵抗器の製造手順を示
す図
FIG. 17 is a diagram showing a manufacturing procedure of the chip resistor according to the second embodiment;

【図18】第2実施形態のチップ抵抗器の製造手順を示
す図
FIG. 18 is a view showing a manufacturing procedure of the chip resistor according to the second embodiment;

【符号の説明】[Explanation of symbols]

1,11…チップ、1a,11a…凹部、1b…段部、
2,12…抵抗膜、3,13…引出電極、4,14…外
装、5,15…外部電極、CS…基板、LG…凹部、R
F…抵抗膜、EC…引出電極、AF…外装、CC…チッ
プ、EE…外部電極。
1, 11: chip, 1a, 11a: concave portion, 1b: step portion,
2,12: Resistive film, 3,13: Lead electrode, 4,14: Exterior, 5,15: External electrode, CS: Substrate, LG: Concave, R
F: resistive film, EC: extraction electrode, AF: exterior, CC: chip, EE: external electrode.

Claims (4)

【特許請求の範囲】[Claims] 【請求項1】 一面中央に凹部を有するチップと、 凹部内に埋設された回路部と、 回路部の両端部それぞれと接続するようにチップに設け
られた一対の引出電極と、 引出電極の接続部分を除く回路部の表面を覆うようにチ
ップに設けられた外装と、 引出電極それぞれと接続するようにチップに設けられた
一対の外部電極とを備え、 回路部が引出電極よりも下側に位置し、引出電極の表面
高さと外装の表面高さとが一致している、 ことを特徴とするチップ部品。
1. A chip having a recess in the center of one surface, a circuit portion embedded in the recess, a pair of extraction electrodes provided on the chip so as to connect to both ends of the circuit portion, and connection of the extraction electrodes. It has an exterior provided on the chip so as to cover the surface of the circuit part excluding the part, and a pair of external electrodes provided on the chip so as to be connected to each of the extraction electrodes, and the circuit part is below the extraction electrode A chip component, wherein the surface height of the extraction electrode is equal to the surface height of the exterior.
【請求項2】 引出電極と外装が凹部内に埋設されてい
る、 ことを特徴とする請求項1記載のチップ部品。
2. The chip component according to claim 1, wherein the extraction electrode and the exterior are buried in the recess.
【請求項3】 少なくとも1つの直線状凹部を一面に有
する基板を用意する工程と、 基板の凹部内に間隔をおいて回路部を埋設する工程と、 各回路部の両端部それぞれと接続するように基板に間隔
をおいて引出電極を形成する工程と、 各回路部の露出部分を覆うように、且つ自らの表面高さ
が引出電極の表面高さと一致するように基板に外装を形
成する工程と、 チップ一面中央に凹部が残るように基板を個々のチップ
に分断する工程と、 引出電極それぞれと接続するようにチップに一対の外部
電極を形成する工程とを備えた、 ことを特徴とするチップ部品の製造方法。
3. A step of preparing a substrate having at least one linear concave portion on one surface, a step of burying a circuit portion at intervals in the concave portion of the substrate, and connecting to both ends of each circuit portion. Forming extraction electrodes at intervals on the substrate, and forming an exterior on the substrate so as to cover the exposed portions of the respective circuit portions and to adjust the surface height of the extraction electrodes to the surface height of the extraction electrodes. And a step of dividing the substrate into individual chips so that a concave portion remains in the center of one surface of the chip, and a step of forming a pair of external electrodes on the chip so as to be connected to the respective extraction electrodes. Manufacturing method of chip parts.
【請求項4】 基板用意工程が、未焼成セラミクス基板
に押型成形によって直線状凹部を形成するステップと、
凹部成形後の未焼成セラミクス基板を焼成するステップ
とを含む、 ことを特徴とする請求項3記載のチップ部品の製造方
法。
4. The substrate preparing step includes: forming a linear concave portion in the unfired ceramic substrate by stamping.
Baking the unfired ceramics substrate after forming the recesses.
JP9334409A 1997-12-04 1997-12-04 Chip component and manufacture thereof Withdrawn JPH11168003A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9334409A JPH11168003A (en) 1997-12-04 1997-12-04 Chip component and manufacture thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9334409A JPH11168003A (en) 1997-12-04 1997-12-04 Chip component and manufacture thereof

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JPH11168003A true JPH11168003A (en) 1999-06-22

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Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002299102A (en) * 2001-03-29 2002-10-11 Koa Corp Chip resistor
JP2014204096A (en) * 2013-04-10 2014-10-27 日本カーバイド工業株式会社 Chip resistor
JP2015019023A (en) * 2013-06-13 2015-01-29 ローム株式会社 Chip resistor and mounting structure of the same
US9859041B2 (en) 2013-06-13 2018-01-02 Rohm Co., Ltd. Chip resistor and mounting structure thereof
US10134510B2 (en) 2014-04-24 2018-11-20 Panasonic Intellectual Property Management Co., Ltd. Chip resistor and method for manufacturing same
WO2021106676A1 (en) * 2019-11-25 2021-06-03 パナソニックIpマネジメント株式会社 Chip resistor

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002299102A (en) * 2001-03-29 2002-10-11 Koa Corp Chip resistor
JP2014204096A (en) * 2013-04-10 2014-10-27 日本カーバイド工業株式会社 Chip resistor
JP2015019023A (en) * 2013-06-13 2015-01-29 ローム株式会社 Chip resistor and mounting structure of the same
US9859041B2 (en) 2013-06-13 2018-01-02 Rohm Co., Ltd. Chip resistor and mounting structure thereof
US10290401B2 (en) 2013-06-13 2019-05-14 Rohm Co., Ltd. Chip resistor and mounting structure thereof
US10586635B2 (en) 2013-06-13 2020-03-10 Rohm Co., Ltd. Chip resistor and mounting structure thereof
US11017922B2 (en) 2013-06-13 2021-05-25 Rohm Co., Ltd. Chip resistor and mounting structure thereof
US11676742B2 (en) 2013-06-13 2023-06-13 Rohm Co, Ltd. Chip resistor and mounting structure thereof
US10134510B2 (en) 2014-04-24 2018-11-20 Panasonic Intellectual Property Management Co., Ltd. Chip resistor and method for manufacturing same
WO2021106676A1 (en) * 2019-11-25 2021-06-03 パナソニックIpマネジメント株式会社 Chip resistor

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