JPH04298040A - Manufacture of integrated circuit - Google Patents
Manufacture of integrated circuitInfo
- Publication number
- JPH04298040A JPH04298040A JP8614391A JP8614391A JPH04298040A JP H04298040 A JPH04298040 A JP H04298040A JP 8614391 A JP8614391 A JP 8614391A JP 8614391 A JP8614391 A JP 8614391A JP H04298040 A JPH04298040 A JP H04298040A
- Authority
- JP
- Japan
- Prior art keywords
- main surface
- wiring layer
- semiconductor substrate
- integrated circuit
- circuit device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 29
- 239000000758 substrate Substances 0.000 claims abstract description 40
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims abstract description 30
- 238000010438 heat treatment Methods 0.000 claims abstract description 26
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 24
- 239000012298 atmosphere Substances 0.000 claims abstract description 19
- 238000000034 method Methods 0.000 claims abstract description 18
- 239000001257 hydrogen Substances 0.000 claims abstract description 14
- 229910052739 hydrogen Inorganic materials 0.000 claims abstract description 14
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims abstract description 12
- 229910052681 coesite Inorganic materials 0.000 claims abstract description 12
- 229910052906 cristobalite Inorganic materials 0.000 claims abstract description 12
- 239000000377 silicon dioxide Substances 0.000 claims abstract description 12
- 235000012239 silicon dioxide Nutrition 0.000 claims abstract description 12
- 229910052682 stishovite Inorganic materials 0.000 claims abstract description 12
- 229910052905 tridymite Inorganic materials 0.000 claims abstract description 12
- 229910052757 nitrogen Inorganic materials 0.000 claims abstract description 11
- 239000004065 semiconductor Substances 0.000 claims description 67
- 239000010410 layer Substances 0.000 claims description 54
- 239000004020 conductor Substances 0.000 claims description 15
- 239000011229 interlayer Substances 0.000 claims description 12
- 239000007789 gas Substances 0.000 claims description 9
- 229910001873 dinitrogen Inorganic materials 0.000 claims description 8
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 abstract 2
- 229910052782 aluminium Inorganic materials 0.000 abstract 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 abstract 2
- 239000010931 gold Substances 0.000 abstract 2
- 229910052737 gold Inorganic materials 0.000 abstract 2
- 239000012299 nitrogen atmosphere Substances 0.000 abstract 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract 1
- 229910052710 silicon Inorganic materials 0.000 abstract 1
- 239000010703 silicon Substances 0.000 abstract 1
- 238000007796 conventional method Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 239000006023 eutectic alloy Substances 0.000 description 3
- 239000012535 impurity Substances 0.000 description 3
- 238000005259 measurement Methods 0.000 description 3
- 230000001186 cumulative effect Effects 0.000 description 2
- 150000002431 hydrogen Chemical class 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 238000001816 cooling Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【0001】0001
【産業上の利用分野】本発明は、Siでなる半導体基板
の第1の主面上にAlでなる配線層が形成され、また、
上記半導体基板の第1の主面上に上記配線層を覆って延
長しているSiO2 でなる層間絶縁膜が形成され、さ
らに、上記半導体基板の上記第1の主面と対向している
第2の主面上にAuでなる導体層が付されている構成を
有する半導体集積回路装置の製法に関する。[Industrial Field of Application] The present invention provides a method in which a wiring layer made of Al is formed on a first main surface of a semiconductor substrate made of Si, and
An interlayer insulating film made of SiO2 is formed on the first main surface of the semiconductor substrate and extends to cover the wiring layer, and a second interlayer insulating film that is opposite to the first main surface of the semiconductor substrate is formed. The present invention relates to a method for manufacturing a semiconductor integrated circuit device having a configuration in which a conductor layer made of Au is attached on the main surface of the semiconductor integrated circuit device.
【0002】0002
【従来の技術】従来、Siでなる半導体基板の第1の主
面上にAlでなる配線層が形成され、また、上記半導体
基板の第1の主面上に上記配線層を覆って延長している
SiO2 でなる層間絶縁膜が形成され、さらに、上記
半導体基板の上記第1の主面と対向している第2の主面
上にAuでなる導体層が付されている構成を有する半導
体集積回路装置が、種々の理由で広く提案されている。
このような半導体集積回路装置を製造するにつき、従来
は、上記半導体基板の上記第1の主面上に配線層を形成
する第1の工程をとり、その第1の工程後、上記半導体
基板の上記第1の主面上に、上記配線層を覆って延長し
ているSiO2でなる層間絶縁膜を形成する第2の工程
をとり、その第2の工程後、水素と窒素との混合ガスの
雰囲気中での熱処理を行う第3の工程をとり、その第3
の工程後、上記半導体基板の上記第2の主面上に上記導
体層を形成する第4の工程をとり、その第4の工程後、
窒素ガス雰囲気中での熱処理を行う第5の工程とをとる
、という方法が提案されている。2. Description of the Related Art Conventionally, a wiring layer made of Al is formed on a first main surface of a semiconductor substrate made of Si, and a wiring layer is formed on the first main surface of the semiconductor substrate to cover the wiring layer. A semiconductor having a structure in which an interlayer insulating film made of SiO2 is formed, and a conductor layer made of Au is further attached on a second main surface facing the first main surface of the semiconductor substrate. Integrated circuit devices have been widely proposed for a variety of reasons. Conventionally, in manufacturing such a semiconductor integrated circuit device, a first step of forming a wiring layer on the first main surface of the semiconductor substrate is performed, and after the first step, the semiconductor substrate is A second step of forming an interlayer insulating film made of SiO2 extending to cover the wiring layer is performed on the first main surface, and after the second step, a mixed gas of hydrogen and nitrogen is applied. A third step is performed in which heat treatment is performed in an atmosphere.
After the step, a fourth step of forming the conductor layer on the second main surface of the semiconductor substrate is performed, and after the fourth step,
A method has been proposed that includes a fifth step of heat treatment in a nitrogen gas atmosphere.
【0003】このような従来の半導体集積回路装置の製
法によれば、第3の工程において、第1の工程で形成さ
れた配線層に含有を予儀なくされているBrなどの望ま
しくない不純物元素を水素に置換できるので、最終的に
得られる配線層を、低い断線率で得ることができる。According to such a conventional manufacturing method of a semiconductor integrated circuit device, in the third step, undesirable impurity elements such as Br, which are inevitably contained in the wiring layer formed in the first step, are removed. Since hydrogen can be substituted for hydrogen, the final wiring layer can be obtained with a low disconnection rate.
【0004】また、第5の工程において、第4の工程で
形成された導体層を、半導体基板の第2の主面側におい
て、それと共晶合金化させることができるので、導体層
を半導体基板と良好に連結しているものとして得ること
ができる。Furthermore, in the fifth step, the conductor layer formed in the fourth step can be formed into a eutectic alloy with the second main surface of the semiconductor substrate, so that the conductor layer is formed on the second main surface side of the semiconductor substrate. It can be obtained as being well connected with.
【0005】[0005]
【発明が解決しようとする課題】しかしながら、上述し
た従来の半導体集積回路装置の製法の場合、得られた半
導体集積回路装置における配線層の加熱時間に対する断
線率が、時間とともに急激に大きくなる、という欠点を
有していた。[Problems to be Solved by the Invention] However, in the case of the above-mentioned conventional method for manufacturing a semiconductor integrated circuit device, the wire breakage rate with respect to the heating time of the wiring layer in the obtained semiconductor integrated circuit device increases rapidly with time. It had drawbacks.
【0006】よって、本発明は、上述した欠点を有効に
回避し得る新規な半導体集積回路装置の製法を提案せん
とするものである。Accordingly, the present invention aims to propose a novel method for manufacturing a semiconductor integrated circuit device that can effectively avoid the above-mentioned drawbacks.
【0007】[0007]
【課題を解決するための手段】本発明による半導体集積
回路装置の製法は、Siでなる半導体基板の第1の主面
上にAlでなる配線層が形成され、上記半導体基板の第
1の主面上に上記配線層を覆って延長しているSiO2
でなる層間絶縁膜が形成され、上記半導体基板の上記
第1の主面と対向している第2の主面上にAuでなる導
体層が付されている構成を有する半導体集積回路装置を
製造するにつき、(i)上記半導体基板の上記第1の主
面上に上記配線層を形成する第1の工程をとり、(ii
)その第1の工程後、上記半導体基板の上記第1の主面
上に、上記配線層を覆って延長しているSiO2 でな
る層間絶縁膜を形成する第2の工程をとり、(iii)
その第2の工程後、上記半導体基板の上記第2の主面上
に上記導体層を形成する第3の工程をとり、(iv)そ
の第3の工程後、窒素ガスの雰囲気中での熱処理と、そ
れに続く、窒素と水素との混合ガスの雰囲気中での熱処
理とを行う第4の工程をとる。Means for Solving the Problems A method for manufacturing a semiconductor integrated circuit device according to the present invention includes forming a wiring layer made of Al on a first main surface of a semiconductor substrate made of Si, SiO2 extending over the above wiring layer on the surface
manufacturing a semiconductor integrated circuit device having a structure in which an interlayer insulating film made of is formed, and a conductor layer made of Au is attached on a second main surface opposite to the first main surface of the semiconductor substrate. (i) taking a first step of forming the wiring layer on the first main surface of the semiconductor substrate; (ii)
) After the first step, a second step is performed to form an interlayer insulating film made of SiO2 extending over the wiring layer on the first main surface of the semiconductor substrate, (iii)
After the second step, a third step of forming the conductor layer on the second main surface of the semiconductor substrate is performed, and (iv) after the third step, heat treatment in a nitrogen gas atmosphere is performed. A fourth step is followed by heat treatment in an atmosphere of a mixed gas of nitrogen and hydrogen.
【0008】[0008]
【作用・効果】本発明による半導体集積回路装置の製法
によれば、第4の工程における窒素ガスの雰囲気中での
熱処理が、従来の半導体集積回路装置の製法における第
5の工程に対応しているので、第3の工程で形成された
導体層を、半導体基板の表面において、それと共晶合金
化させることができるので、従来の半導体集積回路装置
の製法の場合と同様に、導体層を半導体基板と良好に連
結しているものとして得ることができる。[Operations and Effects] According to the method for manufacturing a semiconductor integrated circuit device according to the present invention, the heat treatment in a nitrogen gas atmosphere in the fourth step corresponds to the fifth step in the conventional method for manufacturing a semiconductor integrated circuit device. As a result, the conductor layer formed in the third step can be formed into a eutectic alloy with the semiconductor substrate on the surface of the semiconductor substrate. It can be obtained as being well connected to the substrate.
【0009】しかしながら、本発明による半導体集積回
路装置の製法の場合、第3の工程によって導体層を形成
して後、第4の工程における窒素と水素との混合ガスの
雰囲気中での熱処理も行っているので、その熱処理によ
って、導体層を、半導体基板の表面においてさらに共晶
合金化させることができ、よって、導体層を、従来の半
導体集積回路装置の製法の場合に比しより良好に、半導
体基板に連結させることができる。However, in the method for manufacturing a semiconductor integrated circuit device according to the present invention, after the conductor layer is formed in the third step, heat treatment in an atmosphere of a mixed gas of nitrogen and hydrogen is also performed in the fourth step. Therefore, by the heat treatment, the conductor layer can be further formed into a eutectic alloy on the surface of the semiconductor substrate. It can be coupled to a semiconductor substrate.
【0010】また、本発明による半導体集積回路装置の
製法によれば、第4の工程における窒素と水素との混合
ガスの雰囲気中での熱処理が、従来の半導体集積回路装
置の製法における第3の工程に対応しているので、従来
の半導体集積回路装置の製法の場合と同様に、配線層に
含有を予儀なくされているBrなどの望ましくない不純
物元素を水素に置換できるので、最終的に得られる配線
層を、従来のの半導体集積回路装置の製法の場合と同様
に低い断線率で得ることができる。Furthermore, according to the method for manufacturing a semiconductor integrated circuit device according to the present invention, the heat treatment in the atmosphere of a mixed gas of nitrogen and hydrogen in the fourth step is the third step in the conventional method for manufacturing a semiconductor integrated circuit device. As it is compatible with the manufacturing process, it is possible to replace undesirable impurity elements such as Br, which are inevitable to be included in the wiring layer, with hydrogen, as in the case of the conventional manufacturing method of semiconductor integrated circuit devices. The resulting wiring layer can be obtained with a low disconnection rate similar to the conventional manufacturing method of a semiconductor integrated circuit device.
【0011】しかしながら、本発明による半導体集積回
路装置の製法の場合、第4の工程における窒素と水素と
の混合ガスの雰囲気中での熱処理を、第3の工程で半導
体基板の第2の主面上に導体層を形成している状態で行
っているので、配線層に含有を予儀なくされているBr
などの望ましくない不純物元素を水素によって従来の半
導体集積回路装置の製法に比し十分高い置換率で置換さ
せることができ、よって、最終的に得られる配線層を、
従来の半導体集積回路装置の製法の場合に比しより低い
断線率で得ることができる。また、本発明による半導体
集積回路装置の製法の場合、上述したように、第4の工
程における窒素と水素との混合ガスの雰囲気中での熱処
理を、第3の工程で半導体基板の第2の主面上に導体層
を形成している状態で行っているので、第2の工程で形
成された層間絶縁膜によって配線層に与えるストレスを
大きく緩和させることができ、よって、最終的に得られ
る配線層を、従来の半導体集積回路装置の製法の場合に
比しより低い断線率で得ることができる。However, in the method of manufacturing a semiconductor integrated circuit device according to the present invention, the heat treatment in an atmosphere of a mixed gas of nitrogen and hydrogen in the fourth step is performed on the second main surface of the semiconductor substrate in the third step. Since the process is carried out with a conductor layer formed on top, it is inevitable that Br will be included in the wiring layer.
Undesirable impurity elements such as
A lower wire breakage rate can be obtained than in the conventional manufacturing method of a semiconductor integrated circuit device. In addition, in the method for manufacturing a semiconductor integrated circuit device according to the present invention, as described above, the heat treatment in the atmosphere of a mixed gas of nitrogen and hydrogen in the fourth step is carried out in the second step of the semiconductor substrate in the third step. Since the process is carried out with the conductor layer formed on the main surface, the stress applied to the wiring layer can be greatly alleviated by the interlayer insulating film formed in the second step, so that the final result can be reduced. The wiring layer can be obtained with a lower disconnection rate than in the conventional manufacturing method of a semiconductor integrated circuit device.
【0012】0012
【実施例】次に、本発明による半導体集積回路装置の製
法の実施例を述べよう。[Embodiment] Next, an embodiment of the method for manufacturing a semiconductor integrated circuit device according to the present invention will be described.
【0013】本発明による半導体集積回路装置の製法の
実施例は、An embodiment of the method for manufacturing a semiconductor integrated circuit device according to the present invention is as follows:
【課題を解決するための手段】の項で述べたように、S
iでなる半導体基板の第1の主面上にAlでなる配線層
が形成され、上記半導体基板の第1の主面上に上記配線
層を覆って延長しているSiO2 でなる層間絶縁膜が
形成され、上記半導体基板の上記第1の主面と対向して
いる第2の主面上にAuでなる導体層が付されている構
成を有する半導体集積回路装置を製造するにつき、(i
)上記半導体基板の上記第1の主面上に上記配線層を形
成する第1の工程をとり、(ii)その第1の工程後、
上記半導体基板の上記第1の主面上に、上記配線層を覆
って延長しているSiO2 でなる層間絶縁膜を形成す
る第2の工程をとり、(iii)その第2の工程後、上
記半導体基板の上記第2の主面上に上記導体層を形成す
る第3の工程をとり、(iv)その第3の工程後、窒素
ガスの雰囲気中での熱処理と、それに続く、窒素と水素
との混合ガスの雰囲気中での熱処理とを行う第4の工程
をとる。As mentioned in the section [Means for solving the problem], S
A wiring layer made of Al is formed on a first main surface of a semiconductor substrate made of i, and an interlayer insulating film made of SiO2 is formed on the first main surface of the semiconductor substrate and extends to cover the wiring layer. (i
) taking a first step of forming the wiring layer on the first main surface of the semiconductor substrate; (ii) after the first step;
A second step of forming an interlayer insulating film made of SiO2 extending to cover the wiring layer is performed on the first main surface of the semiconductor substrate, and (iii) after the second step, the A third step of forming the conductor layer on the second main surface of the semiconductor substrate is performed, and (iv) after the third step, heat treatment is performed in a nitrogen gas atmosphere, followed by nitrogen and hydrogen treatment. A fourth step is a heat treatment in a mixed gas atmosphere.
【0014】そして、その第1の工程におけるAlでな
る配線層の形成を、半導体基板上に、それに対する無加
熱状態で、Alでなる層をスパッタリング法によって形
成し、次でそのAlでなる層に対するマスクを用いたエ
ッチング処理を行うことによって形成した。[0014] In the first step, the wiring layer made of Al is formed by sputtering a layer made of Al on the semiconductor substrate without heating it, and then the layer made of Al is formed by sputtering. It was formed by performing an etching process using a mask.
【0015】また、第2の工程におけるSiO2 でな
る層間絶縁膜の形成を、低温堆積法によって形成した。Furthermore, the interlayer insulating film made of SiO2 in the second step was formed by a low-temperature deposition method.
【0016】さらに、第3の工程におけるAuでなる導
体層の形成を、半導体基板に対する無加熱状態で、蒸着
法によって0.3μmの厚さに形成した。Furthermore, in the third step, a conductor layer made of Au was formed to a thickness of 0.3 μm by vapor deposition without heating the semiconductor substrate.
【0017】また、第4の工程における窒素ガスの雰囲
気中での熱処理を、390〜430℃の温度範囲の温度
、なかんずく、400℃の温度で、15分間行い、また
窒素と水素との混合ガスの雰囲気中での熱処理を、39
0℃〜430℃の温度範囲における温度、なかんずく4
00℃の温度で30分間行った。[0017] Furthermore, heat treatment in a nitrogen gas atmosphere in the fourth step is carried out at a temperature in the temperature range of 390 to 430°C, particularly at a temperature of 400°C, for 15 minutes, and a mixed gas of nitrogen and hydrogen is Heat treatment in an atmosphere of 39
Temperatures in the temperature range from 0°C to 430°C, inter alia 4
The test was carried out at a temperature of 00°C for 30 minutes.
【0018】なお、第4の工程後、半導体基板を、約5
℃/秒の速度で冷却した。Note that after the fourth step, the semiconductor substrate is
Cooling was performed at a rate of °C/sec.
【0019】上述した本発明による半導体集積回路装置
の製法の実施例によれば、図1及び図2の、加熱時間に
対する見積断線率の、従来の半導体集積回路装置の製法
の場合と対比して示す測定結果からも明らかなように、
半導体集積回路装置を、配線層の断線率が従来の半導体
集積回路装置の製法の場合に比し格段的に低い断線率で
製造できた。According to the embodiment of the method for manufacturing a semiconductor integrated circuit device according to the present invention described above, the estimated wire breakage rate with respect to the heating time shown in FIGS. As is clear from the measurement results shown,
A semiconductor integrated circuit device can be manufactured with a wire breakage rate in wiring layers that is significantly lower than that in conventional semiconductor integrated circuit device manufacturing methods.
【0020】なお、図1は、0.8μmの幅と、0.5
μmの厚さと、7mmの長さを有する配線層について、
窒素ガスの雰囲気中で温度を400℃として加熱した場
合を示す。Note that FIG. 1 shows a width of 0.8 μm and a width of 0.5 μm.
For a wiring layer having a thickness of μm and a length of 7 mm,
The case is shown in which heating is performed at a temperature of 400° C. in a nitrogen gas atmosphere.
【0021】なお、図2は、1.0μmの幅と、0.5
μmの厚さと、7mmの長さを有する配線層について、
空気中で温度を400℃として加熱した場合を示す。Note that FIG. 2 shows a width of 1.0 μm and a width of 0.5 μm.
For a wiring layer having a thickness of μm and a length of 7 mm,
The case is shown when heated in air at a temperature of 400°C.
【図1】本発明による半導体集積回路装置の製法の作用
効果の説明に供する、配線層の、窒素ガス雰囲気中での
加熱時間に対する累積断線率の測定結果を、従来の半導
体集積回路装置の製法の場合と対比して示す図である。FIG. 1 shows the measurement results of the cumulative disconnection rate of a wiring layer with respect to the heating time in a nitrogen gas atmosphere, which is used to explain the effects of the method for manufacturing a semiconductor integrated circuit device according to the present invention. It is a figure shown in comparison with the case of.
【図2】本発明による半導体集積回路装置の製法の作用
効果の説明に供する、配線層の、空気中での加熱時間に
対する累積断線率の測定結果を、従来の半導体集積回路
装置の製法の場合と対比して示す図である。FIG. 2 shows the measurement results of the cumulative disconnection rate of the wiring layer with respect to the heating time in air in the case of the conventional semiconductor integrated circuit device manufacturing method, which is used to explain the effects of the semiconductor integrated circuit device manufacturing method according to the present invention. FIG.
Claims (1)
にAlでなる配線層が形成され、上記半導体基板の第1
の主面上に上記配線層を覆って延長しているSiO2
でなる層間絶縁膜が形成され、上記半導体基板の上記第
1の主面と対向している第2の主面上にAuでなる導体
層が付されている構成を有する半導体集積回路装置を製
造するにつき、上記半導体基板の上記第1の主面上に上
記配線層を形成する第1の工程をとり、その第1の工程
後、上記半導体基板の上記第1の主面上に、上記配線層
を覆って延長しているSiO2 でなる層間絶縁膜を形
成する第2の工程をとり、その第2の工程後、上記半導
体基板の上記第2の主面上に上記導体層を形成する第3
の工程をとり、その第3の工程後、窒素ガスの雰囲気中
での熱処理と、それに続く、窒素と水素との混合ガスの
雰囲気中での熱処理とを行う第4の工程をとることを特
徴とする半導体集積回路装置の製法。1. A wiring layer made of Al is formed on a first main surface of a semiconductor substrate made of Si, and a wiring layer made of Al is formed on a first main surface of a semiconductor substrate made of Si.
SiO2 extending over the main surface of the wiring layer and covering the wiring layer.
manufacturing a semiconductor integrated circuit device having a structure in which an interlayer insulating film made of is formed, and a conductor layer made of Au is attached on a second main surface opposite to the first main surface of the semiconductor substrate. To do this, a first step of forming the wiring layer on the first main surface of the semiconductor substrate is performed, and after the first step, the wiring layer is formed on the first main surface of the semiconductor substrate. A second step is performed to form an interlayer insulating film made of SiO2 extending to cover the layer, and after the second step, a second step is performed to form the conductive layer on the second main surface of the semiconductor substrate. 3
After the third step, a fourth step is performed in which heat treatment is performed in a nitrogen gas atmosphere, followed by heat treatment in a mixed gas atmosphere of nitrogen and hydrogen. A method for manufacturing a semiconductor integrated circuit device.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP8614391A JPH04298040A (en) | 1991-03-26 | 1991-03-26 | Manufacture of integrated circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP8614391A JPH04298040A (en) | 1991-03-26 | 1991-03-26 | Manufacture of integrated circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH04298040A true JPH04298040A (en) | 1992-10-21 |
Family
ID=13878508
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP8614391A Pending JPH04298040A (en) | 1991-03-26 | 1991-03-26 | Manufacture of integrated circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH04298040A (en) |
-
1991
- 1991-03-26 JP JP8614391A patent/JPH04298040A/en active Pending
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