JPS6364343A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS6364343A JPS6364343A JP20893886A JP20893886A JPS6364343A JP S6364343 A JPS6364343 A JP S6364343A JP 20893886 A JP20893886 A JP 20893886A JP 20893886 A JP20893886 A JP 20893886A JP S6364343 A JPS6364343 A JP S6364343A
- Authority
- JP
- Japan
- Prior art keywords
- film
- layer
- wiring
- interconnection
- sio2 film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 6
- 229920001721 polyimide Polymers 0.000 claims abstract description 12
- 239000000758 substrate Substances 0.000 claims abstract description 7
- 239000009719 polyimide resin Substances 0.000 claims description 9
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 23
- 229910052681 coesite Inorganic materials 0.000 abstract description 12
- 229910052906 cristobalite Inorganic materials 0.000 abstract description 12
- 229910052682 stishovite Inorganic materials 0.000 abstract description 12
- 229910052905 tridymite Inorganic materials 0.000 abstract description 12
- 239000000377 silicon dioxide Substances 0.000 abstract description 11
- 235000012239 silicon dioxide Nutrition 0.000 abstract description 11
- 239000011347 resin Substances 0.000 abstract description 4
- 229920005989 resin Polymers 0.000 abstract description 4
- 239000004642 Polyimide Substances 0.000 abstract description 3
- 238000010438 heat treatment Methods 0.000 abstract description 3
- 238000000034 method Methods 0.000 abstract description 3
- 238000001259 photo etching Methods 0.000 abstract description 2
- 238000004528 spin coating Methods 0.000 abstract description 2
- 239000000126 substance Substances 0.000 abstract description 2
- 239000010410 layer Substances 0.000 description 25
- 239000011229 interlayer Substances 0.000 description 10
- 238000004519 manufacturing process Methods 0.000 description 4
- 230000007547 defect Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 230000001681 protective effect Effects 0.000 description 2
- 241001494479 Pecora Species 0.000 description 1
- 229910020489 SiO3 Inorganic materials 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 238000005245 sintering Methods 0.000 description 1
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〈産業上の利用分野〉
本発明は８１基板上にＳ ｉＯ２膜を介してＡｌ配線を
有する半導体装置に関するものである。DETAILED DESCRIPTION OF THE INVENTION <Industrial Application Field> The present invention relates to a semiconductor device having Al wiring on an 81 substrate via a SiO2 film.
〈従来の技術〉
従来の半導体装置（２層配線デバイス）の構造を第４図
に示す。図に於いて、１ｉｔＳｉ基板、２はＳｉＯ３膜
、３は１層目のＡ４配線、４は層間絶縁膜、５は２層目
のＡｌ配線である。<Prior Art> The structure of a conventional semiconductor device (two-layer wiring device) is shown in FIG. In the figure, 1itSi substrate, 2 is a SiO3 film, 3 is A4 wiring in the first layer, 4 is an interlayer insulating film, and 5 is Al wiring in the second layer.
〈発明が解決しようとする問題点〉
しかしながら、上記従来の半導体装置；こは、層間配線
ショート不良が生じ易いという問題点かあった。<Problems to be Solved by the Invention> However, the above-mentioned conventional semiconductor device has a problem in that interlayer wiring short-circuit defects are likely to occur.
この点を第５図の製造工程図に基づき詳細に説明する。This point will be explained in detail based on the manufacturing process diagram of FIG.
（１１周知のプロセヌにより１層目のＡ４配線ＣＡｌ−
５ｉ配線等を含む）形成までを完了したＩＣ−ＬＳＩの
表面付近の断面構造を示す。(11) The first layer A4 wiring CAl-
5 shows a cross-sectional structure near the surface of an IC-LSI that has been completely formed (including 5i wiring, etc.).
（２１Ｓｉ基板１とＡ６配線３とのオーミックコンタク
トを得るために４００℃〜５００℃の温度範囲下で所定
の時間シンタリングを行う。この際ＡＪ配線表面には、
Ｓ １０２とＡｅとの熱膨張係数差により生じる膜内応
力の緩和現象の結果としてヒルロック６が発生する。(In order to obtain ohmic contact between the 21Si substrate 1 and the A6 wiring 3, sintering is performed at a temperature range of 400°C to 500°C for a predetermined time. At this time, the surface of the AJ wiring is
Hillock 6 occurs as a result of the relaxation phenomenon of intra-film stress caused by the difference in thermal expansion coefficient between S102 and Ae.
（３）層間絶縁膜４としてＣｖＤ ＳｉＯ２膜、ＳｉＮ
膜、ＰＳＧ膜等やポリイミド系樹脂層を全面に形成（成
長）させる。ヒルシロツタ上の層間絶縁１嘆は平坦部ン
こ比へ著しく薄くなり、極部ではヒルロック最上部が絶
縁膜表面に露出してしまう。(3) CvD SiO2 film, SiN as interlayer insulating film 4
A film, a PSG film, etc., and a polyimide resin layer are formed (grown) on the entire surface. The interlayer insulation layer on the hillock becomes extremely thin compared to the flat part, and the top of the hillock is exposed to the surface of the insulating film at the extreme part.
（４）２層目のＡ４配線５を形成する。この際、上記露
出部分は層間配線のショートを引き起こす。(4) Form the second layer of A4 wiring 5. At this time, the exposed portion causes a short circuit in the interlayer wiring.
また、２層目のＡ４配線とｌ石目のＡｌ配線との良好な
コンタクトを得るために再度シンクリングを行うと、ヒ
ルロックの数は更に増加し、すでに発生しているヒルロ
ックは成長する。これは層間配線ショート不良を増加さ
せる結果となる。Furthermore, when sinking is performed again to obtain good contact between the second-layer A4 wiring and the first-layer Al wiring, the number of hillocks increases further, and the hillocks that have already occurred grow. This results in an increase in interlayer wiring short-circuit defects.
本発明は上記問題点を解決し、層間配線ショートを著し
く低減させる構造を提供するものである。The present invention solves the above problems and provides a structure that significantly reduces interlayer wiring short circuits.
〈問題点を解決するための手段〉
ＳｉＯ２膜とＡ６配線との間にポリイミド系樹脂層を設
ける。<Means for solving the problem> A polyimide resin layer is provided between the SiO2 film and the A6 wiring.
く作用〉
ＳｉＯ２膜とＡ６配線との間にバッファ層としてポリイ
ミド系樹脂層を設けることにより、ＳｉＯ２とＡ６間の
熱膨張係数差により生じる膜内応力を吸収させ、Ａ６６
配線面のヒツジロックの発生を防止する。Effect> By providing a polyimide resin layer as a buffer layer between the SiO2 film and the A6 wiring, the stress in the film caused by the difference in thermal expansion coefficient between SiO2 and A6 is absorbed, and the A66
Prevents the occurrence of sheep lock on the wiring surface.
〈実施例〉 以下、実施例に基いて本発明の詳細な説明する。<Example> Hereinafter, the present invention will be explained in detail based on Examples.
第１図は本発明の一実施例（２届配線デバイヌ）の構造
を示す断面図である。FIG. 1 is a sectional view showing the structure of an embodiment of the present invention (two-way wiring device).
−に於いて、１１は８１基板、１２は５１０２換、１３
はポリイミド系樹脂層、１４は１層目のＡ ｅ配線（Ａ
６−５ｉ配線等を含む）、１５は層間絶縁膜、１６は２
層日のＡ ｅ配線である。-, 11 is 81 board, 12 is 5102 board, 13
is a polyimide resin layer, 14 is the first layer A e wiring (A
6-5i wiring, etc.), 15 is an interlayer insulating film, 16 is 2
This is the Ae wiring of Layer Day.
製造方法を第２図の製造工程図により説明する。The manufacturing method will be explained with reference to the manufacturing process diagram in FIG.
（ｌ］ Ｓ １０２嘆１２にコンタクト窓を開化する
ｎｉＪに、ポリイミド系樹脂層１３を回転塗布方式′Ｌ
こより形成し、所定の熱処理により熟的に安定な膜とす
る。(l) S 102 The polyimide resin layer 13 is applied by spin coating on the niJ that opens the contact window.
The film is formed from this, and then subjected to a prescribed heat treatment to form a stable film.
（２）周知のホトエツチング技術（プラズマ又はケミ力
／ｌ／）によりコンタクト窓１７を開孔する。(2) Open the contact window 17 using a well-known photoetching technique (plasma or chemical force/l/).
（３）１層目のＡ１１！配線１４を形成する。(3) First layer A11! Wiring 14 is formed.
以降は従来技術と同一プロセスである。すなわち、Ｓ
ｉ基板とＡ６配線とのオーミックコンタクトを得るため
にシンクリングを行い、居間絶縁１慎１５を形成し、２
層目のＡＪ配線１６を形成する。The subsequent process is the same as the conventional technology. That is, S
In order to obtain ohmic contact between the i-board and the A6 wiring, sink ring was performed to form a living room insulation layer 15, and
A layer AJ wiring 16 is formed.
以上のように、Ａ／’配線とＳ ＋ ０２慎間にバッフ
ァ層としてポリイミド系樹脂層を設けることにより、Ａ
４と８１０２間の熱膨張係数差により生ずる膜内応力は
バッファ層に吸収され、Ａ ｌ配線表面のヒルロックの
発生が防止される（第３図参照。As described above, by providing a polyimide resin layer as a buffer layer between the A/' wiring and the S + 02 line, the
The stress in the film caused by the difference in thermal expansion coefficient between 4 and 8102 is absorbed by the buffer layer, and the occurrence of hillocks on the surface of the Al wiring is prevented (see FIG. 3).
矢印＝応力）。これにより、多層配線の層間配線ショー
ト不良は著しく低域され、高歩留りのデバイス作成が可
能となる。arrow = stress). As a result, interlayer wiring short-circuit defects in multilayer wiring can be significantly reduced, making it possible to manufacture devices with high yield.
尚、単層配線デバイスに本発明を適用した場合、保護膜
形成後の熱処理に於いても保護膜にクラックの発生が無
い高信頼性デバイスの作成が可能となる。Note that when the present invention is applied to a single-layer wiring device, it is possible to create a highly reliable device in which no cracks occur in the protective film even during heat treatment after forming the protective film.
また、ポリイミド系樹脂を感光性のものにすれば、ポリ
イミド系樹脂膜をレジヌト膜として、Ｓ ｉ Ｏ２膜を
エツチングできるので、工程増にもならず上記効果が得
られる。Furthermore, if the polyimide resin is photosensitive, the SiO2 film can be etched using the polyimide resin film as a resin film, so the above effects can be obtained without increasing the number of steps.
〈発明の効果〉
以上説明したように本発明によれば、従来の問題点を解
決できる極めて有用な半導体装置が提供されるものであ
る。<Effects of the Invention> As explained above, according to the present invention, an extremely useful semiconductor device that can solve the conventional problems is provided.
第１図、第２図ｉｌ＋乃至（３；、第３図、第４図及び
第５回国乃至（４）は断面図である。
符号の説明
１１：Ｓｉ基板、１２：ＳｉＯ２膜、１３：ポリイミド
系樹脂層、１４：１層目のＡｌ配線、１５：層間絶縁膜
、１６：２層目のＡｌ配線。Fig. 1, Fig. 2 il+ to (3;, Fig. 3, Fig. 4, and Fig. 5) are cross-sectional views. Explanation of symbols 11: Si substrate, 12: SiO2 film, 13: polyimide system resin layer, 14: first layer Al wiring, 15: interlayer insulating film, 16: second layer Al wiring.
Claims (1)
る半導体装置に於いて、上記ＳｉＯ＿２膜とＡｌ配線と
の間にポリイミド系樹脂層を設けたことを特徴とする半
導体装置。1. A semiconductor device having Al wiring on a Si substrate via a SiO_2 film, characterized in that a polyimide resin layer is provided between the SiO_2 film and the Al wiring.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20893886A JPS6364343A (en) | 1986-09-04 | 1986-09-04 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20893886A JPS6364343A (en) | 1986-09-04 | 1986-09-04 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6364343A true JPS6364343A (en) | 1988-03-22 |
Family
ID=16564618
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP20893886A Pending JPS6364343A (en) | 1986-09-04 | 1986-09-04 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6364343A (en) |
-
1986
- 1986-09-04 JP JP20893886A patent/JPS6364343A/en active Pending
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