JPS5898948A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To readily form a tapered shape on the side surface of a connecting window and to enable to form Al wirings by forming a silicon oxide insulating layer on a semiconductor substrate and opening by a dry etching method a window at the insulating layer, thereby forming a connecting window with an upper layer. CONSTITUTION:After a PSG film 5 is covered on an Al wiring layer 2 of primary layer formed on a semiconductor substrate 1, an organic solution which contains silicon compound is coated with a span coater on the upper surface of the film. Subsequently, it is heat treated, thereby forming an oxidized silicon film 6. Then, a resist film 7 is coated, is patterned, thereby exposing only the connecting window forming region, a mask is coated on the other part, the films 5, 6 are then etched, and the side face of the window is formed in a tapered shape. Thereafter, the film 7 is removed, an Al wiring layer 8 is coated on the upper layer, thereby obtaining the layer 8 of the upper layer of constant thickness.

Description

Detailed Description of the Invention α) Technical Field of the Invention The present invention relates to integrated circuits (IC), large-scale integrated circuits (LSI)
, ultra-LS, I, etc., and particularly relates to a method of manufacturing a semiconductor device provided with multilayer wiring.

(2) Background of the Technology As the degree of integration increases, interconnections or interconnections with external circuits become more complex and the number of interconnections increases, resulting in the formation of multilayer wiring layers on a semiconductor substrate. When a multilayer wiring layer is formed, it becomes necessary to form a connection window (contact hole, A/) for connecting the upper and lower wiring layers to an insulating layer interposed between the wiring layers.

If such a connection window is covered with upper layer wiring, it is likely to break due to the difference in the level of the insulating layer in the connection chamber. Therefore, a window opening etching method that forms the side surface of the insulating layer in the window into a tapered shape is recommended. It is used. Various methods have been proposed in the past for this purpose, but in cases where the degree of integration is relatively low, wet etching is used to form a connection window using a simple method that creates a gentle shoulder. was.

However, as the degree of integration increases in recent years, it is necessary to form connection windows finely and with high precision. For this reason, dry etching methods are used, and in this case, vertical steps are formed on the sides of the connection windows. This increases the risk of wire breakage.

(8) Prior Art and Problems Figure 1 shows a cross-sectional view of a multilayer wiring structure that is susceptible to the above-mentioned disconnection.
1) This is a diagram in which a window is opened in an insulating layer made of a phosphosilicate glass (PSG) layer 8 and an upper Al wiring layer 4 is deposited on the wiring layer 2, and the Al wiring layer 4 is formed thinly on the side surface of the connection window. This indicates that there is a risk of wire breakage.

In order to avoid such serious failures regarding reliability, for example, a polycrystalline silicon layer is used as a wiring layer and heat treated at a high temperature (approximately 1000°C) to form a 'PSG layer 80 layer surface 0 surface and connect it. A method has been adopted in which the shoulder portions on the side surfaces of the window are made gradual, but the polycrystalline silicon layer has a high resistivity, which adversely affects the electrical characteristics, especially the response speed.

On the other hand, the AI wiring layer has a low resistivity and is ideal for wiring layers, but its melting point is low, so as shown in Figure 1, the AI! When used as a wiring structure, it is impossible to melt the PSG layer at high temperatures.

Further, other proposed taper forming methods are not necessarily satisfactory because the number of steps is increased and the patterning is delicate.

(4) Purpose of the Invention The present invention solves these problems and proposes a manufacturing method that makes it possible to easily form the side surface of the connection window into a tapered shape and also to form AI wiring. .

(5) Structure of the Invention This purpose is to form a silicon oxide insulating layer on a semiconductor substrate or on a lower wiring layer on the surface of the substrate by chemical vapor deposition (CVV).
D) After applying a nucleated solution containing a silicon compound on the top surface and heat-treating it to form a silicon oxide insulating layer, a window is formed in both of the insulating layers by a dry etching method. This can be achieved by a manufacturing method including a step of forming a connection window with the upper layer, and will be described in detail below by way of an example with reference to the drawings.

(6) Embodiment of the Invention FIGS. 2 to 4 are cross-sectional views of an embodiment of the present invention in the order of steps. First, as shown in FIG. 2, the lower layer of AI formed on one surface of a semiconductor substrate! Wiring layer (film thickness 1 Cμm11)
) 2 to KCVD method! -) PSG film (film thickness 1 [μm]
) After coating 5, methyl alcohol silicate is further applied on the top surface.
A nucleated solution containing a silicon compound such as μ is applied using a spin coater. The nucleated solution containing this silicon compound is, for example, 81(OH).

A solution is prepared by dissolving a compound with the structure of Next, when the film is heat-treated at about 800 [°C], dehydration and condensation occur to form a silicon oxide (Si, O,) film 6, whose thickness is about SOO~1000 (people).500 (t) If the heat treatment temperature is below, Al
Since its melting point is lower than 660 (°C), the A4 wiring layer will not melt.

Next, as shown in FIG. 8, a resist film 7 is applied by a photo process and patterned to expose only the connection window forming area and mask the rest.
PSGSbO was formed by a gas plasma etching method (a type of dry etching method) using
2 and Sing 116, the side surface of the connection window is formed into a tapered shape as shown in the figure. This is because the etching rate of the Sin film 6 coated and formed as described above is faster (14 to 15 times) than that of PSGSbO2, so the surface is etched to form a tapered shape.

After opening the connection window in this way, the resist film 7 is removed, and then the upper Al wiring layer 8 is removed as shown in FIG.
When it is deposited by vapor deposition, the upper A/wiring layer 8 can be obtained with a constant film thickness and no risk of disconnection because the connecting sickle shoulder portion has a gently tapered shape.

Although PSGSbO2 is used as the edge layer in the above embodiments, similar results can be obtained by using other silicon oxides such as Si or a film deposited by CVD instead. Furthermore, in addition to the 510s film 6 coated above, plasma CVD
Silicon nitride film formed by the method or Si film formed by the vapor deposition method
Similar results can be obtained with n, membrane. In addition to A4, the wiring layer is made of molybdenum gold (MO-Au), fi17 silver (rl
-Ag) or the like.

(7) Effects of the Invention As can be seen from the above description, according to the present invention, a tapered connection window can be easily formed in an insulating layer interposed between wiring layers, and the A4 multilayer wiring structure can be easily solved. Can be used without In addition, 6 layers of Sin, which are formed by coating, “
It also has a great effect of smoothing an uneven surface, and is therefore extremely effective in improving the reliability and yield of semiconductor devices having a multilayer wiring structure manufactured by the present invention.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional view of a conventional connection window, and FIGS. 2 to 4 are cross-sectional views of the manufacturing method according to the present invention. In the figure,
l is the semiconductor substrate, 2 is the lower AJI wiring layer, 3.5qP
SG film, 4,111 on top 117) l' wiring layer, 6 is a 5102 film formed from a nucleated solution containing a silicon compound, 7 is a resist film. Figure 1 Figure 2 Figure 3 Figure 4

Claims (1)

[Scope of Claims] A silicon oxide insulating layer is deposited on a semiconductor substrate or a lower layer wiring on the substrate surface by chemical vapor deposition, and a nucleated solution containing a silicon compound is further applied on the upper surface of the silicon oxide insulating layer. . A semiconductor characterized by comprising the step of forming a connection layer with the upper layer by forming a window in both of the insulating layers by a dry etching method after the silicon oxide insulating layer is sealed by heat treatment. Method of manufacturing the device.