JPH04216630A - Wiring formation of semiconductor element - Google Patents
Wiring formation of semiconductor elementInfo
- Publication number
- JPH04216630A JPH04216630A JP40264990A JP40264990A JPH04216630A JP H04216630 A JPH04216630 A JP H04216630A JP 40264990 A JP40264990 A JP 40264990A JP 40264990 A JP40264990 A JP 40264990A JP H04216630 A JPH04216630 A JP H04216630A
- Authority
- JP
- Japan
- Prior art keywords
- film
- wiring
- wiring layer
- natural oxide
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 12
- 230000015572 biosynthetic process Effects 0.000 title description 4
- 238000000034 method Methods 0.000 claims abstract description 24
- 239000000758 substrate Substances 0.000 claims abstract description 5
- 229910000676 Si alloy Inorganic materials 0.000 claims description 3
- 238000005530 etching Methods 0.000 abstract description 8
- 229910021364 Al-Si alloy Inorganic materials 0.000 abstract description 7
- 230000000694 effects Effects 0.000 abstract description 7
- 238000005229 chemical vapour deposition Methods 0.000 abstract description 5
- 238000004380 ashing Methods 0.000 abstract description 3
- 238000004140 cleaning Methods 0.000 abstract description 3
- 229910018125 Al-Si Inorganic materials 0.000 abstract description 2
- 229910018520 Al—Si Inorganic materials 0.000 abstract description 2
- 238000009792 diffusion process Methods 0.000 description 4
- 238000002161 passivation Methods 0.000 description 4
- 239000013078 crystal Substances 0.000 description 3
- 238000000206 photolithography Methods 0.000 description 3
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 2
- 238000002441 X-ray diffraction Methods 0.000 description 2
- 239000002253 acid Substances 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 239000005380 borophosphosilicate glass Substances 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 230000006911 nucleation Effects 0.000 description 2
- 238000010899 nucleation Methods 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 229910015844 BCl3 Inorganic materials 0.000 description 1
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 description 1
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 239000000460 chlorine Substances 0.000 description 1
- 229910052801 chlorine Inorganic materials 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 238000013508 migration Methods 0.000 description 1
- 230000005012 migration Effects 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 239000002994 raw material Substances 0.000 description 1
- 238000005001 rutherford backscattering spectroscopy Methods 0.000 description 1
- 238000005245 sintering Methods 0.000 description 1
- FAQYAMRNWDIXMY-UHFFFAOYSA-N trichloroborane Chemical compound ClB(Cl)Cl FAQYAMRNWDIXMY-UHFFFAOYSA-N 0.000 description 1
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【０００１】0001
【産業上の利用分野】本発明は半導体素子の配線形成の
方法に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming interconnects for semiconductor devices.
【０００２】0002
【従来の技術】半導体素子における配線の従来の構造は
、図２、図３の従来例１および２に示すように形成され
ている。以下にそれを説明する。2. Description of the Related Art Conventional wiring structures in semiconductor devices are formed as shown in Conventional Examples 1 and 2 in FIGS. 2 and 3. This will be explained below.
【０００３】まず図２の従来例１から説明すると、半導
体基板１上に絶縁膜２（例えばＢＰＳＧ膜）をＣＶＤ法
で形成し、その上に配線層となるＡｌ−Ｓｉ合金層３を
スパッタ法で形成する。First, starting with conventional example 1 shown in FIG. 2, an insulating film 2 (for example, a BPSG film) is formed on a semiconductor substrate 1 by a CVD method, and an Al-Si alloy layer 3, which will become a wiring layer, is formed on it by a sputtering method. to form.
【０００４】その配線層をホトリソグラフィ・エッチン
グ技術にてパターニングした後、パッシベーション膜（
例えばＳｉＮ膜）４をＣＶＤ法にて形成すれば、図２の
配線構造が得られる。After patterning the wiring layer using photolithography and etching technology, a passivation film (
For example, if a SiN film (4) is formed by CVD, the wiring structure shown in FIG. 2 can be obtained.
【０００５】しかしながら、半導体素子の集積度が増加
するにつれて配線幅は細くなり、１μｍ以下の幅の配線
も必要とされてくるようになってきている。そうすると
前述の従来例１の方法では、エレクトロマイグレーショ
ン、ストレスマイグレーションなどの問題が生じるので
、様々な不純物を添加して配線層の強化を図っているが
、０．５μｍレベルの配線幅では限界があり、上層の絶
縁膜を形成しただけでもその膜のストレスで断線を生じ
る。そこでＡｌ以外の金属でＡｌ配線層をカバーする方
法が考えられており、それが図３に示す従来例２である
。However, as the degree of integration of semiconductor devices increases, the wiring width becomes narrower, and wiring with a width of 1 μm or less is now required. If this happens, problems such as electromigration and stress migration will occur in the method of Conventional Example 1, so various impurities are added to strengthen the wiring layer, but there is a limit to the wiring width at the 0.5 μm level. , even if an upper insulating film is formed, stress on that film can cause wire breakage. Therefore, a method of covering the Al wiring layer with a metal other than Al has been considered, and this is the conventional example 2 shown in FIG.
【０００６】図３に示す従来例２は、半導体基板１上に
絶縁膜２を形成、Ａｌ−Ｓｉ合金配線層３を図２の従来
例１同様形成した後、選択ＷＣＶＤ法（タングステンＣ
ＶＤ法）を用いて前記配線層３の面上にのみＷ膜５を形
成して、その上にパッシベーション膜４を形成したもの
である。In the conventional example 2 shown in FIG. 3, an insulating film 2 is formed on a semiconductor substrate 1, an Al-Si alloy wiring layer 3 is formed in the same way as the conventional example 1 shown in FIG.
A W film 5 is formed only on the surface of the wiring layer 3 using the VD method, and a passivation film 4 is formed thereon.
【０００７】このような方法とすることにより、配線層
３のまわりを高融点金属であるＷ膜５で囲む形となり、
段切れのない強い配線が得られ、かつＡｌ−Ｓｉ合金の
ヒロック発生も抑制できる。By using such a method, the wiring layer 3 is surrounded by the W film 5 which is a high melting point metal,
Strong wiring with no breaks can be obtained, and the occurrence of hillocks in the Al-Si alloy can also be suppressed.
【０００８】[0008]
【発明が解決しようとする課題】しかしながら前述の従
来例２の方法で配線層を形成する場合、その配線層の上
にできる自然酸化膜がＷの核形成の障害となる。この自
然酸化膜は、主としてエッチング後レジスト除去の際の
アッシングや酸洗浄（例えば発煙硝酸）によって形成さ
れたものである。この自然酸化膜が存在すると、ＷＣＶ
Ｄ法の原料であるＷＦ６ やＳｉＨ４ が均一に吸着せ
ず、Ｗの核形成密度が極端に低くなり、薄くしたいＷ膜
が不均一に形成されてしまう。However, when a wiring layer is formed by the method of Conventional Example 2 described above, the natural oxide film formed on the wiring layer becomes an obstacle to the formation of W nuclei. This natural oxide film is mainly formed by ashing or acid cleaning (for example, fuming nitric acid) during resist removal after etching. If this natural oxide film exists, WCV
WF6 and SiH4, which are the raw materials for method D, are not uniformly adsorbed, and the W nucleation density becomes extremely low, resulting in the formation of a non-uniform W film that is desired to be thin.
【０００９】また、前処理（例えば、希ＨＦ溶液中でエ
ッチング後速やかにＣＶＤＷ膜を形成したり、真空中で
塩素系プラズマで表面をエッチングし、そのまま真空中
でＣＶＤＷ膜を形成する方法など）でＡｌの自然酸化膜
を除去して、均一なＷ膜を形成しようとする方法も考え
られているが、その場合、後工程の熱処理によって、Ａ
ｌとＷが反応してＡｌ中にＷが入り込み、Ａｌの配線抵
抗が上昇するという問題が生じる。さらにＣＶＤＷ膜（
ＷＣＶＤ法によって形成したＷ膜）自身のストレスが、
細いＡｌ−Ｓｉ合金配線に影響を与えるという問題があ
り、技術的に満足できるものではなかった。[0009] Also, pretreatment (for example, a method of forming a CVDW film immediately after etching in a dilute HF solution, etching the surface with chlorine-based plasma in a vacuum, and then forming a CVDW film in a vacuum, etc.) A method has also been considered in which a uniform W film is formed by removing the natural oxide film of Al.
A problem arises in that L and W react, W enters into Al, and the wiring resistance of Al increases. Furthermore, CVDW film (
The stress of the W film formed by WCVD method is
There was a problem that it affected thin Al-Si alloy wiring, and it was not technically satisfactory.
【００１０】0010
【課題を解決するための手段】本発明は、前述した自然
酸化膜の影響の除去と、それを除去しても、ＷがＡｌ配
線に入り込み抵抗を増大させることや、Ｗ自身のストレ
スがＡｌ配線に悪影響を与えるなどの問題点を解決する
ために、Ａｌ−Ｓｉ合金配線層を形成した後、Ａｌ配線
層上の自然酸化膜を除去し、選択ＷＣＶＤ法によってβ
−Ｗ膜を配線層の表面にのみ形成するようにしたもので
ある。後述するように、β−Ｗは通常のＷであるα−Ｗ
に比べ、酸素を吸収する特性を持っており、かつＡｌ中
に拡散しにくく、またストレスも極めて小さい。[Means for Solving the Problems] The present invention eliminates the effect of the natural oxide film mentioned above, and even if it is removed, W enters the Al wiring and increases the resistance, and the stress of W itself In order to solve problems such as adverse effects on wiring, after forming an Al-Si alloy wiring layer, the natural oxide film on the Al wiring layer was removed, and β
-The W film is formed only on the surface of the wiring layer. As will be explained later, β-W is α-W which is normal W.
Compared to aluminum, it has the property of absorbing oxygen, is difficult to diffuse into Al, and has extremely low stress.
【００１１】[0011]
【作用】本発明は前述のように、自然酸化膜を除去した
後、配線層上にβ−Ｗ膜を形成するようにしたので、Ａ
ｌと反応して配線抵抗が増大するようなこともなく、ス
トレスも小さいのでＡｌ配線に対して悪影響も与えず、
良質で強い配線が得られる。[Operation] As described above, the present invention forms a β-W film on the wiring layer after removing the natural oxide film, so that
There is no increase in wiring resistance due to reaction with Al, and the stress is small, so it does not have any negative effect on Al wiring.
Good quality and strong wiring can be obtained.
【００１２】0012
【実施例】本発明の実施例の工程を主要断面図として図
１に示し、以下に説明する。DESCRIPTION OF THE PREFERRED EMBODIMENTS The process of an embodiment of the present invention is shown in main cross-sectional view in FIG. 1, and will be described below.
【００１３】先ず図（ａ）に示すように、従来同様半導
体（ＩＣ）基板１上に絶縁膜（例えばＢＰＳＧ膜）２を
ＣＶＤ法にて５０００Å程度の厚さ形成し、その上にＡ
ｌ−Ｓｉ系合金層３をスパッタ法にて６０００Å程度の
厚さ形成し、ホトリソグラフィ・エッチング技術にてパ
ターニングして配線層３を形成する。First, as shown in Figure (a), an insulating film (for example, a BPSG film) 2 is formed to a thickness of about 5000 Å on a semiconductor (IC) substrate 1 by the CVD method as in the conventional method, and then an A
An l-Si alloy layer 3 is formed to a thickness of about 6000 Å by sputtering, and patterned by photolithography and etching to form a wiring layer 3.
【００１４】そして、エッチング後に行なわれるレジス
ト除去のアッシングや、洗浄によってできる前記配線層
３表面の自然酸化膜を除去する。この除去法は、希釈弱
酸による方法もしくはＢＣｌ３ やＣＦ４ などのガス
プラズマ法があり、いずれの方法でもよい。Then, the natural oxide film on the surface of the wiring layer 3 formed by ashing for resist removal performed after etching and cleaning is removed. This removal method may be a method using a diluted weak acid or a gas plasma method such as BCl3 or CF4, and either method may be used.
【００１５】前述のようにして自然酸化膜を除去した後
、図（ｂ）のように選択ＷＣＶＤ法により、β−Ｗ膜６
を選択的に前記配線層３の表面上にのみ３００〜５００
Å程度の厚さ形成する。このβ−Ｗ膜６の形成条件は、
温度２７５〜３２０℃、ＳｉＨ４ ／ＷＦ６ の流量比
を１．０、反応圧力を０．２〜０．３Ｔｏｒｒで行なう
。ＣＶＤ法によるＷ膜は、周知のようにその形成を行な
う条件により通常のＷであるα−Ｗ膜と、準安定相のβ
−Ｗ膜ができる。本実施例はそのβ−Ｗ膜を形成するよ
うにしたものである。以下にその特性を説明する。After removing the native oxide film as described above, the β-W film 6 is formed by selective WCVD as shown in FIG.
300 to 500 selectively only on the surface of the wiring layer 3
Form a thickness of about 1.5 Å. The conditions for forming this β-W film 6 are as follows:
The reaction is carried out at a temperature of 275 to 320°C, a flow rate ratio of SiH4/WF6 of 1.0, and a reaction pressure of 0.2 to 0.3 Torr. As is well known, the W film produced by the CVD method is composed of an α-W film, which is normal W, and a β-W film, which is a metastable phase, depending on the conditions under which it is formed.
-W film is formed. In this embodiment, the β-W film is formed. Its characteristics will be explained below.
【００１６】図４にα−Ｗとβ−ＷとのＸ線回折結果を
示す。横軸は２θで表示したＸ線の角度（Ｘ線回折で通
常表示される方法）であり、縦軸は強度である。図中（
）内の数字は結晶方位面を表わす。図から解るよう
にα−Ｗとβ−Ｗとでは結晶相が異なっている。つまり
Ｗの膜質が異なるのである。即ちβ−Ｗ膜は針状結晶構
造を持っており、大気に触れると酸素を吸収する性質を
持っている。FIG. 4 shows the X-ray diffraction results of α-W and β-W. The horizontal axis is the X-ray angle expressed in 2θ (the way it is usually expressed in X-ray diffraction), and the vertical axis is the intensity. In the figure (
The numbers in ) represent the crystal orientation plane. As can be seen from the figure, α-W and β-W have different crystal phases. In other words, the film quality of W is different. That is, the β-W film has an acicular crystal structure and has the property of absorbing oxygen when exposed to the atmosphere.
【００１７】図５はＡｌ／Ｗ構造によるＡｌ中における
Ｗの拡散係数のアレニウスプロットを示したものである
。これはＲＢＳ法（ラザフォード・バック・スキャッタ
リング法）によってＡｌ中のＷのプロファイルから求め
たものである。横軸は温度であり絶対温度の逆数で表示
したもので（上部の表示は℃）、縦軸の拡散係数である
。図から解るように、拡散係数はβ−Ｗとα−Ｗの間で
５〜１０倍違うので十分Ａｌとの反応を抑制できる。
つまりＡｌ中に拡散しにくい。FIG. 5 shows an Arrhenius plot of the diffusion coefficient of W in Al due to the Al/W structure. This was determined from the profile of W in Al using the RBS method (Rutherford back scattering method). The horizontal axis is temperature, expressed as a reciprocal of the absolute temperature (the upper display is in °C), and the vertical axis is the diffusion coefficient. As can be seen from the figure, the diffusion coefficients are different between β-W and α-W by a factor of 5 to 10, so that the reaction with Al can be sufficiently suppressed. In other words, it is difficult to diffuse into Al.
【００１８】また、これらのＷ膜のストレスは表１に示
すように、β−Ｗ膜の方がα−Ｗ膜よりはるかに小さく
Ａｌ配線に与える影響は極めて少ない。Furthermore, as shown in Table 1, the stress on these W films is much smaller in the β-W film than in the α-W film, and has very little effect on the Al wiring.
【００１９】[0019]
【表１】[Table 1]
【００２０】このようなβ−Ｗ膜６を形成した後、シン
ターを４００℃、３０分程、Ｈ２ 雰囲気で行ない、パ
ッシベーション膜（例えばＳｉＮ膜）４をＣＶＤ法にて
６０００Å程度の厚さ形成し、ホトリソグラフィ・エッ
チングを行なった後、ファイナルアニールを行なって完
成させる。また、多層配線構造の半導体素子では、この
工程を繰り返すことにより、２層目以上の配線層にも適
用できることは言うまでもない。After forming the β-W film 6, sintering is performed at 400° C. for about 30 minutes in an H2 atmosphere, and a passivation film (for example, a SiN film) 4 is formed to a thickness of about 6000 Å by CVD. After photolithography and etching, final annealing is performed to complete the process. Furthermore, in a semiconductor element having a multilayer wiring structure, it goes without saying that by repeating this process, the present invention can be applied to the second or higher wiring layers.
【００２１】[0021]
【発明の効果】以上説明したように本発明によれば、Ａ
ｌ−Ｓｉ合金配線層の自然酸化膜を除去してＷＣＶＤで
の核形成をし易くし、かつβ−Ｗ膜をその配線層表面に
形成したので、均一なＷ膜が形成されるとともに、後工
程での熱処理や膜形成時の熱でＷとＡｌが反応すること
もなく、配線抵抗の増大も生じない。また、ストレスも
極めて少ないので、細い配線に適用しても悪影響はなく
、良質で強い配線を実現できる。[Effects of the Invention] As explained above, according to the present invention, A
The natural oxide film of the l-Si alloy interconnection layer was removed to facilitate nucleation in WCVD, and the β-W film was formed on the surface of the interconnection layer, so a uniform W film was formed and the subsequent There is no reaction between W and Al due to heat treatment during the process or during film formation, and no increase in wiring resistance occurs. In addition, since the stress is extremely low, there is no negative effect even if it is applied to thin wiring, and high-quality and strong wiring can be realized.
【図１】本発明の実施例の工程断面図である。FIG. 1 is a process sectional view of an embodiment of the present invention.
【図２】従来例１の断面図である。FIG. 2 is a sectional view of Conventional Example 1.
【図３】従来例２の断面図である。FIG. 3 is a sectional view of conventional example 2.
【図４】α−Ｗ、β−Ｗの回折結果図である。FIG. 4 is a diagram showing the diffraction results of α-W and β-W.
【図５】Ａｌ中におけるＷの拡散係数のアレニウスプロ
ットを示す図である。FIG. 5 is a diagram showing an Arrhenius plot of the diffusion coefficient of W in Al.
１ ＩＣ基板 ２ 絶縁膜 ３ Ａｌ−Ｓｉ配線層 ４ パッシベーション膜 ５ β−Ｗ膜 1 IC board 2 Insulating film 3 Al-Si wiring layer 4 Passivation film 5 β-W film
Claims (1)
（ａ）半導体基板上に絶縁膜を形成し、その上にＡｌ−
Ｓｉ合金系配線層を形成する工程と、（ｂ）前記配線層
の表面に形成された自然酸化膜を除去する工程と、（ｃ
）その後β−Ｗ膜を前記配線層の表面上にのみ選択的に
形成する工程とを含むことを特徴とする半導体素子の配
線形成方法。[Claim 1] In a method for forming wiring of a semiconductor element,
(a) An insulating film is formed on a semiconductor substrate, and an Al-
a step of forming a Si alloy-based wiring layer, (b) a step of removing a natural oxide film formed on the surface of the wiring layer, and (c)
) Thereafter, a method for forming wiring in a semiconductor device, comprising the step of selectively forming a β-W film only on the surface of the wiring layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2402649A JP3040177B2 (en) | 1990-12-17 | 1990-12-17 | Semiconductor element wiring forming method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2402649A JP3040177B2 (en) | 1990-12-17 | 1990-12-17 | Semiconductor element wiring forming method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH04216630A true JPH04216630A (en) | 1992-08-06 |
| JP3040177B2 JP3040177B2 (en) | 2000-05-08 |
Family
ID=18512448
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2402649A Expired - Fee Related JP3040177B2 (en) | 1990-12-17 | 1990-12-17 | Semiconductor element wiring forming method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3040177B2 (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110310919A (en) * | 2013-12-27 | 2019-10-08 | 朗姆研究公司 | Realize the tungsten nucleation technique of low-resistivity tungsten feature filling |
| US11972952B2 (en) | 2018-12-14 | 2024-04-30 | Lam Research Corporation | Atomic layer deposition on 3D NAND structures |
| US12002679B2 (en) | 2019-04-11 | 2024-06-04 | Lam Research Corporation | High step coverage tungsten deposition |
-
1990
- 1990-12-17 JP JP2402649A patent/JP3040177B2/en not_active Expired - Fee Related
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110310919A (en) * | 2013-12-27 | 2019-10-08 | 朗姆研究公司 | Realize the tungsten nucleation technique of low-resistivity tungsten feature filling |
| US11972952B2 (en) | 2018-12-14 | 2024-04-30 | Lam Research Corporation | Atomic layer deposition on 3D NAND structures |
| US12002679B2 (en) | 2019-04-11 | 2024-06-04 | Lam Research Corporation | High step coverage tungsten deposition |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3040177B2 (en) | 2000-05-08 |
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