JPH05243225A - Semiconductor device and manufacture thereof - Google Patents

Semiconductor device and manufacture thereof

Info

Publication number
JPH05243225A
JPH05243225A JP4508792A JP4508792A JPH05243225A JP H05243225 A JPH05243225 A JP H05243225A JP 4508792 A JP4508792 A JP 4508792A JP 4508792 A JP4508792 A JP 4508792A JP H05243225 A JPH05243225 A JP H05243225A
Authority
JP
Japan
Prior art keywords
film
aluminum
platinum
wiring
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP4508792A
Other languages
Japanese (ja)
Inventor
Hiroshi Tsuda
博 津田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP4508792A priority Critical patent/JPH05243225A/en
Publication of JPH05243225A publication Critical patent/JPH05243225A/en
Withdrawn legal-status Critical Current

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  • Electrodes Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE:To increase resistance to electromigration of an aluminum interconnection. CONSTITUTION:An aluminum film 3 and a platinum film 4 are deposited in this order and are patterned. By heat treatment, these two films are alloyed to form an alloy interconnection 6. Due to the high density alloy film formed of platinum and aluminum, resistance to electromigration and resistance to stress migration of an insulating film are increased.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、半導体装置及びその製
造方法に関し、特に金属配線及びその製造方法に関す
る。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly to metal wiring and a method of manufacturing the same.

【0002】[0002]

【従来の技術】従来、半導体装置に古くから用いられて
いるアルミニウム配線は、その重大な欠点(問題点)と
して、エレクトロマイグレーション耐性が小さいことが
周知となっており、種々の改善がなされている。
2. Description of the Related Art Conventionally, it has been well known that aluminum wiring, which has been used for a long time in semiconductor devices, has a low electromigration resistance as a serious drawback (problem), and various improvements have been made. .

【0003】その第1の例は、エレクトロマイグレーシ
ョンの原因である粒界拡散を抑制するために、アルミニ
ウムに合金元素を添加するものであり、添加される不純
物金属としてCu,Ti,Si,Pd等が知られてい
る。
The first example is to add an alloying element to aluminum in order to suppress grain boundary diffusion, which is a cause of electromigration, and Cu, Ti, Si, Pd, etc. are added as impurity metals to be added. It has been known.

【0004】第2の例はアルミニウム配線の表面に絶縁
膜を被覆する方法で絶縁膜としてリンをドープした酸化
シリコン膜,酸化シリコン膜,窒化シリコン膜等が用い
られている。
The second example is a method of covering the surface of an aluminum wiring with an insulating film, and a silicon oxide film doped with phosphorus, a silicon oxide film, a silicon nitride film or the like is used as the insulating film.

【0005】また、第3の例としてアルミニウムの結晶
粒径を大きくして結晶粒界を少なくすることにより、エ
レクトロマイグレーションを低減する方法が知られてい
る。
As a third example, there is known a method of reducing electromigration by increasing the crystal grain size of aluminum to reduce the crystal grain boundaries.

【0006】[0006]

【発明が解決しようとする課題】この従来の半導体装置
では、アルミニウム系配線のエレクトロマイグレーショ
ンに対しては効果があるが、次のような問題点がある。
Although this conventional semiconductor device is effective against electromigration of aluminum-based wiring, it has the following problems.

【0007】まず、第1の例では不純物金属を含むアル
ミニウム配線の結晶粒界に析出させて拡散を抑制するた
めに不純物を含むアルミニウム膜をスパッタ法により被
着させて形成しており、そのためエッチング加工時に不
純物金属が残渣として残るという問題点がある。
First, in the first example, an aluminum film containing impurities is deposited by a sputtering method in order to deposit on the grain boundaries of aluminum wiring containing impurity metals to suppress diffusion, and therefore etching is performed. There is a problem that the impurity metal remains as a residue during processing.

【0008】また、第2の例ではアルミニウム配線を被
覆する絶縁膜により、ストレスマイグレーションを生ず
るという問題点が生ずる。
Further, in the second example, the problem that stress migration occurs due to the insulating film covering the aluminum wiring occurs.

【0009】また、第3の例では、アルミニウム配線の
結晶粒径を大きくすることは容易であるが、エッチング
加工時に結晶粒界が早くエッチングされるため、微細化
が困難である。
Further, in the third example, it is easy to increase the crystal grain size of the aluminum wiring, but it is difficult to miniaturize because the crystal grain boundaries are etched quickly during the etching process.

【0010】[0010]

【課題を解決するための手段】本発明の半導体装置は、
半導体基板上に設けてアルミニウム膜を主体とし且つア
ルミニウムと白金との合金を少くともその一部に含む配
線を備えている。
The semiconductor device of the present invention comprises:
The semiconductor device is provided on a semiconductor substrate with an aluminum film as a main component and a wiring containing an alloy of aluminum and platinum as at least a part thereof.

【0011】本発明の半導体装置の製造方法は、半導体
基板上にアルミニウム膜及び白金膜を順次積層して形成
する工程と、前記白金膜及びアルミニウム膜を選択的に
順次エッチングする工程と、熱処理により前記アルミニ
ウム膜と白金膜とを合金化して配線を形成する工程とを
含んで構成される。
A method of manufacturing a semiconductor device according to the present invention comprises a step of sequentially laminating and forming an aluminum film and a platinum film on a semiconductor substrate, a step of selectively sequentially etching the platinum film and the aluminum film, and a heat treatment. And a step of alloying the aluminum film and the platinum film to form a wiring.

【0012】[0012]

【実施例】次に、本発明について図面を参照して説明す
る。
DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

【0013】図1(a)〜(c)は本発明の一実施例の
製造方法を説明するための工程順に示した半導体チップ
の断面図である。
1 (a) to 1 (c) are cross-sectional views of a semiconductor chip showing the order of steps for explaining a manufacturing method according to an embodiment of the present invention.

【0014】まず、図1(a)に示すように、半導体基
板1の上に設けた絶縁膜2の上にスパッタ法により厚さ
1μmのアルミニウム膜3及び厚さ0.1〜0.2μm
の白金膜4を順次堆積して形成する。この時、基板の温
度は低温に保つ方が良い。次に、白金膜4の上にフォト
レジスト膜5を塗布してパターニングし、配線形成用の
マスクを形成する。
First, as shown in FIG. 1A, an aluminum film 3 having a thickness of 1 μm and a thickness of 0.1 to 0.2 μm are formed on an insulating film 2 provided on a semiconductor substrate 1 by a sputtering method.
Of the platinum film 4 are sequentially deposited and formed. At this time, it is better to keep the temperature of the substrate low. Next, a photoresist film 5 is applied on the platinum film 4 and patterned to form a wiring forming mask.

【0015】次に、図1(b)に示すように、フォトレ
ジスト膜5をマスクとして白金膜4及びアルミニウム膜
3を順次異方性エッチングしてアルミニウム膜3及び白
金膜4の2層構造を形成する。ここで、アルミニウム膜
3と白金膜4とを積層構造の状態でエッチングするた
め、残渣を生じない利点がある。
Next, as shown in FIG. 1B, the platinum film 4 and the aluminum film 3 are anisotropically etched successively using the photoresist film 5 as a mask to form a two-layer structure of the aluminum film 3 and the platinum film 4. Form. Here, since the aluminum film 3 and the platinum film 4 are etched in a laminated structure, there is an advantage that no residue is generated.

【0016】次に、図1(c)に示すように、フォトレ
ジスト膜5を除去した後150℃〜450℃の窒素雰囲
気中で熱処理し、アルミニウムと白金との合金配線6を
形成する。
Next, as shown in FIG. 1C, after removing the photoresist film 5, heat treatment is performed in a nitrogen atmosphere at 150 ° C. to 450 ° C. to form an alloy wiring 6 of aluminum and platinum.

【0017】[0017]

【発明の効果】以上説明したように本発明は、アルミニ
ウムと密度の大きい白金の合金膜を形成することによ
り、エレクトロマイグレーション耐性に優れた合金配線
を得られるという効果を有する。
As described above, the present invention has an effect that an alloy wiring excellent in electromigration resistance can be obtained by forming an alloy film of aluminum and platinum having a high density.

【0018】また、密度の大きい合金膜により、硬度が
増加するため、絶縁膜に対するストレスマイグレーショ
ン耐性も向上し、エッチング加工の際の残渣を生ずるこ
とを防止できるという効果を有する。
Further, since the alloy film having a high density increases the hardness, the resistance to stress migration with respect to the insulating film is also improved, and it is possible to prevent residues from being generated during the etching process.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の一実施例の製造方法を説明するための
工程順に示した半導体チップの断面図。
FIG. 1 is a cross-sectional view of a semiconductor chip showing the order of steps for explaining a manufacturing method according to an embodiment of the present invention.

【符号の説明】[Explanation of symbols]

1 半導体基板 2 絶縁膜 3 アルミニウム膜 4 白金膜 5 フォトレジスト膜 6 合金配線 1 Semiconductor substrate 2 Insulating film 3 Aluminum film 4 Platinum film 5 Photoresist film 6 Alloy wiring

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 半導体基板上に設けてアルミニウム膜を
主体とし且つアルミニウムと白金との合金を少くともそ
の一部に含む配線を備えたことを特徴とする半導体装
置。
1. A semiconductor device comprising a wiring which is provided on a semiconductor substrate and which mainly comprises an aluminum film and at least a part of which contains an alloy of aluminum and platinum.
【請求項2】 半導体基板上にアルミニウム膜及び白金
膜を順次積層して形成する工程と、前記白金膜及びアル
ミニウム膜を選択的に順次エッチングする工程と、熱処
理により前記アルミニウム膜と白金膜とを合金化して配
線を形成する工程とを含むことを特徴とする半導体装置
の製造方法。
2. A step of sequentially laminating and forming an aluminum film and a platinum film on a semiconductor substrate, a step of selectively sequentially etching the platinum film and the aluminum film, and a heat treatment to form the aluminum film and the platinum film. And a step of forming an interconnection to form a wiring.
JP4508792A 1992-03-03 1992-03-03 Semiconductor device and manufacture thereof Withdrawn JPH05243225A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4508792A JPH05243225A (en) 1992-03-03 1992-03-03 Semiconductor device and manufacture thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4508792A JPH05243225A (en) 1992-03-03 1992-03-03 Semiconductor device and manufacture thereof

Publications (1)

Publication Number Publication Date
JPH05243225A true JPH05243225A (en) 1993-09-21

Family

ID=12709543

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4508792A Withdrawn JPH05243225A (en) 1992-03-03 1992-03-03 Semiconductor device and manufacture thereof

Country Status (1)

Country Link
JP (1) JPH05243225A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2020174165A (en) * 2019-04-15 2020-10-22 ルネサスエレクトロニクス株式会社 Manufacturing method of semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2020174165A (en) * 2019-04-15 2020-10-22 ルネサスエレクトロニクス株式会社 Manufacturing method of semiconductor device

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A300 Withdrawal of application because of no request for examination

Free format text: JAPANESE INTERMEDIATE CODE: A300

Effective date: 19990518