JPH042976B2 - - Google Patents

Info

Publication number
JPH042976B2
JPH042976B2 JP60229537A JP22953785A JPH042976B2 JP H042976 B2 JPH042976 B2 JP H042976B2 JP 60229537 A JP60229537 A JP 60229537A JP 22953785 A JP22953785 A JP 22953785A JP H042976 B2 JPH042976 B2 JP H042976B2
Authority
JP
Japan
Prior art keywords
port
page
memory bank
address
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP60229537A
Other languages
English (en)
Japanese (ja)
Other versions
JPS6289149A (ja
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP60229537A priority Critical patent/JPS6289149A/ja
Priority to EP86902020A priority patent/EP0248906B1/en
Priority to PCT/JP1986/000136 priority patent/WO1987002488A1/ja
Priority to DE8686902020T priority patent/DE3688505T2/de
Priority to KR1019870700030A priority patent/KR880700354A/ko
Publication of JPS6289149A publication Critical patent/JPS6289149A/ja
Priority to SU874202747A priority patent/SU1561834A3/ru
Priority to US07/344,507 priority patent/US4930066A/en
Publication of JPH042976B2 publication Critical patent/JPH042976B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/1647—Handling requests for interconnection or transfer for access to memory bus based on arbitration with interleaved bank access
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/1652—Handling requests for interconnection or transfer for access to memory bus based on arbitration in a multiprocessor architecture
    • G06F13/1657—Access to multiple memories
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G06F15/173—Interprocessor communication using an interconnection network, e.g. matrix, shuffle, pyramid, star, snowflake

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Mathematical Physics (AREA)
  • Software Systems (AREA)
  • Dram (AREA)
  • Multi Processors (AREA)
  • Memory System (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
JP60229537A 1985-10-15 1985-10-15 多ポ−トメモリシステム Granted JPS6289149A (ja)

Priority Applications (7)

Application Number Priority Date Filing Date Title
JP60229537A JPS6289149A (ja) 1985-10-15 1985-10-15 多ポ−トメモリシステム
EP86902020A EP0248906B1 (en) 1985-10-15 1986-03-24 Multi-port memory system
PCT/JP1986/000136 WO1987002488A1 (en) 1985-10-15 1986-03-24 Multi-port memory system
DE8686902020T DE3688505T2 (de) 1985-10-15 1986-03-24 Multiportspeichersystem.
KR1019870700030A KR880700354A (ko) 1985-10-15 1987-01-16 다포오트 메모리 시스템
SU874202747A SU1561834A3 (ru) 1985-10-15 1987-06-12 Устройство адресации к пам ти
US07/344,507 US4930066A (en) 1985-10-15 1989-04-26 Multiport memory system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60229537A JPS6289149A (ja) 1985-10-15 1985-10-15 多ポ−トメモリシステム

Publications (2)

Publication Number Publication Date
JPS6289149A JPS6289149A (ja) 1987-04-23
JPH042976B2 true JPH042976B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) 1992-01-21

Family

ID=16893724

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60229537A Granted JPS6289149A (ja) 1985-10-15 1985-10-15 多ポ−トメモリシステム

Country Status (7)

Country Link
US (1) US4930066A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
EP (1) EP0248906B1 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
JP (1) JPS6289149A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
KR (1) KR880700354A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
DE (1) DE3688505T2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
SU (1) SU1561834A3 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
WO (1) WO1987002488A1 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)

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JPH07107792B2 (ja) * 1988-01-19 1995-11-15 株式会社東芝 マルチポートメモリ
US5146581A (en) * 1988-02-24 1992-09-08 Sanyo Electric Co., Ltd. Subprogram executing data processing system having bank switching control storing in the same address area in each of memory banks
US5247649A (en) * 1988-05-06 1993-09-21 Hitachi, Ltd. Multi-processor system having a multi-port cache memory
JP2872251B2 (ja) * 1988-10-12 1999-03-17 株式会社日立製作所 情報処理システム
US5043874A (en) * 1989-02-03 1991-08-27 Digital Equipment Corporation Memory configuration for use with means for interfacing a system control unit for a multi-processor system with the system main memory
JP2673390B2 (ja) * 1991-03-13 1997-11-05 三菱電機株式会社 マルチポートメモリ
EP0660954A1 (en) * 1992-09-21 1995-07-05 Unisys Corporation Multiported buffer memory system for disk drive complex
US5337414A (en) * 1992-09-22 1994-08-09 Unisys Corporation Mass data storage and retrieval system
AU3412295A (en) * 1994-09-01 1996-03-22 Gary L. Mcalpine A multi-port memory system including read and write buffer interfaces
KR960042372A (ko) * 1995-05-10 1996-12-21 가나이 쯔또무 멀티채널 메모리시스템, 전송정보 동기화방법 및 신호전송회로
WO1997011419A2 (en) * 1995-09-08 1997-03-27 Shablamm Computer, Inc. Synchronous multi-port random access memory
US5717646A (en) * 1996-12-05 1998-02-10 Kyi; Ben-I Random access multiport memory capable of simultaneously accessing memory cells from a plurality of interface ports
US6108756A (en) * 1997-01-17 2000-08-22 Integrated Device Technology, Inc. Semaphore enhancement to allow bank selection of a shared resource memory device
US6212607B1 (en) 1997-01-17 2001-04-03 Integrated Device Technology, Inc. Multi-ported memory architecture using single-ported RAM
US5978889A (en) * 1997-11-05 1999-11-02 Timeplex, Inc. Multiple device data transfer utilizing a multiport memory with opposite oriented memory page rotation for transmission and reception
US6874013B2 (en) 1999-05-24 2005-03-29 Koninklijke Philips Electronics N.V. Data processing arrangement and memory system
DE19937176A1 (de) * 1999-08-06 2001-02-15 Siemens Ag Multiprozessor-System
JP2002007201A (ja) * 2000-06-21 2002-01-11 Nec Corp メモリシステム、メモリインターフェース及びメモリチップ
US7143185B1 (en) * 2000-08-29 2006-11-28 Advanced Micro Devices, Inc. Method and apparatus for accessing external memories
JP2002109885A (ja) * 2000-09-28 2002-04-12 Toshiba Corp 半導体記憶装置
US7380085B2 (en) * 2001-11-14 2008-05-27 Intel Corporation Memory adapted to provide dedicated and or shared memory to multiple processors and method therefor
US6895488B2 (en) * 2002-05-22 2005-05-17 Lsi Logic Corporation DSP memory bank rotation
US7652922B2 (en) 2005-09-30 2010-01-26 Mosaid Technologies Incorporated Multiple independent serial link memory
US7747833B2 (en) * 2005-09-30 2010-06-29 Mosaid Technologies Incorporated Independent link and bank selection
KR101260632B1 (ko) 2005-09-30 2013-05-03 모사이드 테크놀로지스 인코퍼레이티드 출력 제어 메모리
US20070130374A1 (en) * 2005-11-15 2007-06-07 Intel Corporation Multiported memory with configurable ports
EP2477109B1 (en) 2006-04-12 2016-07-13 Soft Machines, Inc. Apparatus and method for processing an instruction matrix specifying parallel and dependent operations
US8059128B1 (en) * 2006-04-19 2011-11-15 Nvidia Corporation Apparatus and method for performing blit operations across parallel processors
US20100088475A1 (en) * 2006-09-26 2010-04-08 Koninklijke Philips Electronics N.V. Data processing with a plurality of memory banks
WO2008061154A2 (en) 2006-11-14 2008-05-22 Soft Machines, Inc. Apparatus and method for processing instructions in a multi-threaded architecture using context switching
US20080170571A1 (en) * 2007-01-12 2008-07-17 Utstarcom, Inc. Method and System for Synchronous Page Addressing in a Data Packet Switch
US8250312B2 (en) * 2009-04-29 2012-08-21 Micron Technology, Inc. Configurable multi-port memory devices and methods
EP2616928B1 (en) 2010-09-17 2016-11-02 Soft Machines, Inc. Single cycle multi-branch prediction including shadow cache for early far branch prediction
EP2689326B1 (en) 2011-03-25 2022-11-16 Intel Corporation Memory fragments for supporting code block execution by using virtual cores instantiated by partitionable engines
WO2012135041A2 (en) 2011-03-25 2012-10-04 Soft Machines, Inc. Register file segments for supporting code block execution by using virtual cores instantiated by partitionable engines
WO2012135031A2 (en) 2011-03-25 2012-10-04 Soft Machines, Inc. Executing instruction sequence code blocks by using virtual cores instantiated by partitionable engines
WO2012162188A2 (en) 2011-05-20 2012-11-29 Soft Machines, Inc. Decentralized allocation of resources and interconnect structures to support the execution of instruction sequences by a plurality of engines
WO2012162189A1 (en) 2011-05-20 2012-11-29 Soft Machines, Inc. An interconnect structure to support the execution of instruction sequences by a plurality of engines
CN103858386B (zh) * 2011-08-02 2017-08-25 凯为公司 用于通过优化的决策树执行包分类的方法和装置
US20150039859A1 (en) 2011-11-22 2015-02-05 Soft Machines, Inc. Microprocessor accelerated code optimizer
US10191746B2 (en) 2011-11-22 2019-01-29 Intel Corporation Accelerated code optimizer for a multiengine microprocessor
US9569216B2 (en) 2013-03-15 2017-02-14 Soft Machines, Inc. Method for populating a source view data structure by using register template snapshots
US9811342B2 (en) 2013-03-15 2017-11-07 Intel Corporation Method for performing dual dispatch of blocks and half blocks
US9904625B2 (en) 2013-03-15 2018-02-27 Intel Corporation Methods, systems and apparatus for predicting the way of a set associative cache
CN105210040B (zh) 2013-03-15 2019-04-02 英特尔公司 用于执行分组成块的多线程指令的方法
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Also Published As

Publication number Publication date
US4930066A (en) 1990-05-29
EP0248906A4 (en) 1989-08-22
JPS6289149A (ja) 1987-04-23
DE3688505T2 (de) 1993-09-09
DE3688505D1 (de) 1993-07-01
SU1561834A3 (ru) 1990-04-30
EP0248906A1 (en) 1987-12-16
KR880700354A (ko) 1988-02-22
EP0248906B1 (en) 1993-05-26
WO1987002488A1 (en) 1987-04-23

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Legal Events

Date Code Title Description
EXPY Cancellation because of completion of term