KR880700354A - 다포오트 메모리 시스템 - Google Patents

다포오트 메모리 시스템

Info

Publication number
KR880700354A
KR880700354A KR1019870700030A KR870700030A KR880700354A KR 880700354 A KR880700354 A KR 880700354A KR 1019870700030 A KR1019870700030 A KR 1019870700030A KR 870700030 A KR870700030 A KR 870700030A KR 880700354 A KR880700354 A KR 880700354A
Authority
KR
South Korea
Prior art keywords
dafot
memory system
memory
dafot memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
KR1019870700030A
Other languages
English (en)
Korean (ko)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Publication of KR880700354A publication Critical patent/KR880700354A/ko
Ceased legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/1647—Handling requests for interconnection or transfer for access to memory bus based on arbitration with interleaved bank access
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/1652—Handling requests for interconnection or transfer for access to memory bus based on arbitration in a multiprocessor architecture
    • G06F13/1657—Access to multiple memories
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G06F15/173—Interprocessor communication using an interconnection network, e.g. matrix, shuffle, pyramid, star, snowflake

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Mathematical Physics (AREA)
  • Software Systems (AREA)
  • Dram (AREA)
  • Memory System (AREA)
  • Multi Processors (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
KR1019870700030A 1985-10-15 1987-01-16 다포오트 메모리 시스템 Ceased KR880700354A (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP60229537A JPS6289149A (ja) 1985-10-15 1985-10-15 多ポ−トメモリシステム
PCT/JP1986/000136 WO1987002488A1 (en) 1985-10-15 1986-03-24 Multi-port memory system

Publications (1)

Publication Number Publication Date
KR880700354A true KR880700354A (ko) 1988-02-22

Family

ID=16893724

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019870700030A Ceased KR880700354A (ko) 1985-10-15 1987-01-16 다포오트 메모리 시스템

Country Status (7)

Country Link
US (1) US4930066A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
EP (1) EP0248906B1 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
JP (1) JPS6289149A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
KR (1) KR880700354A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
DE (1) DE3688505T2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
SU (1) SU1561834A3 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
WO (1) WO1987002488A1 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)

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JP2673390B2 (ja) * 1991-03-13 1997-11-05 三菱電機株式会社 マルチポートメモリ
JPH08501647A (ja) * 1992-09-21 1996-02-20 ユニシス・コーポレイション ディスクドライブ複合のためのマルチポートバッファメモリシステム
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WO1997011419A2 (en) * 1995-09-08 1997-03-27 Shablamm Computer, Inc. Synchronous multi-port random access memory
US5717646A (en) * 1996-12-05 1998-02-10 Kyi; Ben-I Random access multiport memory capable of simultaneously accessing memory cells from a plurality of interface ports
US6108756A (en) * 1997-01-17 2000-08-22 Integrated Device Technology, Inc. Semaphore enhancement to allow bank selection of a shared resource memory device
US6212607B1 (en) 1997-01-17 2001-04-03 Integrated Device Technology, Inc. Multi-ported memory architecture using single-ported RAM
US5978889A (en) * 1997-11-05 1999-11-02 Timeplex, Inc. Multiple device data transfer utilizing a multiport memory with opposite oriented memory page rotation for transmission and reception
US6874013B2 (en) 1999-05-24 2005-03-29 Koninklijke Philips Electronics N.V. Data processing arrangement and memory system
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JP2002007201A (ja) * 2000-06-21 2002-01-11 Nec Corp メモリシステム、メモリインターフェース及びメモリチップ
US7143185B1 (en) * 2000-08-29 2006-11-28 Advanced Micro Devices, Inc. Method and apparatus for accessing external memories
JP2002109885A (ja) * 2000-09-28 2002-04-12 Toshiba Corp 半導体記憶装置
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US6895488B2 (en) * 2002-05-22 2005-05-17 Lsi Logic Corporation DSP memory bank rotation
KR101293365B1 (ko) 2005-09-30 2013-08-05 모사이드 테크놀로지스 인코퍼레이티드 출력 제어 메모리
US7747833B2 (en) 2005-09-30 2010-06-29 Mosaid Technologies Incorporated Independent link and bank selection
US7652922B2 (en) 2005-09-30 2010-01-26 Mosaid Technologies Incorporated Multiple independent serial link memory
US20070130374A1 (en) * 2005-11-15 2007-06-07 Intel Corporation Multiported memory with configurable ports
CN101449256B (zh) 2006-04-12 2013-12-25 索夫特机械公司 对载明并行和依赖运算的指令矩阵进行处理的装置和方法
US8059128B1 (en) * 2006-04-19 2011-11-15 Nvidia Corporation Apparatus and method for performing blit operations across parallel processors
JP2010505158A (ja) * 2006-09-26 2010-02-18 コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ 複数のメモリーバンクを有するデータ処理
EP2527972A3 (en) 2006-11-14 2014-08-06 Soft Machines, Inc. Apparatus and method for processing complex instruction formats in a multi- threaded architecture supporting various context switch modes and virtualization schemes
US20080170571A1 (en) * 2007-01-12 2008-07-17 Utstarcom, Inc. Method and System for Synchronous Page Addressing in a Data Packet Switch
US8250312B2 (en) * 2009-04-29 2012-08-21 Micron Technology, Inc. Configurable multi-port memory devices and methods
KR101685247B1 (ko) 2010-09-17 2016-12-09 소프트 머신즈, 인크. 조기 원거리 분기 예측을 위한 섀도우 캐시를 포함하는 단일 사이클 다중 분기 예측
KR101966712B1 (ko) 2011-03-25 2019-04-09 인텔 코포레이션 분할가능한 엔진에 의해 인스턴스화된 가상 코어를 이용한 코드 블록의 실행을 지원하는 메모리 프래그먼트
US9766893B2 (en) 2011-03-25 2017-09-19 Intel Corporation Executing instruction sequence code blocks by using virtual cores instantiated by partitionable engines
KR101620676B1 (ko) 2011-03-25 2016-05-23 소프트 머신즈, 인크. 분할가능한 엔진에 의해 인스턴스화된 가상 코어를 이용한 코드 블록의 실행을 지원하는 레지스터 파일 세그먼트
US9940134B2 (en) * 2011-05-20 2018-04-10 Intel Corporation Decentralized allocation of resources and interconnect structures to support the execution of instruction sequences by a plurality of engines
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US9569216B2 (en) 2013-03-15 2017-02-14 Soft Machines, Inc. Method for populating a source view data structure by using register template snapshots
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US9886279B2 (en) 2013-03-15 2018-02-06 Intel Corporation Method for populating and instruction view data structure by using register template snapshots
US10275255B2 (en) 2013-03-15 2019-04-30 Intel Corporation Method for dependency broadcasting through a source organized source view data structure
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US10140138B2 (en) 2013-03-15 2018-11-27 Intel Corporation Methods, systems and apparatus for supporting wide and efficient front-end operation with guest-architecture emulation
WO2014151043A1 (en) 2013-03-15 2014-09-25 Soft Machines, Inc. A method for emulating a guest centralized flag architecture by using a native distributed flag architecture
US9891924B2 (en) 2013-03-15 2018-02-13 Intel Corporation Method for implementing a reduced size register view data structure in a microprocessor
EP2972845B1 (en) 2013-03-15 2021-07-07 Intel Corporation A method for executing multithreaded instructions grouped onto blocks
US9811342B2 (en) 2013-03-15 2017-11-07 Intel Corporation Method for performing dual dispatch of blocks and half blocks
US9760481B2 (en) 2014-06-13 2017-09-12 Sandisk Technologies Llc Multiport memory

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JPS5128450B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) * 1971-10-06 1976-08-19
US3883854A (en) * 1973-11-30 1975-05-13 Ibm Interleaved memory control signal and data handling apparatus using pipelining techniques
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US4710868A (en) * 1984-06-29 1987-12-01 International Business Machines Corporation Interconnect scheme for shared memory local networks

Also Published As

Publication number Publication date
EP0248906A1 (en) 1987-12-16
DE3688505T2 (de) 1993-09-09
EP0248906A4 (en) 1989-08-22
JPH042976B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) 1992-01-21
EP0248906B1 (en) 1993-05-26
SU1561834A3 (ru) 1990-04-30
DE3688505D1 (de) 1993-07-01
US4930066A (en) 1990-05-29
JPS6289149A (ja) 1987-04-23
WO1987002488A1 (en) 1987-04-23

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Legal Events

Date Code Title Description
PA0109 Patent application

Patent event code: PA01091R01D

Comment text: Patent Application

Patent event date: 19870116

PG1501 Laying open of application
A201 Request for examination
PA0201 Request for examination

Patent event code: PA02012R01D

Patent event date: 19880324

Comment text: Request for Examination of Application

Patent event code: PA02011R01I

Patent event date: 19870116

Comment text: Patent Application

E902 Notification of reason for refusal
PE0902 Notice of grounds for rejection

Comment text: Notification of reason for refusal

Patent event date: 19910323

Patent event code: PE09021S01D

E601 Decision to refuse application
PE0601 Decision on rejection of patent

Patent event date: 19920120

Comment text: Decision to Refuse Application

Patent event code: PE06012S01D

Patent event date: 19910323

Comment text: Notification of reason for refusal

Patent event code: PE06011S01I

J2X1 Appeal (before the patent court)

Free format text: APPEAL AGAINST DECISION TO DECLINE REFUSAL

PJ2001 Appeal

Appeal kind category: Appeal against decision to decline refusal

Decision date: 19931019

Appeal identifier: 1992201000362

Request date: 19920222