JPH04296057A - Mos semiconductor element - Google Patents

Abstract

PURPOSE:To enable a MOS semiconductor element to be lessened in ON-state resistance by a method wherein a gate electrode provided onto a semiconductor surface layer which serves as a channel region is used for the formation of an inversionlayer inside a channel region in a semiconductor layer provided onto the gate electrode through the intermediary of an insulating layer. CONSTITUTION:A second gate oxide film 61 is formed on a gate electrode 7, a polycrystalline silicon layer is deposited thereon, and a P region 11 and an N<+> source region 12 and an N<+> drain region 13 which sandwich the region 11 between them are formed. The second N channel NOSFET is made to have a threshold voltage nearly equal to that of a first N channel MOSFET by controlling a P region in impurity concentration and an oxide film 61 in thickness. The electron currents which flow when MOS semiconductor elements are in ON-states are set equal to each other as much as possible. The source region 12 of the second MOSFET is connected to a source electrode 8, and the drain region 13 is connected to a narrow N<+> contact region 14 provided onto the surface layer of an N<-> layer 2 with a second drain electrode 15.

Description

[Detailed description of the invention]

0001

[Industrial Field of Application] The present invention is applicable to, for example, MOSFET,
The present invention relates to a MOS type semiconductor element, such as a conductivity modulated MOSFET (IGBT) or a MOS controlled thyristor (MCT), which has a MOS structure on a semiconductor body and whose main current is controlled by applying a voltage to a gate electrode.

0002

[Prior Art] Currently, the power semiconductor device that is attracting the most attention in the field of power electronics is the power MO
It can be said that they are SFET and IGBT. These are currently considered to be the most suitable elements for downsizing and improving the performance of power electronics products. This is due to the high-speed switching performance and low drive power of both. However, the unstoppable expansion, miniaturization, and higher performance of power electronics products require even lower loss and higher frequency power semiconductor devices. FIG. 2 shows the relationship between the specific on-resistance of power MOSFETs on the market, that is, the product of the turn-on resistance Ron and the area A. Lower on-resistance of power MOSFETs has been achieved on the low breakdown voltage side by increasing the channel width by improving cell integration using microfabrication technology of LSI process technology. (“Low on-Resis
tance and High Reality
y Power MOSFETs"PESC '88
(Refer to RECORD, APRIL 1988) There are also reports that the on-resistance is reduced by further increasing the degree of integration using a trench gate structure. (”NUMERICAL
AND EXPERIMENTAL COMPARI
SON OF 60V VERTICAL DOUBL
E-DIFFUSED MOSFETS AND MO
SFETS WITH A TRENCH-GATE
STRUCTURE” Solid-State El
electronics, Vol. 32, NO. 3,19
89)

On the other hand, the on-voltage of the IGBT is given by the following equation. VCE (sat) = VJ (p+ -n-) +V
MOD +I・RS +IMOS (Ra +Rj
+Rch) (1) Here, VJ (p+ -n
−) is the p+ collector of the n-channel IGBT and the n−
The diffusion potential of the high resistance region, VMOD is the voltage drop of the conductivity modulated region of the n- high resistance region, RS is the other series resistance, and (Ra+Rj +Rch) is the MO
Resistance Ra of storage layer of SFET section, junction F
This is the sum of the resistance Rj of the ET section and the channel resistance Rch. FIG. 3 shows the analytically determined on-voltage component of the IGBT. In such IGBTs as well, reducing the on-resistance of the MOSFET section is the most important factor. This is because in order to avoid the latch-up phenomenon, it is necessary to increase the impurity concentration and depth of the region where the channel is formed, which necessitates a significant increase in channel resistance. Therefore, efforts are being made to increase the cell integration density of IGBTs and reduce the on-resistance. ("Improved electricalCha
racteristics trade-off be
tween VCE(sat) and tf”P
OWER Conversion June 1990
Proceedings)

0004

[Problems to be Solved by the Invention] However, each method of reducing on-resistance by increasing the degree of integration has its own problems. FIG. 4 shows a trench gate structure MOSFET, with n
+ Drain layer 1, n drift layer 2, p base layer 3
, a trench 20 selectively formed from the surface of a silicon substrate having four layers, p+ layer 4, penetrating through n+ source region 5 and reaching n drift layer 2,
A gate electrode 7 is provided with a gate oxide film 6 interposed therebetween. A source electrode 8 commonly contacts p+ layer 4 and n+ region 5, and a drain electrode 9 contacts n+ layer 1. However, in such a trench gate structure,
Electric field concentration occurs at the tip of the gate electrode 7 at the bottom of the trench 20, making it difficult to increase the withstand voltage, making it difficult to ensure the quality of the gate oxide film 6 at the trench gate part, and furthermore, There are many problems to be solved, such as a significant decrease in mobility due to crystal damage during trench processing that remains in the channel portion of the opposing p base layer 3. On the other hand, high-precision photolithography technology is indispensable for improving the degree of integration through mere microfabrication, which requires expensive manufacturing equipment that is exactly equivalent to VLSI technology. Furthermore, especially 500
For high voltage MOSFETs and IGBTs with a voltage higher than V, there is an optimum cell size, and unnecessarily reducing the cell size will result in an increase in the on-state voltage. Figure 5 is a MOSFE
The relationship between cell dimensions (accumulation layer width) of T and specific on-resistance RonA is shown, where the accumulation layer width is the interval between channel regions on the substrate surface. In Figure (a), the high resistance layer width is 4.6
Figure (b) is a device with a breakdown voltage of 100 V and a channel length of 0.3 μm in μm.The high-resistance layer width is 73 μm and the channel length is 1 μm.
The element has a breakdown voltage of 1000 V, S is the width of the p+ well, and RD is the resistance of the drift layer. Although reducing the size of the p+ well as shown in the figure is effective in reducing its on-voltage, the breakdown resistance due to the latch-up phenomenon in the case of IGBTs is significantly reduced.

The purpose of the present invention is to maintain optimal cell dimensions and achieve high accuracy, in view of the difficulties in reducing the on-voltage by increasing the degree of integration through trench gate structures or miniaturized structures. It is an object of the present invention to provide a MOS type semiconductor device which does not require any manufacturing equipment and has increased cell density and reduced on-resistance without causing a decrease in breakdown voltage.

[0006]

[Means for Solving the Problems] In order to achieve the above object, the MOS type semiconductor device of the present invention includes a high resistivity layer of a first conductivity type and a surface layer on one side of the high resistivity layer. a selectively formed first region of a second conductivity type; a second region of a first conductivity type selectively formed in a surface layer of the first region; the second region and the high specific resistance; a gate electrode provided on the channel region with an insulating film interposed therebetween, and a gate electrode provided on the opposite side of the channel region with an insulating film interposed therebetween; a semiconductor layer in which a third region of the second conductivity type is sandwiched between fourth and fifth regions of the first conductivity type on both sides facing the gate electrode, the first region, and the second region; a fourth region is connected to the gate electrode, a fifth region is connected to the high resistivity layer, and when a predetermined voltage is applied to the gate electrode, the channel region and the third It is assumed that an inversion layer of the first conductivity type is simultaneously generated in the region. and,
Such a MOS type semiconductor device includes a MOSFET in which a low resistance layer of a first conductivity type is adjacent to the other surface of a high resistivity layer of a first conductivity type, and another main electrode is in contact with the low resistivity layer; Alternatively, a low resistivity layer of a second conductivity type is adjacent to the other surface of the high resistivity layer of the first conductivity type, either directly or via a low resistivity layer of the first conductivity type, and another main electrode is connected to the low resistivity layer. There is an IGBT that contacts the

[0007]

[Operation] The MOS type semiconductor device according to the present invention has a high specific resistance semiconductor layer of the first conductivity type, a first region of the second conductivity type formed on the surface layer, and a high resistivity semiconductor layer of the first conductivity type, as in the conventional device. In addition to the first MOSFET structure consisting of a second region and a gate electrode provided on the first region with an insulating film interposed therebetween, the second MOSFET structure includes a second region and a gate electrode provided on the opposite side of the gate electrode with an insulating film interposed therebetween. There is a second MOSFET structure consisting of a third region of conductivity type and fourth and fifth regions of first conductivity type, with the third region serving as a channel region, and the two MOSFET parts have the same threshold voltage. has. Then, when a voltage higher than the threshold voltage is applied, the two MOS
If almost the same current flows through the channel region of the FET section, the resistance component of the channel section can be reduced by about half with the same cell size and chip size as in the past. Especially in IGBT,
Since the MOS portion accounts for a large component in the on-voltage, the effect of the present invention is even greater than that of a MOSFET. Now, considering n-channel IGBT, n-channel IGB
T is a wide base pnp bipolar transistor
Its operation can be qualitatively considered to be driven by the electron base current flowing through the channel MOSFET. Considering an ideal case in which the electron currents flowing through the two MOSFET sections according to the present invention are equal, the collector current IC is Ih
is the hole current of pnp transistor, Ie is MOSF
Assuming that the electron current per ET element is IC = Ih
+2Ie. Ih = (αpnp / (1
−αpnp ))・2Ie, so IC = (
2/(1-αpnp))·Ie, which means that twice as much current can flow. Therefore, a significant reduction in the on-state voltage of the IGBT can be achieved.

[0008]

[Embodiment] Figure 1 shows a power MOSFE according to an embodiment of the present invention.
T, and parts common to those in FIG. 4 are given the same reference numerals. A p base amount 3 and a p+ well 4 are selectively formed in the surface layer of the n− drift layer 2 on the n+ drain layer 1 which is in contact with the drain electrode 9 connected to the drain terminal D.
is formed, and n+ is selectively formed in the surface layer of these p regions.
A source region 5 is formed. A gate electrode 7 connected to the gate terminal G is provided on the surface of the p region 3 sandwiched between the n+ region 5 and the n− layer 2 via a gate oxide film 6, and the p+ region 4 and the n+ region 5 The source electrode 8 commonly connected to the source terminal S is in contact with the gate electrode 7 and is insulated by the insulating film 10, which is the same as the structure of the conventional vertical DMOSFET. In addition to this structure, a second gate oxide film 61 is formed on the gate electrode 7, a polycrystalline silicon layer is further deposited on it, and impurities are diffused to form the p region 11 and the n+ source region 12 sandwiching it. , n+ drain region 13 is formed. The second n-channel MOSFET formed in this way has n- layer 2, p region 3, n+ region 5,
It is made to have a threshold voltage almost equal to the threshold voltage of the first n-channel MOSFET consisting of gate oxide film 6 and gate electrode 7, and the electron current flowing when turned on is made to have a value as close as possible. Second MOSFE
The source region 12 of T is connected to the source electrode 8, and the drain region 13 is a narrow n+
A second drain electrode 15 is connected to the contact region 14 . Therefore, the equivalent circuit becomes as shown in FIG. When a positive voltage is applied to the gate electrode 7 of this MOSFET and exceeds the threshold voltage, both the first and second MOSFETs enter the on state, and electrons pass through the channel region 3 on one side.
The other side passes through the channel region 11 and forms the n- drift layer 2.
and is attracted to the n+ drain layer 1 by the positive drain voltage.

FIG. 7 shows another embodiment, in which parts common to those in FIG.
The n+ region 13 fills the contact hole opened in the insulating film 10 and contacts the contact region 14 without using the contact region 14. In these MOSFETs, the on-resistance is significantly reduced, especially when the breakdown voltage is low. For example, the on-resistance of a low-voltage MOSFET in the 100 V or lower class has been reduced by about 20%.

Although the above embodiments have been described with respect to a vertical DMOSFET, they can also be implemented in an IGBT in which a p+ layer is provided through an n+ buffer layer instead of the n+ layer 1 or without an n+ buffer layer, and the on-voltage can be significantly increased. It is possible to significantly increase the impurity concentration and depth of the region where the channel is formed while keeping the on-voltage the same, making it possible to achieve high latch-up resistance. It can also be implemented in MCT.

[0011]

[Effects of the Invention] According to the present invention, the conventional MOSFET,
The gate electrode provided on the channel region of the semiconductor body surface layer of a MOS type semiconductor device such as IGBT is also used to form an inversion layer in the channel region of the semiconductor layer provided further above the gate electrode via an insulating film. By making the threshold voltages of the MOSFET formed on the surface of the semiconductor body and the MOSFET formed on the gate electrode approximately equal and making the on-state currents comparable, the MOSFETs are connected in parallel. The current supplied into the element body through the inversion layer is approximately twice that of the conventional one, so the resistance of the channel portion is approximately halved.
It is possible to significantly reduce the on-resistance or on-voltage without changing the cell dimensions or increasing the chip size, and it is also effective in improving the latch-up resistance of the IGBT.

[Brief explanation of drawings]

FIG. 1: Power n-channel MOSF of one embodiment of the present invention
Cross-sectional view of main parts of ET

[Figure 2] Relationship diagram between power MOSFET breakdown voltage and Ron・A product

[Figure 3] Relationship diagram between IGBT breakdown voltage and calculated on-voltage component

[Figure 4] Cross-sectional view of trench gate MOSFET

[Figure 5]
Relationship diagram between MOSFET cell dimensions and on-voltage

[Figure 6]
Equivalent circuit diagram of MOSFET in Figure 1

FIG. 7 is a sectional view of a main part of a power n-channel MOSFET according to another embodiment of the present invention.

[Explanation of symbols]

1 n+ drain layer 2 n- drift layer 3 P base region 4 p+ well 5 n+ source area 6 Gate oxide film 61 Second gate oxide film 7 Gate electrode 8 Source electrode 9 Drain electrode 11 p region 12 n+ source area 13 n+ drain region

Claims (4)

[Claims] 1. A high resistivity layer of a first conductivity type, a first region of a second conductivity type selectively formed in a surface layer on one side of the high resistivity layer, and a surface of the first region. A second region of the first conductivity type selectively formed in the layer, and a portion of the first region sandwiched between the second region and the high resistivity layer as a channel region and insulated over the channel region. A gate electrode is provided through a film, and a third region of a second conductivity type is formed on the opposite side of the gate electrode from the channel region with an insulating film interposed therebetween, and a third region of a second conductivity type is formed on the opposite side of the gate electrode with the first conductivity type on both sides. The fourth area of the type,
A semiconductor layer sandwiched between the fifth region and the first region,
one main electrode in common contact with the second region, a fourth region is connected to the gate electrode, a fifth region is connected to the high resistivity layer, and when a predetermined voltage is applied to the gate electrode, the channel region and an inversion layer of the first conductivity type simultaneously formed in the third region. 2. The MOSFET according to claim 1, wherein a low resistance layer of the first conductivity type is adjacent to the other surface of the high resistivity layer of the first conductivity type, and another main electrode is in contact with the low resistance layer. MOS type semiconductor device. 3. A conductivity modulated MOSFET in which a second conductivity type low resistivity layer is adjacent to the other surface of the first conductivity type high resistivity layer, and another main electrode is in contact with the low resistivity layer. A MOS type semiconductor device according to claim 1. 4. A low resistivity layer of a second conductivity type is provided on the other surface of the high resistivity layer of the first conductivity type via a low resistivity layer of the first conductivity type, and the low resistivity layer of the second conductivity type is provided with a low resistivity layer of the second conductivity type. The M according to claim 1, which is a conductivity modulation type MOSFET in which another main electrode is in contact with the resistivity layer.
OS type semiconductor device.