JPH0429329A - Field effect transistor and its manufacture - Google Patents

Abstract

PURPOSE:To obtain high breakdown strength with simple constitution by forming a high resistance region, where oxygen ions are implanted, on the channel region below a gate electrode or on the channel region between a gate and a drain. CONSTITUTION:A resist 30 to become a mask is formed on a semiinsulating substrate 10, and silicon ions implantation 41 and subsequently oxygen ion implantation 42, shallower than it, are performed. Next, a resist to become a mask anew is formed, and silicon ion implantation 43 in high concentration is performed. After removal of the resist 31, it is heat-treated at high temperature to recrystallize the ion implantation region, whereby a channel region 11 and, on the surface side, a high resistance region 12 and a contact region 2 are formed. As a result, high breakdown strength can be obtained with simple constitution.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to field effect transistors, particularly gallium arsenide field effect transistors and methods of manufacturing the same.

Conventional technology Gallium arsenide field effect transistors (hereinafter referred to as GaAs MESFETs) that use a Schottky electrode for the gate have the following advantages compared to conventional silicon transistors:
It is excellent in terms of high speed, high frequency, and high efficiency, and has been developed and put into practical use in various ways. However, field effect transistors (S 1M08F
Since the gate is a Schottky electrode, the breakdown voltage is lower than that of the ET, making it difficult to use as a large input transistor. Also, the gate of GaAs MESFET
The drain-to-drain breakdown voltage or gate-to-source breakdown voltage is determined by the carrier concentration near the surface of the electrically conductive (hereinafter referred to as channel) region, but in normal silicon ion implantation, carriers are concentrated on the channel surface side, resulting in a high It is difficult to obtain a device with high withstand voltage, and countermeasures have been taken by increasing the distance between the gate and drain or between the gate and source, or by lowering the carrier concentration. However, these treatments
It reduces its own characteristics, especially its high frequency characteristics,
It has been impossible to fabricate a high-voltage FET without deteriorating high-frequency characteristics. A conventional example of a general GaAs MESFET is shown in FIG.

A channel region is formed on a semi-insulating substrate IO by implanting silicon ions, and contact regions 2 are formed at both ends thereof by implanting silicon ions at a concentration of 10,000. A Schottky electrode 7 serving as a gate electrode and an ohmic electrode 8 serving as a drain/source electrode are formed on each region.

Problems to be Solved by the Invention However, with the above configuration, it is difficult to obtain a high gate breakdown voltage as described above, or to obtain a high gate-drain breakdown voltage or gate-source breakdown voltage without degrading high frequency characteristics. That was difficult.

The present invention greatly improves the above-mentioned problems, and it is possible to obtain a high gate breakdown voltage using a process similar to the conventional method, and to achieve a high gate-to-drain breakdown voltage or gate-source breakdown voltage without deteriorating high frequency characteristics. GaAsMESFE to obtain
The purpose of this invention is to provide the structure of T and its manufacturing method.

Means for Solving the Problems In order to solve the above problems, the GaAsMESFE of the present invention
T is characterized by forming a high resistance region implanted with oxygen ions on the channel region under the gate electrode or on the channel region between the gate and drain in order to lower the carrier concentration on the surface side of the channel region. .

Operation The GaAs MESFET having the above structure has a simple structure and can obtain a high gate breakdown voltage, a high gate-drain breakdown voltage, or a gate-source breakdown voltage without deteriorating high frequency characteristics. Additionally, compared to conventional processes, the manufacturing process only requires the addition of an oxygen ion implantation process, which reduces development and manufacturing costs and requires fewer process changes.

Embodiments Hereinafter, embodiments of the present invention will be explained based on FIGS. 1 to 7.

FIG. 1 shows a GaAs MES in the first embodiment of the present invention.
FIG. 2 is a block diagram showing the FET, and a process diagram showing the manufacturing method thereof. As shown in FIG. 2, a resist 30 serving as a mask is formed on a GaAs semi-insulating substrate 1O, and silicon ion implantation 41 is performed, followed by oxygen ion implantation 42 to a shallower depth. Next, resist 31 becomes a new mask.
, and high-degree silicon ion implantation 43 is performed. After removing the resist 3I, heat treatment (hereinafter referred to as annealing) is performed at a high temperature to recrystallize the ion implanted region to form a channel region 11, a high resistance region I2 on the surface side, and a contact region 2. Finally, ohmic electrodes 8, 8d, which will become drain and source electrodes, and Schottky electrode 7, which will become gate electrode, are formed to form the GaAs of the present invention.
MESFET is completed. Note that in this embodiment, not only the gate breakdown voltage but also the gate-drain and gate-source breakdown voltages are improved.

Here, in order to demonstrate the effectiveness of oxygen ion implantation, various characteristics of GaAs implanted with oxygen ions will be described in detail based on experimental results. FIG. 3 is a distribution diagram showing the difference in carrier concentration in the channel region depending on the presence or absence of oxygen ion implantation. The horizontal axis indicates the depth from the substrate surface, and the vertical axis indicates the relative amount of ions (impurity amount) during ion implantation or the carrier concentration after annealing. In the case of only silicon ion implantation, silicon diffused to the surface due to annealing, increasing the carrier concentration near the surface. However, by implanting oxygen ions into the surface side, the carrier concentration in that region decreases, and a channel region that looks like it is buried inside is formed. This is due to oxygen atoms capturing electrons through annealing. Therefore, by implanting oxygen ions in an amount commensurate with the amount of silicon ions, the carrier concentration in that portion decreases and the resistance increases. Furthermore, if silicon ions are implanted at a higher concentration as in the contact region of the present invention, the resistance will be reduced again. Also, GaAsM
The high frequency characteristics of an ESFET are most affected by the portion of the channel region where the carrier concentration is highest, so if the maximum value of the carrier concentration is not changed as in the present invention, the high frequency characteristics will not deteriorate.

FIG. 4 is a photoluminescence intensity distribution diagram showing changes in the crystal state of the oxygen ion implanted region.

The upper row shows the spectrum of GaAs, the middle row shows the spectrum of GaAs after oxygen ion implantation, and the lower row shows the spectrum of GaAs after annealing. As seen in the figure, the crystallinity of GaAs is destroyed by oxygen ion implantation, but
Recrystallize by annealing. Therefore, it can be seen that it is possible to form a Schottky electrode on the oxygen ion implantation region.

FIG. 5 shows the difference in the current (I)-voltage (V) characteristics of the gate depending on whether or not oxygen ions were implanted directly under the gate. The broken line in the figure is the IV characteristic of a normal Schottky electrode, and the solid line is the IV characteristic in the case of having a high-resistance region formed by implanting oxygen ions directly under the gate according to the present invention. It can be seen that the effect of the present invention clearly improves the breakdown voltage of the gate electrode.

FIG. 6 shows a GaAs MESF according to a second embodiment of the present invention.
FIG. 7 is a block diagram showing the ET and a process diagram showing its manufacturing method.

In the second embodiment, oxygen ion implantation is performed on the channel region between the gate and the drain and between the gate and the source to improve the breakdown voltage thereof. 7th
As shown in the figure, a resist 30 serving as a mask is formed on a GaAs semi-insulating substrate 10, and silicon ion implantation 4 is performed.
Do 1. Next, a gate Schottky electrode 17 made of a high melting point metal is formed, and using this as a mask, oxygen ions are implanted into the periphery. Subsequently, similarly to the first embodiment, high-concentration silicon ion implantation 43 is performed and annealing is performed to recrystallize the ion implanted region, thereby forming the channel region 21. A high resistance region 22 and a contact region 2 are formed on the front side. Finally, ohmic electrodes 8 which will become drain and source electrodes are formed to form the GaAs MES of this example.
FET is completed.

Effects of the Invention As described above, the GaAs MESF having the structure of the present invention
ET has a simple configuration and can achieve high gate breakdown voltage, gate-drain breakdown voltage, or It is possible to obtain gate-source breakdown voltage. Furthermore, compared to conventional processes, the manufacturing process only requires the addition of an oxygen ion implantation process, reducing development and manufacturing costs and reducing process changes.

[Brief explanation of drawings]

FIG. 1 shows a GaAs MESF according to a first embodiment of the present invention.
Fig. 2 is a cross-sectional view of the structure of the ET, Fig. 2 is a process cross-sectional view showing its manufacturing method, Fig. 3 is a distribution diagram showing the difference in carrier concentration in the channel depending on the presence or absence of oxygen ion implantation, and Fig. 4 is a diagram showing the difference in carrier concentration in the channel depending on the presence or absence of oxygen ion implantation. A photoluminescence intensity distribution diagram showing changes in the crystal state due to heat treatment, Figure 5 is a diagram of gate current/voltage characteristics with and without oxygen ion implantation, and Figure 6 is a configuration showing a GaAs MESFET according to a second embodiment of the present invention. A cross-sectional view, FIG. 7 is a process cross-sectional view showing the manufacturing method,
FIG. 8 is a block diagram showing a conventional GaAs MESFET. 2...Contact area, 7.17...
Shut key electrode, 8.8d...source,
Drain ohmic electrode, IO...semi-insulating substrate, 11. 21...Channel area, 12.2
2... High resistance region, 30.31... Resist, 41.43... Silicon ion implantation,
42...Oxygen ion implantation. Name of agent: Patent attorney Shigetaka Awano (Source: 1 person)
: Lacey Mitsuku Den I Konui Hen - Bakuden Chaberu fI Aishida Rem Kane Sho jl Resistants - # Robbed Ion Eiri 3rd Figure ↑ Surface Deep Tube 5 Skin Length (λ) No. Power (I) Kotobuki

Claims (4)

[Claims] (1) A semi-insulating gallium arsenide substrate, an electrically conductive region formed on the substrate, a gate electrode formed on the electrically conductive region, and at least a structure formed between the gate electrode and the electrically conductive region. and a high resistance region of gallium arsenide containing oxygen atoms as impurities. (2) A step of implanting silicon ions onto a semi-insulating gallium arsenide substrate to form an electrically conductive region, and implanting oxygen ions shallower than the silicon ions into at least a portion of the electrically conductive region to increase resistance. a step of forming a region;
A method for manufacturing a field effect transistor, comprising the step of forming a gate electrode on the high resistance region. (3) a semi-insulating gallium arsenide substrate, an electrically conductive region formed on the substrate, a gate electrode and a drain electrode formed on the electrically conductive region, and at least the gate electrode on the electrically conductive region; A field effect transistor comprising a high resistance region of gallium arsenide containing oxygen atoms as an impurity formed between the drain electrode and the drain electrode. (4) A step of implanting silicon ions onto a semi-insulating gallium arsenide substrate to form an electrically conductive region, a step of forming a gate electrode on the electrically conductive region, and at least a gate electrode and a drain on the electrically conductive region. A method for manufacturing a field effect transistor, comprising the step of implanting oxygen ions more shallowly than the silicon ions to form a high resistance region.