JPH04288843A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH04288843A JPH04288843A JP3041528A JP4152891A JPH04288843A JP H04288843 A JPH04288843 A JP H04288843A JP 3041528 A JP3041528 A JP 3041528A JP 4152891 A JP4152891 A JP 4152891A JP H04288843 A JPH04288843 A JP H04288843A
- Authority
- JP
- Japan
- Prior art keywords
- bonding pad
- base film
- bonding
- contact area
- unevenness
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 13
- 238000001312 dry etching Methods 0.000 abstract description 4
- 230000000694 effects Effects 0.000 abstract description 3
- 238000010586 diagram Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 210000002784 stomach Anatomy 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05556—Shape in side view
- H01L2224/05558—Shape in side view conformal layer on a patterned surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4807—Shape of bonding interfaces, e.g. interlocking features
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/4845—Details of ball bonds
- H01L2224/48451—Shape
- H01L2224/48453—Shape of the interface with the bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/1015—Shape
- H01L2924/10155—Shape being other than a cuboid
- H01L2924/10157—Shape being other than a cuboid at the active surface
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Abstract
Description
【０００１】0001
【産業上の利用分野】この発明は、半導体装置に係り、
特にチップの電極とパッケージの電極とを接続するボン
ディング部の構造に関するものである。[Industrial Application Field] The present invention relates to a semiconductor device.
In particular, it relates to the structure of a bonding part that connects the electrodes of the chip and the electrodes of the package.
【０００２】0002
【従来の技術】図３は例えば４ＭダイナミックＲＡＭ等
の従来の半導体装置のボンディングパッド部の構成を示
す断面図である。図において、１はチップ（図示せず）
上に形成された下地膜、２はこの下地膜１上に形成され
た金属性のボンディングパッド、３はこのボンディング
パッド２上に例えば熱圧着法等により接合されたＡｕ
またはＡｌ 等の接続ワイヤであり、他端はパッケージ
の電極等のような外囲器端子（図示せず）に接合されて
いる。2. Description of the Related Art FIG. 3 is a sectional view showing the structure of a bonding pad portion of a conventional semiconductor device such as a 4M dynamic RAM. In the figure, 1 is a chip (not shown)
2 is a metal bonding pad formed on the base film 1, and 3 is an Au bonded to the bonding pad 2 by, for example, thermocompression bonding.
Alternatively, it is a connecting wire made of Al, etc., and the other end is joined to an envelope terminal (not shown) such as an electrode of a package.
【０００３】0003
【発明が解決しようとする課題】従来の半導体装置はボ
ンディング部が以上のように構成されているので、ワイ
ヤボンディング作業を行う際に、ボンディングパッド２
が下地膜１から剥がれ機能上支障を来すという問題点が
あった。この発明は上記のような問題点を解消するため
になされたもので、ワイヤボンディング作業を行っても
、ボンディングパッドが下地膜から剥がれることなく機
能上支障を来すことのない半導体装置を提供することを
目的とするものである。[Problems to be Solved by the Invention] Since the bonding portion of the conventional semiconductor device is constructed as described above, when performing wire bonding work, it is difficult to connect the bonding pad 2.
There was a problem in that the film peeled off from the base film 1, causing functional problems. This invention was made to solve the above-mentioned problems, and provides a semiconductor device in which the bonding pads do not peel off from the base film and do not cause functional problems even when wire bonding is performed. The purpose is to
【０００４】0004
【課題を解決するための手段】この発明に係る半導体装
置は、ボンディングパッドまたはその下地膜の少なくと
もいずれか一方に凹凸を有したものである。SUMMARY OF THE INVENTION A semiconductor device according to the present invention has irregularities on at least one of a bonding pad or a base film thereof.
【０００５】[0005]
【作用】この発明における半導体装置のボンディングパ
ッドまたは下地の凹凸は、ボンディングパッドと下地と
の接触面積を大にして、ボンディングパッドと下地との
間の接合力を強化する。[Operation] The unevenness of the bonding pad or the base of the semiconductor device according to the present invention increases the contact area between the bonding pad and the base and strengthens the bonding force between the bonding pad and the base.
【０００６】[0006]
【実施例】以下、この発明の一実施例における半導体装
置を図について説明する。図１において、１１はチップ
（図示せず）上に形成された下地膜で、図２に示すよう
なホトマスク１２を用いて異方性ドライエッチングによ
りパターニングされ形成された凹部１１ａ および凸部
１１ｂ を有している。１３はこの下地膜１１上に形成
されたボンディングパッドで、下地膜１１との接触面は
下地膜１１の凹部１１ａ および凸部１１ｂ に沿って
接合されており、反対側の上面には下地膜１１の凹部１
１ａ および凸部１１ｂ に対応して凹凸が形成されて
いる。１４はボンディングパッド１３の凹凸上に接合さ
れたＡｕ またはＡｌ 等の接続ワイヤであり、他端は
パッケージの電極等のような外囲器端子（図示せず）に
接合されている。DESCRIPTION OF THE PREFERRED EMBODIMENTS A semiconductor device according to an embodiment of the present invention will be described below with reference to the drawings. In FIG. 1, reference numeral 11 denotes a base film formed on a chip (not shown), which has concave portions 11a and convex portions 11b formed by patterning by anisotropic dry etching using a photomask 12 as shown in FIG. have. Reference numeral 13 denotes a bonding pad formed on the base film 11, and the contact surface with the base film 11 is bonded along the concave part 11a and the convex part 11b of the base film 11, and the base film 11 is formed on the upper surface of the base film 11 on the opposite side. recess 1
Concave and convex portions are formed corresponding to the convex portions 1a and 11b. Reference numeral 14 denotes a connection wire made of Au or Al that is bonded to the uneven surface of the bonding pad 13, and the other end is bonded to an envelope terminal (not shown) such as an electrode of a package.
【０００７】上記のように構成されたこの発明の一実施
例における半導体装置においては、ホトマスク１２を用
いて異方性ドライエッチングによりパターニングされた
下地膜１１の凹部１１ａ および凸部１１ｂ に沿って
ボンディングパッド１３は接合されているので、従来装
置における下地膜１とボンディングパッド２との接合に
比較し、接触面積は大幅に増大しており接合力も強化さ
れるため、ワイヤボンディング作業時にボンディングパ
ッド１３が下地膜１１から剥がれることもなくなる。In the semiconductor device according to an embodiment of the present invention configured as described above, bonding is performed along the concave portions 11a and convex portions 11b of the base film 11, which are patterned by anisotropic dry etching using the photomask 12. Since the pad 13 is bonded, the contact area is significantly increased and the bonding force is strengthened compared to the bonding between the base film 1 and the bonding pad 2 in conventional equipment, so the bonding pad 13 is bonded during wire bonding work. Peeling from the base film 11 is also prevented.
【０００８】また、ボンディングパッド１３の上面には
、下地膜１１のパターンに従って凹凸が形成されるので
、ボンディングパッド１３と接続ワイヤ１３との接触面
積も増大し接合力は強化される。尚、上記一実施例にお
いては、下地膜１１に凹部１１ａ および凸部１１ｂ
を形成したものについて説明したが、ボンディングパッ
ド１３側に凹凸を形成しても良く、この場合は下地膜１
１がボンディングパッド１３の凹凸に沿って接合される
ので同様の効果を有する。又、上記一実施例では、下地
膜１１を異方的にドライエッチングしパターンを形成し
たが、ウエットエッチング等により等方的に下地膜１１
をエッチングしパターンを形成しても良い。さらに、上
記一実施例では、矩形状に凹凸を形成しているが、三角
形状、波形状等のように平面形状に比較し接触面積が増
大するような形状のものであれば良いことは言うまでも
ない。Furthermore, since the upper surface of the bonding pad 13 is formed with unevenness according to the pattern of the base film 11, the contact area between the bonding pad 13 and the connecting wire 13 is increased, and the bonding force is strengthened. Incidentally, in the above embodiment, the base film 11 has a concave portion 11a and a convex portion 11b.
Although the explanation has been given on the case where the bonding pad 13 is formed, unevenness may be formed on the bonding pad 13 side.
Since bonding pad 1 is bonded along the unevenness of bonding pad 13, it has a similar effect. Further, in the above embodiment, the base film 11 is anisotropically dry etched to form a pattern, but the base film 11 is isotropically etched by wet etching or the like.
A pattern may be formed by etching. Furthermore, in the above embodiment, the irregularities are formed in a rectangular shape, but it goes without saying that any shape that increases the contact area compared to a flat shape, such as a triangular shape or a wavy shape, may be used. stomach.
【０００９】[0009]
【発明の効果】以上のように、この発明によればボンデ
ィングパッドまたはその下地膜のいずれか一方に凹凸を
形成したので、ボンディングパッドと下地膜との接触面
積が増大して接合力が強化され、ワイヤボンディング作
業を行っても、ボンディングパッドが下地膜から剥がれ
ることもなく、機能上支障を起こすことのない半導体装
置を提供することかできる。[Effects of the Invention] As described above, according to the present invention, since irregularities are formed on either the bonding pad or its base film, the contact area between the bonding pad and the base film is increased and the bonding force is strengthened. Therefore, it is possible to provide a semiconductor device in which the bonding pads do not peel off from the base film even when wire bonding is performed, and there is no functional problem.
【図１】この発明の一実施例における半導体装置のボン
ディング部の構成を示す断面図である。FIG. 1 is a cross-sectional view showing the configuration of a bonding portion of a semiconductor device in an embodiment of the present invention.
【図２】図１における下地膜の凹凸をドライエッチング
により形成するために用いられるホトマスクの構成を示
す図である。FIG. 2 is a diagram showing the configuration of a photomask used to form the unevenness of the base film in FIG. 1 by dry etching.
【図３】従来の半導体装置のボンディング部の構成を示
す断面図である。FIG. 3 is a cross-sectional view showing the configuration of a bonding part of a conventional semiconductor device.
１１ 下地膜 １１ａ 凹部 １１ｂ 凸部 １３ ボンディングパッド １４ 接続ワイヤ 11 Base film 11a Recessed part 11b Convex part 13 Bonding pad 14 Connection wire
Claims (1)
の少なくともいずれか一方に凹凸を有したことを特徴と
する半導体装置。1. A semiconductor device characterized in that at least one of a bonding pad or a base film thereof has irregularities.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3041528A JPH04288843A (en) | 1991-03-07 | 1991-03-07 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3041528A JPH04288843A (en) | 1991-03-07 | 1991-03-07 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH04288843A true JPH04288843A (en) | 1992-10-13 |
Family
ID=12610905
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3041528A Pending JPH04288843A (en) | 1991-03-07 | 1991-03-07 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH04288843A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5309025A (en) * | 1992-07-27 | 1994-05-03 | Sgs-Thomson Microelectronics, Inc. | Semiconductor bond pad structure and method |
| US6348416B1 (en) * | 1998-12-24 | 2002-02-19 | Shinko Electric Industries Co., Ltd | Carrier substrate for producing semiconductor device |
| KR100734250B1 (en) * | 2001-01-09 | 2007-07-02 | 삼성전자주식회사 | Bonding pad of semiconductor memory device for improving adhesive strength bonding pad and bonding wire and method of manufacturing the same |
-
1991
- 1991-03-07 JP JP3041528A patent/JPH04288843A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5309025A (en) * | 1992-07-27 | 1994-05-03 | Sgs-Thomson Microelectronics, Inc. | Semiconductor bond pad structure and method |
| US6348416B1 (en) * | 1998-12-24 | 2002-02-19 | Shinko Electric Industries Co., Ltd | Carrier substrate for producing semiconductor device |
| US6700198B2 (en) * | 1998-12-24 | 2004-03-02 | Shinko Electric Industries Co., Ltd. | Resin for semiconductor wire |
| KR100734250B1 (en) * | 2001-01-09 | 2007-07-02 | 삼성전자주식회사 | Bonding pad of semiconductor memory device for improving adhesive strength bonding pad and bonding wire and method of manufacturing the same |
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