JPH04288840A - Mos semiconductor device of ldd structure and manufacture thereof - Google Patents

Abstract

PURPOSE:To enhance breakdown strength of an MOS semiconductor in LDD structure by allowing a drain region to have three stage offset structure consisting of a low concentration region, middle concentration region, and a high concentration region and the low concentration region to project from a side wall to the drain side. CONSTITUTION:A drain region comprises a low concentration region 6 which occupies a side wall 9 of an electrode 4 and a region extending outward from there, a middle concentration region 8 which is positioned outside the low concentration region 6 and provides a higher impurity concentration, and a high concentration region 11 which is positioned outside the middle concentration region 8 and provides a higher impurity concentration. As the drain goes to the channel side, the concentration is lowered by three stages. Since the most inner side low concentration region 6 extends out-wardly from the lower part of the side wall, the length of the low concentration region in its channel direction is greater than the thickness of the side wall. It is, there fore possible to increase the amount of extending the depletion layer for that portion and raises its breakdown strength in its turn.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a MOS semiconductor device with an LDD structure and a method of manufacturing the same, and more particularly to a MOS semiconductor device with a high breakdown voltage LDD structure and a method of manufacturing the same.

0002

2. Description of the Related Art In a MOS semiconductor device having an LDD structure, a lightly doped drain region and a lightly doped source region are formed by doping an element formation region with impurities using a gate electrode as a mask, and then sidewalls are formed on the sides of the gate electrode. By doping impurities using the sidewalls and gate electrodes as masks, offset high concentration drain regions and high concentration source regions are formed. A MOS semiconductor device with such an LDD structure is
The generation of hot carriers can be suppressed, and characteristic deterioration due to hot carriers can be prevented.

By the way, several attempts have been made to increase the withstand voltage of a MOS semiconductor device having an LDD structure, and FIG. 5 is a sectional view showing one of the attempts. Figure 5
The MOS semiconductor device shown in FIG.
An n- type region c is formed between a lightly doped region a and an n+ type drain region b.

According to such a MOS semiconductor device, the edge of the drain region b on the channel side has a three-step staircase shape, and the electric field due to the voltage applied between the drain and the substrate is relaxed in three steps. Low concentration (n--) region a
and high concentration (n+) region b, there is an intermediate concentration (n-
), the electric field is relaxed through the intermediate concentration region c. Therefore, not only the generation of hot carriers can be reduced compared to the conventional method, but also the breakdown voltage can be increased.

[0005]

However, according to the conventional high voltage MOS semiconductor device shown in FIG. 5, there is a limit to the increase in voltage resistance. This is because the n-type region 9 is located below the sidewall d, so the n-type region a
This is because the width of the depletion layer is limited by the thickness of the sidewall d, the edge of the highly doped drain b is located close to the edge of the gate electrode e, and there is a limit to the extension of the depletion layer extending from the drain to the channel side. be.

The present invention has been made to solve these problems, and an object of the present invention is to increase the withstand voltage of a MOS semiconductor device having an LDD structure.

[0007]

[Means for Solving the Problems] According to the present invention, the drain region has a three-stage offset structure consisting of a low concentration region, a medium concentration region, and a high concentration region, and the low concentration region protrudes from the sidewall toward the drain side. It is characterized by the following.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The MOS semiconductor device and method of manufacturing the same according to the present invention will be explained in detail below according to the illustrated embodiments. FIG. 1 is a sectional view showing one embodiment of the MOS semiconductor device of the present invention. 1 is a p-type semiconductor substrate, 2 is a field insulating film formed by selectively oxidizing the surface of the semiconductor substrate 1, 3 is a gate insulating film, 4 is a silicon gate electrode, and 5 is an n-type light The doped source region 6 is an n-type lightly doped drain region, which is formed simultaneously with the lightly doped source region 5 by ion implantation using the gate electrode 4 as a mask.

Reference numeral 7 denotes an n- type source region, and 8 denotes an n- type drain region, which are formed simultaneously with the n- type source region 7 by implanting impurity ions using the gate electrode 4 and the resist film as masks. The diffusion depth is deeper than that of the n-type lightly doped drain region 6.

9 is a Si formed on the side surface of the gate electrode 4.
This is a sidewall made of O2. The channel side edge of the n-type drain region 8 is shifted considerably outward from the edge of the sidewall 9, and therefore the n-type lightly doped drain region 6 is shifted considerably outward from below the sidewall 9. It's growing. 10 is n+
11 is an n+ type drain region,
These are formed by implanting impurity ions to mask the gate electrode 4 and the resist film after forming the sidewall 9, and have a deeper diffusion depth than the n- type drain region 7.

The drain of this MOS semiconductor device has an n- type lightly doped drain region (low concentration region) 6 and an n- type lightly doped drain region (low concentration region) 6.
It consists of a type drain region (medium concentration region) 8 and an n+ type drain region (high concentration region) 11, and the outer peripheral edge of the drain is formed in the shape of three steps. The innermost n-type lightly doped drain region 6 extends considerably outward from below the sidewall 9. Therefore, according to the present MOS semiconductor device, since the length of the n-type lightly doped drain region 6 in the channel direction is considerably longer than the thickness of the sidewall 9, the n-type lightly doped drain region 6 is extended from the drain to the channel side by the reverse bias drain voltage. The allowable amount of extension of the depletion layer becomes large, and as a result, the withstand voltage becomes considerably high.

FIGS. 2 to 4 show the MOS of the present invention shown in FIG.
FIG. 1 is a cross-sectional view showing a method for manufacturing a semiconductor device in order of steps. (1) Form a field insulating film 2 by selectively oxidizing the surface of a p-type semiconductor substrate 2, form a gate insulating film 3 and a gate electrode 4, and use the gate electrode 4 as a mask to form a field insulating film 2 on the semiconductor substrate 2. An n--type source region 5 and an n--type drain region 6 are formed by ion-implanting impurities into the surface portion. FIG. 2 shows the state after regions 5 and 6 are formed. (2) Next, as shown in FIG. 3, a resist film 12 is formed to mask at least the n- type drain region 6 except for the part where the n- type drain region 8 is to be formed, and in this state, impurity By doping, an n- type source region 7 and an n- type sidewall 8 are formed. (3) Next, after sidewalls 9 are formed on the side surfaces of the gate electrode 4, a resist film 13 is formed as shown in FIG.
---type drain region 6 and n--type drain region 8,
The area where the n+ type drain region 11 is to be formed is masked, and impurities are doped in that state to form the n+ type drain region 11.
A type source region 10 and an n+ type sidewall 11 are formed. As a result, the MOS semiconductor device shown in FIG. 1 is completed.

[0013]

[Effects of the Invention] The present invention provides a drain region that has a low concentration region that occupies a region below the sidewall of a gate electrode and a region extending outward from there as appropriate, and a drain region that is located outside the low concentration region and has a high impurity concentration. It is characterized by consisting of a medium concentration region and a high concentration region located outside the medium concentration region and having a high impurity concentration. Therefore, according to the present invention, the drain is formed so that the concentration decreases in three steps toward the channel side, and the innermost low concentration region extends from below the sidewall to the outside.
The length of the lightly doped drain region in the channel direction is considerably longer than the thickness of the sidewall. Therefore, the amount by which the depletion layer extends can be increased accordingly, and the withstand voltage can be increased considerably.

[Brief explanation of the drawing]

FIG. 1 is a sectional view showing one embodiment of a MOS semiconductor device of the present invention.

FIG. 2 is a cross-sectional view showing the first step of the method for manufacturing the MOS semiconductor device of the present invention shown in FIG. 1;

3 is a sectional view showing a second step of the method for manufacturing the MOS semiconductor device of the present invention shown in FIG. 1; FIG.

FIG. 4 is a cross-sectional view showing the third step of the method for manufacturing the MOS semiconductor device of the present invention shown in FIG. 1;

FIG. 5 is a sectional view showing main parts of a conventional example.

[Explanation of symbols]

1 Semiconductor substrate 4 Gate electrode 6 Low concentration area 8 Medium concentration area 9 Sidewall 11 High concentration area

Claims (2)

[Claims] 1. The drain region includes a low concentration region that occupies a region below the sidewall of the gate electrode and a region extending outward from the sidewall, and a medium concentration region that is located outside the low concentration region and has a high impurity concentration. , a high concentration region having a high impurity concentration located outside the medium concentration region, and a MOS semiconductor device having an LDD structure. [Claim 2]
forming at least a low concentration region of the drain by doping an impurity into the element formation region of the semiconductor substrate using the gate electrode as a mask; selectively masking at least the low concentration region of the drain with a resist film; and forming at least a medium concentration region of the drain by doping an impurity into the element formation region of the semiconductor substrate using the gate electrode as a mask, and forming at least the low concentration region of the drain after forming sidewalls on the sides of the gate electrode. selectively masking the medium concentration region with a resist film, and doping an impurity into the element formation region of the semiconductor substrate using the resist film, the gate electrode, and the sidewall as a mask to form at least a high concentration region of the drain; 2. The method of manufacturing a MOS semiconductor device having an LDD structure according to claim 1, comprising: