JPH0427249A - Demodulating device - Google Patents

Abstract

PURPOSE:To demodulate the FSL modulating signal by executing its delay detection by an optimal delay quantity by multiplying an input signal by a frequency shift clock. CONSTITUTION:An A/D converter 101 converts a signal 100 to digital data. A clock 107 shifts the digital data to an arbitrary frequency. A first multiplier 106 executes multiplication of the digital data and the clock 107. A band pass filter 108 fetches only an arbitrary frequency component from an output of the multiplier 106. A delay buffer 102 delays the digital data by T seconds (T = ntau : (n) is an arbitrary natural number) and outputs it. A second multiplier 103 multiplies and outputs data outputted from a filter 108 and the buffer 102, respectively. A low-pass filter 104 eliminates a high frequency component of the output of the multiplier 103. A deciding device 105 decides a sine code of output data of the filter 104, and outputs '0' and '1' as a demodulating signal when it is positive, and negative, respectively. A block surrounded by a broken line is that which executes a delay detection.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a demodulation device, and particularly to a demodulation device using digital signal processing.

[Conventional technology]

In recent years, modem equipment has become popular due to its low cost.

Data communication using public telephone networks has become popular.

In normal personal computer communications, the bit rate is becoming higher in order to increase the amount of data and reduce the number of calls. on the one hand,
There are fields where the amount of data is not so large and a low bit rate is sufficient, and in such fields, a low-cost FSX modem is combined with a microcomputer etc. into a single chip, and low-cost,
There is a movement to realize space saving. The present invention provides a demodulator suitable for realizing a high-performance FSX modem (modem) in such a highly integrated digital and analog mixed LSI.

A delay detection method is one of the demodulation methods for FSK modulated signals. In F'SK modulation, the modulation code "QIZll"
The frequency of the carrier wave changes from fl to f2 in response to ``l''.A change in frequency means a change in the way the phase advances.If the center frequency fc is the average of fl and f2, then (f + < f , < f 2. f.

(f+f2)/2) Based on the center frequency f, when the modulation code is "0" (fl), the frequency of the modulated wave is low, so the phase is delayed, and the modulation code becomes "l++(f2)".
), the frequency of the modulated wave is high, so the phase advances. In the delayed detection method, a modulated code is detected by measuring the phase difference of carrier waves with a time difference (delay) of a certain length.

Demodulation using a conventional differential detection method will be explained with reference to the drawings.

FIG. 2 is a diagram showing the configuration of a conventional differential detection method.

In FIG. 2, 200 is an FSX modulated signal (fl=800Hz, f2=1000Hz) with an input signal. 201 is A/I) + Nno < for a certain period of time (τ seconds = 1/ (7200Hz))
Convert each data into digital data. Delay buffer 202
is a buffer that delays the digital data by T seconds (T=nτ: n is an arbitrary natural number) and outputs the digital data. A multiplier 203 multiplies the digital data output from the A/D converter and the delayed digital data output from the delay buffer and outputs the result. 204 is a low-pass filter that removes high frequency components from the output of the multiplier.

The determiner 205 determines the sign of the output data of the low-pass filter, and if it is positive, it will be "0", if it is negative, it will be "l".
This circuit outputs the demodulated signal 210 as a demodulated signal 210.

A conventional delay detection method will be explained below using FIG. 2 and mathematical expressions.

Assuming that the input signal 200 is Acos (ωt),
The signal obtained by delaying the input signal by T seconds, ie, the output of the delay buffer 202, is Acos (ω(1-T)).

When these two signals are multiplied by the multiplier 203, the following result is obtained.

Acos (ωt) ・Aocs (ω(t-T))=
A2 cos (ωt)・(cos (ωt)+sin
(ωt)・sin (ωT))=A2・(cos2(
ωt) ・cos ((IJT) ten cos (ωt)
・sin (ωt) ・sin (ωT))...
...(1) Formula %Formula %() Here, the first term of formula (2) is a function uniquely determined by delay jlT and angular frequency ω, and the second term of formula (2) is a function determined by the input It is a function of an angular frequency that is twice the angular frequency ω of the signal. The signal output from the multiplier 203, that is, the signal expressed by equation (2), is input to a low-pass filter 204. The low-pass filter 204 functions to remove the signal in the second term of equation (2). .

Therefore, the output signal of the low-pass filter 204 can be regarded as a function of only the first term of equation (2).

Here, two modulation frequencies (f+=800Hz.

f2=1000Hz), the center frequency fc=900Hz, and the value of the first term C05 ((IJT) in equation (2) is "0".
(2πfe=π/2+πm2m=0,1,2...f
Set the delay amount T so that it satisfies the function of cT=fc*nr=1/44m/2 (T=2τ=2/72
00: n=2. l+2m=1), then, as shown in FIG. 3, the phase difference between the two frequencies to be determined, fI=800Hz and center frequency fe of f2=1000Hz, is expressed by the sine sign of the output data of the low-pass filter 204. Ru. In other words, the input modulation code is “0”
(f, = 800Hz), the output of cos (ωlT) is positive, and the input modulation code is “l” (f2
= 1000Hz), the output of cos (ω2T) is negative. Therefore, the determiner 205 outputs "0" as the output signal 210 (demodulation result) if the sine sign of the output data of the low-pass filter is positive, and "1" if it is negative.

With the above operation, the conventional delay detection method demodulates the FSX modulated signal.

Then the two modulation frequencies are f + = 1650 Hz
.

When f2=1850Hz, the A/D conversion rate is τ seconds=
The case of 1/ (7200H2) will be described.

Modulation frequency is f, = 1650Hz, f2 = 1850Hz
When the center frequency fe=1750Hz, the value of the first term cos ((IJT) in equation (2) is “0” (2Kf,
T=yr/2+rrm, m=0.1.2-f, T=f,
*Set the delay [LT so as to satisfy the relationship of nτ = 1/4 + m/2 (T = 36 * τ = 36/720
0: when n=36.1+2m=35) Then, the fourth
As shown in the figure, the center frequency f to be determined is not insignificant, but two modulation frequencies f+=1650Hz and fz=18
Even at 50 Hz, the value of CO3((IJT) is 0". In other words, even if the input modulation code is "0°" (f+), the output of the low-pass filter 204 is "l" ( f2) is also "0", and the determiner 205 is unable to perform normal demodulation.

[Problem to be solved by the invention]

In modulation/demodulation equipment that has multiple data transfer rates, it is common for a single digital signal processing LSI to perform all demodulation processing for each transfer rate in order to reduce costs. be. In such cases, the timing clock given to the digital signal processing LSI is often selected to be compatible with a faster modulation/demodulation method (transfer rate), and the clock required for A/D conversion is also This timing clock is often used.

Therefore, the modulation frequency explained in the conventional example is L=1650H.
z, fz=1850Hz, A/D conversion rate τ=
As in the case of l/7200 seconds, in FSX demodulators using conventional delay detection methods, a delay that is an integral multiple of the A/D conversion rate cannot necessarily be adapted to the optimal delay amount of the modulation frequency for which delay detection is to be performed. First, it has the disadvantage of not being able to perform optimal demodulation.

[Means to solve the problem]

An A/D converter that converts an input analog signal into digital data and outputs it; a converter that is used to shift the digital data to an arbitrary frequency; and a multiplier that multiplies the digital data and the frequency shift clock. a first multiplier for extracting an arbitrary frequency component from the output of the first multiplier, a delay buffer for delaying and outputting the output of the bandpass filter, and output data of the bandpass filter. a second multiplier that performs multiplication with the output data of the delay buffer; a low-pass filter that extracts a low frequency component from the output of the second multiplier; and a demodulated signal that determines the frequency from the output data of the low-pass filter. It consists of a judger that outputs.

〔Example〕

The present invention will be explained with reference to the drawings.

FIG. 1 is a configuration diagram of an embodiment of the present invention.

In FIG. 1, 100 is a signal FSX modulated with an input signal. 101 is an A/D converter and the FSK
The modulated signal is converted into digital data at fixed time intervals (τ seconds). A clock 107 is used to shift the digital data to an arbitrary frequency. 10
6 is a first multiplier that multiplies the digital data and the frequency shift clock 107; 108
is a bandpass filter, which extracts only an arbitrary frequency component from the output of the first multiplier. The delay buffer 102 stores the digital data for T seconds (T=n
τ: n is an arbitrary natural number) This is a buffer that outputs with a delay. A second multiplier 103 multiplies the data output from the band pass filter and the data output from the delay buffer and outputs the result. 104 is a low-pass filter that removes high frequency components from the output of the multiplier.

The determiner 105 is a circuit that determines the sign of the output data of the low-pass filter, and outputs "0" if it is positive, and "l" if it is negative, as the demodulated signal 110. In FIG. The block shown in FIG. 1 is a circuit that operates in the same manner as the delay detection method described in the conventional example, and performs delay detection on the output signal of the bandpass filter 108.

The delayed detection method of this embodiment will be explained below using FIG. 1 and mathematical expressions.

Suppose that the input signal 100 is Acos (2πfit).

If the clock 107 used to shift digital data to an arbitrary frequency is Acos(2πf,), then (
f+=f+ rh), and when these two signals are multiplied by the first multiplier 106, the following is obtained.

Acos (2πfat) ・Acos (2πfr
t) ......In equation (3) and equation (4),
The first term is a function of the frequency 2fi-fk, and the second term is a function of the frequency f. Multiplier 10
The signal output from 6, that is, the signal expressed by equation (4), is input to bandpass filter 108. The bandpass filter 108 functions to extract only the signal component of the second term in equation (4). Therefore, the output signal of the bandpass filter 108 is the function cos(
2πfht).

Here, we will specifically explain using numerical values the case where the modulation frequency is f + "1650 Hz, f2 = 1850 Hz, and the A/D conversion rate is τ = 1/7200 seconds, which was impossible to demodulate in the conventional example. .

Suppose that the frequency of the clock 1070 for frequency shifting is f,
= 850Hz, the frequency of the input signal 100 is f I
” f + ORf 2, so f r = f +
Due to the relationship f k, when f,=f+, f,=80
0 Hz (fh+), and when f + = f 2, fk = 1000 Hz (f k,). As mentioned above, the output of the bandpass filter 108 is cos(2π
fkt), so the input signal 100 is f + = 1
At 650 Hz, cos (2fffv+t) (=
800Hz signal), and when f2=1850Hz, c
os(2yrfbzt)=1000Hz signal) is output. That is, as shown in FIG. 5, the output of the bandpass filter is a signal obtained by shifting the input signal 100 to the lower side by 850 Hz.

Therefore, since the processing of the block surrounded by the broken line after the bandpass filter output is the same delay detection method as in the conventional example, the two modulation frequencies after the frequency shift that are the bandpass filter output are changed to fl (=800Hz ), f t
' (= 1000Hz) and performs delayed detection, so
As in the case of the data shown in the conventional example, the center frequency fc
'=900Hz, the first term CO3((LIT
) is “0” (2πf.

T=yr/2+πm, m=0.1,2. -fc' Tf
,' *nr=1740m/2)
Set the delay and flT so that (T=2τ=2/72
00: n = 2.1 + 2m = 1), so the two frequencies to be determined are L' = 800Hz and f2' = 10.
The phase difference with respect to the center frequency fo' of 00 Hz is expressed by the sine sign of the output data of the low-pass filter 104. Therefore, the input signal 100 is “0” (f +=16
50Hz), the bandpass filter output is f+'
= 800Hz, the output of the low-pass filter 104 becomes positive, and the input signal 100 becomes "l" (f2 = 1850Hz
), then the bandpass filter output is fz'=1.00
0Hz,! : s'), low-pass filter 104
The output of is negative. Therefore, the determiner 105 can stably output 0'' as the output signal 11O (demodulation result) if the sine sign of the output data of the low-pass filter is positive, and ゛l'' if it is negative. .

As explained above, in the conventional example, the delay due to the A/D conversion rate does not adapt to the optimal delay amount of the modulation frequency to be delayed detected, and even at a modulation frequency where delay detection cannot be performed, according to this embodiment, By multiplying the input signal by the frequency shift clock and passing it through a bandpass filter, the modulation frequency is shifted by an appropriate amount, so it is possible to optimize the delay amount depending on the A/D conversion rate, and FSX modulation. It is possible to perform delayed detection and demodulation of the signal with an optimal amount of delay.

〔Effect of the invention〕

As explained above, when the timing clock given to the signal processing LSI is selected to correspond to a faster modulation/demodulation method and the timing clock is used for A/D conversion, conventional FSX demodulation equipment using delayed detection has been used. In this case, a delay that is an integral multiple of the A/D conversion rate cannot necessarily be adapted to the optimal delay amount of the modulation frequency to be subjected to differential detection, and optimal demodulation by differential detection may not be possible.

However, according to the present invention, the modulation frequency is shifted by an appropriate amount by multiplying the input signal by the frequency shift clock and passing it through a bandpass filter, so the delay due to the A/D conversion rate is optimized. It is possible, F S
It is possible to perform delay detection and demodulation of the K modulated signal with an optimal amount of delay.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention, FIG. 2 is a diagram showing the configuration of a conventional example, and FIGS. FIG. 5 is a graph of the output function of the low-pass filter with respect to the frequency of the input signal, and is a diagram showing the relationship between the input signal and the output of the band-pass filter in this embodiment. In the figure, 100.200 is an FSX modulated input signal, 101.
201);! A/D converter, 102, 202 are delay buffers, 103, 106, 203 are multipliers, 104, 20
4 is a low-pass filter, 105°205 is a judger, 10
7 is a frequency shift clock, 108 is a band pass filter, and 110 and 210 are output signals (demodulated signals). Agent Patent Attorney Shinminezu Uchihara

Claims (1)

[Claims] A demodulation device that demodulates and outputs an input signal modulated by a frequency shifting method (FSK) using digital signal processing includes an A/D converter that converts an input analog signal into digital data and outputs it, and an A/D converter that converts the input analog signal into digital data and outputs the digital data. a first multiplier that multiplies the frequency shifting clock of the digital data by a clock used for shifting the digital data to the frequency of the digital data; and a bandpass filter that extracts an arbitrary frequency component from the output of the first multiplier. and,
a delay buffer that delays and outputs the output of the band-pass filter; a second multiplier that multiplies the output data of the band-pass filter by the output data of the delay buffer; A demodulation device comprising: a low-pass filter that extracts a frequency component; and a determiner that determines a frequency based on output data of the low-pass filter and outputs a demodulated signal.