JPS62108633A - Clock recovery circuit - Google Patents

Abstract

PURPOSE:To avoid the effect of temperature change by inserting an amplifier, a filter and a waveform converter having nearly the same characteristic as that of an amplifier and a filter at the input side and an output side waveform converter between a voltage controlled oscillator and a phase comparator in series. CONSTITUTION:A base band signal is subject to full wave rectification 5, amplified (6) and detected (7) and the result is inputted to one input of a phase comparator 8. A low frequency component being an output of the comparator 8 is filtered (9) and subject to error amplification 10 to drive a voltage controlled oscillator 11. An amplifier 16, a filter 17 having nearly the same characteristic as that of the input side amplifier 6 and the filter 7 and a waveform converter 12' having nearly the same characteristic as that of the output side waveform converter 12 are connected in series between the oscillator 11 and the other input of the phase comparator 8. Let the phase change of the amplifier 6, the filter 7 and the waveform converter 12 due to temperature be phi1-phi3, the phase phi1+phi2 is canceled by the phase comparator 8 and -phi3 appearing at the voltage controlled oscillator 11 is canceled by the phase +phi3 of the waveform converter 12. Thus, the effect of the temperature change is hardly received.

Description

[Detailed Description of the Invention] [Summary] In a clock recovery circuit, an amplifier and a filter provided in the input stage and a waveform converter provided in the output stage are provided between the voltage controlled oscillator and the phase comparator in the phase locked circuit. Since the phase change of the output of the waveform converter due to temperature change is compensated for by inserting the converter, a clock regeneration circuit that is hardly affected by temperature change can be obtained.

[Industrial application field]

The present invention relates to improvements in clock recovery circuits.

In recent years, it has become common practice to transmit digital signals using wireless lines.

FIG. 2 shows a Zoronck diagram of a demodulator for digital radio, and FIG. 3 shows an operation explanatory diagram of the discriminator shown in FIG. Therefore, the operation shown in FIG. 2 will be explained with reference to FIG.

1. Ma! In FIG.
After frequency conversion and amplification, demodulator 1
The −ζ Haese hand signal (hereinafter abbreviated as No. 8818) is extracted and applied to the clock recovery circuit 4 and the discriminator 2.

In the former case, the clock is regenerated, but in the latter case, as shown in FIG. After the phase shift amount is adjusted 9 times (initial setting), B, Bj
The signal G'Bh is separated and converted into a digital signal and sent to terminal 0.
1jT exclusive output. .

However, even if the ambient temperature changes, the characteristics of the transmission line connecting the receiver and the discriminator are not affected, but the phase shifts in response to this change. Since the discriminator sends out the same clock, there is a possibility that the discriminator will make an erroneous identification.

Therefore, there is a need for a clock regeneration circuit that is not easily affected by changes in ambient temperature.

・・・　9. [Conventional technology] FIG. 4 shows the conventional example shown in FIG. 1.129.

In the figure, for example, 16 hanidomari amplitude changes,
aThl wave (hereinafter referred to as 160AM H1fG)
1°'-J) Color 4 Lareta II II (The signal g is input from the terminal 1N to the full-wave rectifier circuit 5. Here, after being doubled, it is amplified to an appropriate level by the amplifier 6, and then the signal is output by the filter 7. Only the r:I component is extracted 111° and added to the phase comparator 8.

゛ On the other hand, here is a voltage controlled oscillator (hereinafter referred to as VCO) that oscillates at a frequency close to the frequency of the above clock component.
The output from (abbreviated as ・ ) is also added, so
The two outputs are phase-compared, and the output corresponding to the phase error is passed through a low-pass filter 9 to extract only the low-frequency component, and then amplified by an error amplifier 10 and output to VCOI! added to. Therefore, the oscillation frequency of the VCO is controlled so that the above phase error is minimized, and a part of the output of the VCO is converted into a rectangular wave by the waveform converter 12.
Used as a clock.

[Problem that the invention seeks to solve]

However, the phase changes of the amplifier 6, filter 7, and waveform converter 12 when the ambient temperature changes by T are shown in Figs. 2, each φ1. φ2. If φ3, the phase change of the BB multiplied signal or r dock at the input of the phase comparator 8 is (φ1+φ2).

Therefore, in order to make the phase error 0 in the phase synchronization circuit 8, V
VC so that the phase change of the CO output becomes (φ1 + φ2)
Since the oscillation frequency loss is controlled, the phase change of the output of the waveform converter becomes (φ1+φ2+φ3), and each phase change directly becomes a clock phase change.

On the other hand, multi-leveling has progressed to 16QAM, 640AM, etc.
There is a problem in that the higher the transmission speed, the narrower the amount of allowable phase change, which requires a clock recovery circuit that is less susceptible to temperature changes.

Means for Solving Problem c] The above problem is caused by the fact that an amplifier 6. This problem is solved by the clock synchronization circuit of the present invention in which the filter 7 and the voltage comparator 12 are inserted.

[Effect]

The present invention utilizes the phase comparison characteristics of a phase synchronized circuit to compensate for changes in clock phase due to temperature. That is, an amplifier 6 provided at the input stage, a filter 7 and a waveform converter 12 provided at the output stage are inserted between the VC'0"l'l and the phase comparator 8 in the phase synchronized circuit, and temperature changes are detected. The phase change of the output of the waveform converter 12 caused by

[Embodiment] Fig. 1 shows a bookdog diagram of an embodiment of the present invention, and the same reference numerals indicate the same objects throughout the figures.

As shown in the figure, voltage controlled oscillator 11 and phase comparator 8
and the amplifier 6, which affects the temperature characteristics of this clock redistribution circuit. By inserting the filter 7 and the waveform converter 12, the output wave (i.e., clock) of the waveform converter
The phase change of can be compensated for as follows.

That is, when the ambient temperature change is T, amplifier 6. Filter 7
, the phase change of the waveform converter 12 is φ1, φ2 . φ
3, the number of RB parts added to the phase comparator 8 is
The γ phase change becomes (φ1→φ2).

On the other hand, since the phase synchronization circuit 14 operates so as to eliminate the phase error, the phase change (2) on the input side of the phase comparator 8 becomes 7 (φ1 φ2). However, this phase change is caused by the amplifier 6. The change after passing through the filter 7 and the waveform converter 12 results in -φ3 at the output side of the VCO 11. Therefore, on the output side of the waveform converter 12, -ψ3-tφ3-0 is obtained, and an output that is not affected by temperature changes is obtained.

That is, if the phase of the clock is initially set so that the BFI number is identified by the optimum value A as shown in Fig. 3, a clock regeneration circuit whose state hardly changes even if the ambient temperature changes can be obtained. However, this improves the deterioration of the error rate.

Note that the input stage amplifier 6. A filter 7, an output stage waveform converter 12, and a compensation amplifier 6. Filter 7° waveform converter 1
2 has the same circuit configuration and temperature characteristics.

(Effects of the invention) As explained above, even if the ambient temperature changes,
This has the effect of providing an I:I drive regeneration circuit that is not easily affected by this.

This improves the deterioration of the error rate.

[Brief explanation of drawings]

Figure 1 is a block diagram of the present invention, Figure 2 is a schematic diagram of a demodulator for digital radio, and Figure 3 is a block diagram of the present invention.
This figure is an explanatory diagram of the operation of the discriminator shown in FIG. 2, and FIG. 4 is a block diagram of a conventional example. In the figure, 5 is a full-wave rectifier circuit, 6 is an amplifier, 7 is a filter, 8 is a phase comparator, 941 is a low-pass filter, IO is an error amplifier, 11 is a voltage controlled oscillator, and 12 is a waveform converter. Nokokai ≦ Sun and Moon Funko is busy! , Sashi's figurine hat % j Figure 4th ward

Claims (1)

[Claims] After full-wave rectification of the baseband signal obtained by demodulation,
A clock component extraction circuit (13) amplifies the clock component with an amplifier (6) and extracts the clock component with a filter (7), and the phase is determined by comparing the phase of the output of the clock component extraction circuit and the output of the voltage controlled oscillator (11). a phase comparator (8) that obtains an output corresponding to the error; and a phase comparator (8) that filters and amplifies the output of the phase comparator and applies it to the voltage controlled oscillator to control the oscillation frequency so that the phase error is minimized. In a clock synchronization circuit composed of a synchronization circuit (14) and a voltage comparator that converts the output of the voltage control oscillator (11) into a rectangular wave, the voltage control oscillator (11) and the phase comparator (8) An amplifier (16), a filter (17) and a voltage comparator (12) having almost the same characteristics as the amplifier (6) and filter (7).
A clock regeneration circuit characterized by inserting the following in series.