JPH04268818A - Level shift circuit - Google Patents

Abstract

PURPOSE:To make a through current small, and to accelerate response speed by utilizing the channel resistance of the transistor(TR) of a level shift circuit. CONSTITUTION:Two pairs of inverters are constituted by connecting the drains and the gates of P type TRs Q4, Q5 and N type TRs Q3, Q6. Besides the P type TRs Q1, Q4 are connected to the power supply sides of the inverters, and the outputs of the inverters are connected to their gates, and cross constitution is formed. Namely, the through current is limited by the P type TRs Q2, Q5, and the stabilization of the potential of the output OUT is accelerated. The operation of the TRs Q2, Q5 becomes effective specially in the case that the difference of supply potentials VDD2 and VDD1 is small.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a level shift circuit, and more particularly to a level shift circuit composed of MOS transistors.

0002

2. Description of the Related Art A conventional level shift circuit, as shown in FIG.
conductivity type transistors Q1 and Q4, the drains of the transistors Q3 and Q1 and the transistors Q4 and Q6 are connected to each other, and each connection point is connected to the gate of the paired second conductivity type transistors Q1 and Q4, respectively. There is. An input IN is input to the gate of the transistor Q3, and a signal obtained by inverting the input IN by an inverter INV is input to the gate of the transistor Q6.

Next, the operation of the circuit shown in FIG. 3 will be explained.

When the signal IN is at the "level", the transistor Q3 is in the "off" state, and the potential at the point A becomes the "H" level, so that the potential at the point B becomes the "H" level.
The potential at the point becomes "L" level, and the gate of transistor Q1 becomes "L" level, thereby becoming "H" level. When the signal IN changes to the “H” level, first the transistor Q3 turns on, and then the transistor Q3 turns on.
6 is turned "off", the potential at point A becomes "L" level, and then the potential at point B becomes "H" level.

Therefore, the potentials at points A and B, that is, the gate potentials of transistors Q4 and Q1, are determined by the "on" state of opposing transistors Q3 and Q6.
6 are simultaneously "on" for a longer time, and the through current increases. Furthermore, this through current slows down the potential stabilization at points A and B, resulting in poor response speed as a level shift circuit.

[0006]

[Problem to be solved by the invention] As explained above,
In the conventional level shift circuit described above, a large through current flows when a signal changes, and this through current further deteriorates the level shift response.

The present invention has been made in view of the above-mentioned conventional circumstances, and therefore, an object of the present invention is to solve the above-mentioned problems inherent in the conventional technology and to provide a novel method that makes it possible to improve the response speed. An object of the present invention is to provide a level shift circuit.

[0008]

[Means for Solving the Problems] In order to achieve the above object, a level shift circuit according to the present invention has the drain and gate of a first conductivity type transistor and a second conductivity type first transistor connected to each other. the source of each transistor of the first conductivity type is connected to ground, and the gate of each first transistor of the second conductivity type is connected to the transistor of the pair; The drains of a second conductive type second transistor pair are connected to each drain connection point of the second conductive type transistor pair and each source is connected to the first power supply, and the first conductive type transistor and the second conductive type transistor pair are connected to each other. The device is characterized in that a second power level signal and an inverted signal of the second power level signal are respectively input to the gate pair of the first conductive type transistor.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, preferred embodiments of the present invention will be specifically explained with reference to the drawings.

FIG. 1 is a circuit diagram showing a first embodiment of the present invention.

Referring to FIG. 1, a P-type transistor Q2
, Q5 and the drains and gates of N-type transistors Q3 and Q6 are connected to form two pairs of inverters,
On the power supply side of each inverter, P-type transistors Q1 and Q
4 are connected, and the gates of the transistors Q1 and Q4 are connected to the output of the inverter in a cross-crossing configuration.

Next, the operation of the first embodiment of the present invention shown in FIG. 1 will be explained.

First, consider the situation when the signal IN is at the "L" level. When signal IN is “L”, point C is “H”
Therefore, the potential at point B becomes "L" because the transistor Q6 turns "on", and the transistor Q1 turns "on".
Since the transistor Q2 is also in the "on" state, the point A becomes "H" level. When the point A is "H", the transistor Q4 is in the "off" state, and is in a steady state.

Next, consider the case where the signal IN changes to "H". When the signal IN becomes "H", the transistor Q3 turns "on", so that the point A becomes "L". At this time, the gate voltage of transistor Q1 (point B) is still “L”
level, a through current flows through transistors Q1, Q2, and Q3, but the gate potential of transistor Q2 is
Since N is at “H” level, transistor Q
Since the resistor 2 has a high resistance, the through current is limited. Also, because the through current decreases, the potential at point A rapidly changes to “
It goes to "L" level and turns the transistor Q4 into the "off" state. Therefore, the potential of the output OUT is quickly stabilized.

When the signal IN changes to "L", the operation is reversed, and the through current flowing through the transistors Q4, Q5, and Q6 is limited by the transistor Q5.
The potential stabilization of the output OUT becomes faster.

The operation of transistors Q2 and Q5 is particularly effective when the difference between power supply potentials VDD2 and VDD1 is small, and when the threshold potential is about 1.0V, VDD1 = 3.0V and VDD2 = 5.0V. When operated, the through current can be reduced almost to the level of an inverter with a CMOS configuration.

FIG. 4 shows timing charts and current consumption of the conventional circuit and the present invention.

FIG. 2 is a circuit diagram showing a second embodiment of the present invention.

Referring to FIG. 2, in the circuit according to the second embodiment, all the polarities of the first embodiment are reversed, and the power supply voltage is set to a negative level.

The operation is similar to that of the first embodiment described above, but the level is shifted to a negative voltage. Generally, P-type transistors have a smaller driving capability than N-type transistors, so P-type transistors Q3 and Q6 must be made larger than N-type transistors, and the level shift circuit becomes larger in area. Further, while the current limiting transistors Q2 and Q5 of the first embodiment are P-type transistors, the circuit according to the second embodiment is an N-type transistor, so that the transistor size can be reduced. Become.

Therefore, the second embodiment can minimize the rate of increase in the area occupied by the circuit compared to the first embodiment.

[0022]

[Effects of the Invention] As explained above, according to the present invention,
By utilizing the channel resistance of a transistor in a conventional level shift circuit, it is possible to reduce the through current and increase the response speed, and the circuit can be used in battery-powered equipment and the like.

[Brief explanation of the drawing]

FIG. 1 is a circuit configuration diagram showing a first embodiment according to the present invention.

FIG. 2 is a circuit configuration diagram showing a second embodiment according to the present invention.

FIG. 3 is a conventional circuit diagram.

FIG. 4 is a diagram showing signal waveforms and through-current waveforms at various parts of the circuit of the present invention and the conventional circuit.

[Explanation of symbols]

Q1, Q2, Q3, Q4, Q5, Q6...MOS transistor IN...Input OUT...Output INV...Inverter VDD1, VDD2...Power supply voltage A, B, C, D, E...In-circuit contact

Claims (1)

[Claims] 1. The transistor has two pairs of transistors in which the drains and gates of a transistor of a first conductivity type and a first transistor of a second conductivity type are respectively connected, and the source of each transistor of the first conductivity type is connected to ground,
Each source of each of the first transistors of the second conductivity type includes a second transistor of the second conductivity type, each gate of which is connected to each drain connection point of the pair of transistors, and each source of which is connected to the first power supply. The drains of each pair of transistors are connected, and the transistor of the first conductivity type and the transistor of the second conductivity type are connected.
A level shift circuit characterized in that a second power level signal and an inverted signal of the second power level signal are respectively input to the gate pair of the first conductive type transistor.