JPH0691455B2 - Logic circuit - Google Patents

Description

The present invention relates to a logic circuit, and more particularly to a logic circuit adapted for high speed operation.

[Conventional technology]

As a conventional technique, there is a circuit shown in FIG. This has a voltage source composed of a P-channel MOSFET (hereinafter referred to as P-MOSFET) 13 and an N-channel MOSFET (hereinafter referred to as N-MOSFET) 14, to which the gate of the P-MOSFET 11 is connected to generate a current. It forms a mirror circuit. There is a driving transistor 12 with the P-MOSFET 11 as a load, and its gate serves as an input of the logic circuit and its drain serves as an output.

Generally, this kind of circuit is composed of a driving transistor and a load element, but in the case of CMOS, the load side is defined as a current mirror circuit composed of a transistor of opposite conductivity type to the driving side to determine the circuit current. By using the transistor of the same conductivity type as the driving transistor, that is, like the N-MOSFET 14 of FIG. 4, even if the characteristics such as the threshold value of the transistor forming the current mirror are changed at the time of manufacture, Size of N-MOSFET 14 (channel width; W
The ratio of / channel length; L) can be used to determine the output "0" level.

In addition, this type of circuit charges the load capacitance at a switching speed when the output level changes from “0” to “1” at a speed determined by the current characteristics of the load circuit, with the driving transistor turned off. It is slower than the switching speed when changing from "1" to "0". This is because when changing from "1" to "0", the driving transistor, which has several times the current capacity on the load side, is turned on, so the switching speed becomes sufficiently high.

[Problems to be solved by the invention]

In the conventional circuit described above, the output level is output stably, but if the load side is increased to switch at high speed, V _OL shown in Fig. 5 shifts to the V _D side, that is, the "0" level deteriorates. However, there is a drawback that the next stage cannot be driven.

[Means for solving problems]

In the logic circuit of the present invention, each gate electrode of the first and second pairs of first conductivity type transistors whose source electrodes are connected to the power supply potential is commonly connected to the drain electrode of the second first conductivity type transistor. A current mirror circuit is used as an active load, and a predetermined number of first second conductivity type transistors are inserted in parallel between the drain electrode of the first first conductivity type transistor and the ground potential, and their respective gates are connected. A predetermined number of input signals are supplied to the electrodes and an output signal is taken out from the drain electrodes connected in parallel, and a second signal is provided between the drain electrode of the second first conductivity type transistor and the ground potential. A gate of the first first-conductivity-type transistor in a logic circuit configured by connecting two-conductivity-type transistors and connecting their gate electrodes to the power supply potential. A third second conductivity type transistor having the output signal connected to the gate electrode is inserted between the pole and the ground potential, and a first (or a second) transistor is provided between the gate electrodes of the first and second first conductivity type transistor pairs. 2) A conductive type control transistor is inserted, the output signal (or input signal) is supplied to the gate electrode of the control transistor, and the control transistor and the control transistor are supplied in accordance with the operation level of the output signal (or input signal). The third second conductivity type transistor is complementarily turned on / off.

〔Example〕

 Next, the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram of the first embodiment of the present invention. P-MOSFET1 for load and N-MOSFET2 for drive are power supply and GND
It is connected in series between and the gate of N-MOSFET2 is input, N
The connection point between the drain of the MOSFET 2 and the drain of the P-MOSFET 1 is the output of this logic circuit.

The gate of P-MOSFET 1 has P-MOSFET 5 and N-MOSFET 6
Is connected to the output of this logic circuit, the source of N-MOSFET 6 is connected to GND, and the source of P-MOSFET 5 is the gate of P-MOSFET 3 that forms a current mirror circuit with P-MOSFET 1. And connected to the drain.

The N-MOSFET 4 determines the current value of this current mirror circuit, and is connected between the drain of P-MOSFET 3 and GND.
A voltage source is connected to the gate. In this embodiment, P
-Supplying the source voltage of MOSFET3.

Next, the operation of this embodiment will be described with reference to FIG.

First, when the input becomes "1" and the driving transistor 2 is turned on, the output switches to "0". At this time, the output of the gate of the load transistor 1 is P-MO.
It goes to GND level until SFET5 is turned on and N-MOSFET6 is turned off. Therefore, the swinging progresses along the current characteristic toward I _OH1 .

Next, when the P-MOSFET 5 is turned on and the N-MOSFET 6 is turned off, the voltage generated in the P-MOSFET 3 and the N-MOSFET 4 is supplied to the gate of the load transistor 1, so that the current characteristic toward I _OH1 is _increased. Switch to the middle.

If I _OH2 remains, the “0” level becomes V _OL2 and GN
If the circuit floats from D and exceeds the threshold of the N-MOSFET, and if the next stage is a dynamic circuit, N
-Since the MOSFET cannot be turned off, it will malfunction. However, in the case of this embodiment, I
This will not happen because the output level becomes V _OL1 by switching to the _OH1 side.

Next, when the input becomes "0", the opposite will occur, but here the switching speed will be explained. When the input is "0" → "1", the output will switch according to the characteristics of the driving transistor (broken line), but this ability can flow several times the current of the load transistor. , Switching speed is slower when the input changes from "1" to "0".

First, the process proceeds from V _OL1 to the I _OH1 side, but the gate of the load transistor switches to GND, increasing the current supply capacity and increasing the switching speed.

Although the substrate of the P-MOSFET 5 is connected to the power supply in FIG. 1, it may be connected to the P-MOSFET 3 side. Also, P
-In parallel with MOSFET5 or instead of P-MOSFET5, N-
It is also possible to connect a MOSFET and add an inverted signal of the output to this gate.

FIG. 3 is a circuit diagram of the second embodiment of the present invention.

This is an N-MOSFET 25 instead of the P-MOSFET 5 in FIG.
And 35 are connected in parallel. At this time, the driving transistor is also connected in parallel to the output, and both are connected in the same number. The same signal is input to the gate signal, and when one of the driving transistors is in the ON state, that is, when the output is "0", the voltage generated in P-MOSFET 23 and N-MOSFET 24 is applied to the gate of the load transistor. Join.

When all inputs are "0" and the driving transistors are off, all the transistors connected in parallel with these N-MOSFETs 35 and 25 are off.
When the output exceeds the threshold value of the N-MOSFET 26, the gate of the load transistor 21 immediately becomes the GND level, and a large current can be passed, so that the switching speed is significantly increased.

〔The invention's effect〕

As described above, the present invention can increase the capacity of the load element and enable high-speed operation by loading the active element, and in particular, in the NOR circuit in which the driving transistors are connected in parallel, the output is Since the drain capacitance of each driving transistor is added to, the load characteristics are greatly improved.

[Brief description of drawings]

FIG. 1 is a circuit diagram of the first embodiment of the present invention, and FIG.
FIG. 3 is a current characteristic diagram of each transistor, FIG. 3 is a circuit diagram of a second embodiment of the present invention, FIG. 4 is a circuit diagram of a conventional example, and FIG. 5 is a current characteristic diagram of each transistor of FIG. is there. 1,3,5,11,13,21,23 …… P-MOSFET, 2,4,6,12,14,22,2
4,25,26,32,35 …… N-MOSFET.

Claims (1)

[Claims] 1. A current mirror in which each gate electrode of a pair of first and second conductivity type transistors having a source electrode connected to a power supply potential is commonly connected to a drain electrode of the second conductivity type transistor. Using a circuit as an active load, a predetermined number of first second-conductivity type transistors are inserted in parallel between the drain electrode of the first first-conductivity type transistor and the ground potential, and are connected to the respective gate electrodes. A predetermined number of input signals are supplied and an output signal is taken out from the drain electrodes connected in parallel, and a second second conductivity is provided between the drain electrode of the second first conductivity type transistor and the ground potential. Type transistor is connected and the gate electrode thereof is connected to the power supply potential, the gate electrode and the gate electrode of the first conductivity type transistor are provided. A third second conductivity type transistor having the output signal connected to the gate electrode is inserted between ground potentials, and a first (or second) transistor is provided between the gate electrodes of the first and second first conductivity type transistor pairs. ) A conductivity type control transistor is inserted, the output signal (or input signal) is supplied to the gate electrode of the control transistor, and the control transistor and the first signal are supplied in accordance with the operation level of the output signal (or input signal). 3. A logic circuit in which the third conductivity type transistor of No. 3 is complementarily turned on / off.