JP2001016050A - Operational amplifier - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain an operational amplifier having good response. SOLUTION: When a ground voltage is inputted to the gate of a 2nd MOS transistor(TR) Q2, the drain of a 5th MOS TR Q5 is not held completely at the ground voltage, and the gate voltage of a 1st MOS TR Q1 is different from the ground voltage, so that the gate potentials of the 1st and 2nd MOS TRs forming an operation couple become unbalanced. Since the 1st MOS TR Q1, however, is larger than the 2nd MOS TR Q2, the 1st MOS TR Q1 can outputs the same current wit the 2nd MOS TR Q2. Consequently, 1st and 2nd MOS TR output currents I1 and I2 become equal at the drain side of the 4th MOS TR Q4, and the gate voltage of a 5th MOS TR Q5 will not rise unwillingly. Then when a plus voltage is inputted to the gate of the 2nd MOS TR Q2, the gate voltage of the 5th MOS TR Q5 need not be lowered, and response characteristics are improved.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an operational amplifier composed of MOS transistors.

[0002]

2. Description of the Related Art An active load of a P-channel MOS type first and second transistor forming a differential pair as such an operational amplifier is constituted by a current mirror circuit, and is connected to a drain of a second transistor on a non-inverting input terminal side. A connection point between the drain of the output transistor of the current mirror circuit and the gate of the output transistor, an output is taken out from the drain of the output transistor via the output terminal, and the gate of the first transistor on the inversion terminal side Is connected to an output terminal.

[0003]

In this case, when a ground level is input to the gate of the second transistor, the output transistor whose source is grounded is turned on, but its drain voltage cannot be at the ground level, and the drain voltage cannot be changed to the ground level. It becomes a near positive voltage. For this reason, the gate voltage of the first transistor to which the positive voltage is fed back becomes higher than the gate voltage of the second transistor, and the voltage of the node (therefore, the gate voltage of the output transistor) increases.

After such a state, when an input voltage higher than the ground level is next applied to the gate of the second transistor, the time required for lowering the gate voltage of the output transistor causes a delay in response speed, The operational amplifier had poor response.

The present invention has been made in view of the above points, and has as its object to provide an operational amplifier having good responsiveness.

[0006]

In order to achieve the above object, an operational amplifier according to the present invention comprises: first and second MOS transistors of a first conductivity type forming a differential pair; And a third MOS transistor of the second conductivity type having a source connected to the first voltage; a drain connected to the drain of the second MOS transistor, a gate connected to the gate of the third MOS transistor, and a source connected to the first voltage. The fourth of the second conductivity type
A MOS transistor; a first constant current source connected to the sources of the first and second MOS transistors; a second and a fourth M
A fifth MOS transistor of a second conductivity type having a gate connected to a connection node of the OS transistor and a source connected to the first voltage; a second constant current source connected to a drain of the fifth MOS transistor; A capacitor connected between the gate and the drain;
An output terminal connected to the drain of the S transistor and the gate of the first MOS transistor; and a means for applying an input voltage including the first voltage to the gate of the second MOS transistor, wherein the first MOS transistor is formed larger than the second MOS transistor. ing.

According to such a configuration, when the fixed first voltage is input to the gate of the second MOS transistor, the drain of the fifth MOS transistor does not completely reach the first voltage, so that the gate voltage of the first MOS transistor is also equal to the first voltage.
The gate voltage of the first and second MOS transistors becomes unbalanced due to a value different from the voltage. However, the first M
Since the OS transistor is formed larger than the second MOS transistor, the first MOS transistor
A current approximately equal to (same as) the OS transistor can be output.

Therefore, the two currents output from the first and second MOS transistors are offset on the drain side of the fourth MOS transistor, and the gate voltage of the fifth MOS transistor does not increase (or decrease) unintentionally. That is, it does not undesirably shift. Therefore, when a voltage different from the first voltage is input to the gate of the second MOS transistor next time, it is not necessary to correct an undesired shift of the gate voltage of the fifth MOS transistor, which is equivalent to the conventional example. Response characteristics are improved.

[0009]

Embodiments of the present invention will be described below with reference to the drawings. In FIG. 1, Q1 and Q2 are P-channel first and second MOS transistors forming a differential pair, and their sources are connected to the first constant current source 1.
The drain of the first MOS transistor Q1 is connected to the drain and gate of an N-channel third MOS transistor Q3, and the drain of the second MOS transistor Q2 is N
It is connected to the drain of a channel type fourth MOS transistor Q4.

The gate of the fourth MOS transistor Q4 is connected to the gate of the third MOS transistor Q3.
The third and fourth transistors Q3 and Q4 form a current mirror circuit 3, and their sources are all connected to ground (fixed voltage point). The gate of the second MOS transistor Q2 is connected to the non-inverting input terminal 2.

A connection node a between the drain of the second MOS transistor Q2 and the drain of the fourth MOS transistor Q4 is connected to the gate of an N-channel type fifth MOS transistor Q5. The fifth MOS transistor Q5 forms an output transistor, and its source is connected to the ground and its drain is connected to the second constant current source 4. The connection point between the drain of the fifth MOS transistor Q5 and the constant current source 4 is connected to the output terminal 5. The output terminal 5 is connected to the gate of the first MOS transistor Q1 in a feedback manner. C1 is an oscillation blocking capacitor connected between the gate and drain of the fifth MOS transistor Q5. VDD is a power supply voltage.

FIG. 2 equivalently shows the circuit of FIG.
Here, (+) is a non-inverting input terminal, which corresponds to the gate side of the second MOS transistor Q2, and (-) is an inverting input terminal, which corresponds to the gate side of the first MOS transistor Q1.

The first MOS transistor Q1 is connected to the second MOS transistor Q1.
It is formed larger than the transistor Q2. Specifically, as shown in FIG. 3, the channel width W1 of the first MOS transistor Q1 is formed larger than the channel width W2 of the second MOS transistor Q2. In FIG.
(A) is a schematic plan view of the first MOS transistor Q1, and (B) is a schematic plan view of the second MOS transistor Q2. G represents a gate, S represents a source, and D represents a drain region. L1 and L2 are channel lengths and have the same dimensions.

Next, the operation of this embodiment will be described. still,
To make the operation easy to understand, the operation in the case where the first and second MOS transistors Q1 and Q2 have the same size (conventional operation) will be described first. When the input voltage as shown in FIG. 4 is input to the non-inverting input terminal, the ground level is applied to the gate of the transistor Q2 at the start of the period T1, so that the transistor Q2 is turned on and the current I ₂
Flows, and the transistor Q5 is turned on.

[0015] However, since the transistor Q5 has a conduction time of resistance, which to the drain of the transistor Q5 by current I ₄ flows from the constant current source 4 is not obtained become the ground voltage, slightly exhibits a positive voltage V1 .
This positive voltage V1 is fed back to the gate of the first MOS transistor Q1. Since the gate of one (Q2) of the differential pair transistor is at the ground level and the gate of the other (Q1) is at the positive voltage V1, the currents I ₁ and I ₂ are I ₂ > I ₁ ,
I ₂ -I ₁ of the current and the capacitor C1 as indicated by the arrow flows through the first 5MOS transistor Q5. for that reason,
The capacitor C1 is charged with the polarity shown, and the gate voltage of the fifth transistor Q5 is high.

In this state, when the period of the input voltage T2 starts, the second MOS transistor Q2 is turned off and the first MOS transistor Q2 is turned off.
Transistor Q1 is turned state ON, the first in other words to discharge the capacitor C1 (the I ₁ 5MO
(Lowering the gate voltage of S transistor Q5). This time clearly results in a delay in response speed.

However, in this embodiment, since the transistor Q1 is formed larger than the transistor Q2, the above-described ground voltage is input to the input terminal 2 and the drain voltage of the transistor Q5 becomes V1, and this voltage V1 is The gate voltage of the first and second MOS transistors Q1 and Q2 becomes unbalanced (the gate voltage of Q1 is V1 and the gate voltage of Q2 is ground level). I ₁ and I ₂ are equal. In other words, in the present embodiment, the size of the transistor Q1 is determined so that I ₁ = I _{2 at} the time of this imbalance.

For this reason, even if the gate voltages of the first and second MOS transistors Q1 and Q2 are unbalanced, I
₁ = because it is I _2, I ₂ -I ₁ becomes current capacitor C1
Does not flow to For this reason, when the period of T2 starts, it is not necessary to discharge the electric charge of the capacitor C1, and the response speed is correspondingly increased.

FIG. 1 shows only the case where the first and second MOS transistors Q1 and Q2 are of P-channel type and the third to fifth MOS transistors Q3 to Q5 are of N-channel type. The 2 MOS transistors are N-channel type, and the third to fifth MOS transistors Q3 to Q3
Q5 may be a P-channel type. In this case, the sources of the third to fifth MOS transistors Q3 to Q5 are connected to the power supply voltage VDD, and the first and second constant current sources 1, 4 are connected to the ground. Also, the directions of the output currents of the first and second constant current sources 1 and 4 are reversed from those in the figure. And
The effect of the present invention can be obtained when the input voltage rapidly changes from a high level to a low level.

Further, in the present embodiment, the difference between the sizes of the transistors Q1 and Q2 is provided by changing the channel width, but the channel length of the transistor Q1 is made shorter than the channel length of the transistor Q2. Accordingly, the size of the transistor Q1 can be increased.

[0021]

As described above, according to the present invention, an operational amplifier having good responsiveness can be realized.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of an operational amplifier according to an embodiment of the present invention.

FIG. 2 is an equivalent circuit diagram thereof.

FIG. 3 is a schematic diagram showing a structure of a part of a MOS transistor constituting the operational amplifier of FIG. 1;

FIG. 4 is a diagram showing an input voltage input to the operational amplifier of FIG. 1;

[Explanation of symbols]

2 input terminal 3 current mirror circuit Q1 first MOS transistor Q2 second MOS transistor Q3 third MOS transistor Q4 forming a current mirror circuit fourth MOS transistor Q5 forming a current mirror circuit Q5 fifth MOS transistor C1 capacitor

Claims (1)

[Claims] 1. First and second MOs of a first conductivity type forming a differential pair
An S transistor; a third MOS transistor of a second conductivity type having a drain and a gate connected to the drain of the first MOS transistor and a source connected to the first voltage; a third MOS transistor having a drain connected to the drain of the second MOS transistor and a gate connected to the third MOS transistor Of the second conductivity type connected to the gate of the second MOS transistor and having the source connected to the first voltage
A transistor; a first constant current source connected to the sources of the first and second MOS transistors; and a second conductivity type having a gate connected to a connection node of the second and fourth MOS transistors and a source connected to the first voltage. A fifth MOS transistor, a second constant current source connected to the drain of the fifth MOS transistor, a capacitor connected between the gate and the drain of the fifth MOS transistor, and a drain connected to the drain of the fifth MOS transistor and the gate of the first MOS transistor. An operational amplifier comprising: a connected output terminal; and means for applying an input voltage including the first voltage to the gate of the second MOS transistor, wherein the first MOS transistor is formed larger than the second MOS transistor.