JPH07154218A - Signal waveform shaping circuit - Google Patents

Abstract

PURPOSE:To attain waveform shaping and propagation of even an analog signal whose amplitude is set to a high potential and whose amplitude is small by providing each circuit decreasing or increasing a potential set to the signal amplitude and 1st and 2nd CMOS inverter circuits in this circuit. CONSTITUTION:An analog signal wave whose amplitude is small and whose potential is set to a high potential in which a lower limit of the signal waveform is set higher than a center potential Vm of a power supply is given to a circuit comprising an N-channel transistor (TR) 11 and a 1st resistor 12, the potential set to the signal amplitude is decreased by a threshold voltage of the N-channel TR and the resulting signal is inversely amplified by a 1st CMOS inverter circuit 13. Its output signal is given to a circuit comprising a P-channel TR 14 and a 2nd resistor 15, the potential set to the signal amplitude is increased by a threshold of the P-channel TR. The resulting signal is given to a 2nd CMOS inverter circuit 16, the signal is again inversely amplified and its output signal becomes a signal having a completely full swing.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal waveform shaping circuit used in a semiconductor integrated circuit.

[0002]

2. Description of the Related Art A conventional signal waveform shaping circuit will be described below.

FIG. 3 shows a signal waveform shaping circuit in which two conventional CMOS type inverter circuits are connected in series. Reference numerals 1 and 2 denote CMOS type inverter circuits.

In this signal waveform shaping circuit, first, an analog signal generated by a signal generation circuit (not shown) is input to the CMOS type inverter circuit 1 and further CMO.
The output signal of the S-type inverter circuit 1 is input to the CMOS-type inverter circuit 2, and as a result, the output signal of the CMOS-type inverter circuit 2 is shaped into a pulse signal.

[0005]

However, in the above-mentioned conventional configuration, the signal waveform shaping may not be possible due to the variation of the characteristics of the signal generating circuit. That is, when the amplitude of the analog signal generated by the signal generation circuit is small and the signal waveform is located at a high potential as a whole, and the lower limit of the analog signal waveform is located above the central potential of the power supply voltage, the CMOS Even if the waveform is amplified by the type inverter, only the upper half of the waveform is amplified, and there is a problem that it is meaningless to operate the CMOS type inverter circuit of the next stage.

Further, when the amplitude of the analog signal waveform generated by the signal generating circuit is small, the signal waveform is located at a low potential as a whole, and the upper limit of the analog signal waveform is located below the center potential of the power supply voltage. Also has a similar problem.

The present invention solves the above-mentioned problems of the prior art, and is a signal capable of shaping an analog signal into a pulse wave even when the amplitude is small and the amplitude is high or low. It is an object to provide a waveform shaping circuit.

[0008]

In order to achieve this object, a signal waveform shaping circuit of the present invention is a circuit composed of an N-type transistor and a first resistor having an effect of lowering the potential at which the amplitude of an input signal is located. A first CMOS-type inverter circuit, a circuit including a P-type transistor having the effect of increasing the potential at which the amplitude of the input signal is located, and a second resistor, and a second CMOS-type inverter circuit.

Further, a circuit composed of a P-type transistor and a first resistor having an effect of increasing the potential at which the amplitude of the input signal is located, a first CMOS inverter circuit, and the potential at which the amplitude of the input signal is located are lowered. It is composed of a circuit composed of an N-type transistor having an effect and a second resistor, and a second CMOS type inverter circuit.

[0010]

With this configuration, a signal in which the potential at which the amplitude of the input signal is located is lowered (or raised) is applied to the first CMO.
Input to the S-type inverter circuit, and further, the first CMO
By raising (or lowering) the potential at which the amplitude of the output signal of the S-type inverter circuit is located, the second CMOS
The output of the inverter circuit becomes a signal with full swing.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a diagram showing the configuration of this embodiment. In FIG. 1, 11 is an N-type transistor, 12 is a first resistor connected to the drain of the N-type transistor 11, 13
Is a first CMOS type inverter circuit having an input terminal connected to the drain of the N type transistor 11, 14 is a P type transistor having a gate connected to the output terminal of the CMOS type inverter circuit 13, and 15 is connected to the drain of the P type transistor 14. The second resistor 16 is a P-type transistor 14
Is a second CMOS type inverter circuit connected to the drain of the.

The operation of this embodiment will be described with reference to the time chart of FIG. An analog signal whose amplitude is small and whose signal waveform is high and whose lower limit is higher than the center potential Vm of the power supply voltage (see FIG. 2).
When (a)) is input to the gate of the N-type transistor 11, a signal output to the drain of the N-type transistor 11 by the circuit composed of the N-type transistor 11 and the first resistor 12 (FIG. 2B). Is a signal in which the potential where the amplitude is located is lowered by the threshold voltage of the N-type transistor. When the signal is input to the first CMOS type inverter circuit 13, the output signal (FIG. 2 (c)) is inverted and amplified, but the high level side is not yet completely output. Further, when the output signal of the CMOS type inverter circuit 13 is input to the gate of the P-type transistor 14, the circuit including the P-type transistor 14 and the second resistor 15 outputs the signal to the drain of the P-type transistor 14 (see FIG. 2).
(D) is a signal in which the potential at which the amplitude is located is increased by the threshold voltage of the P-type transistor. When the signal is input to the second CMOS inverter circuit 16, it is inverted and amplified again and the output signal (FIG. 2 (e) becomes a signal having a perfect full swing).

As described above, according to this embodiment, the circuit for lowering the potential at which the signal amplitude is located, the first CMOS type inverter circuit, the circuit for raising the potential at which the signal amplitude is located, and the second circuit. By connecting the CMOS inverter circuits in series, it is possible to shape and propagate the waveform of an analog signal having a small amplitude and a high amplitude.

In the present embodiment, only the case where the analog signal waveform is located on the high potential side is shown, but even when the analog signal waveform is located on the low potential side, the circuit configuration of the present embodiment is The circuit including the N-type transistor and the first resistor may be replaced with the circuit including the P-type transistor and the second resistor.

Further, in this embodiment, in order to sufficiently enhance the capability of the signal waveform shaping circuit, one N-type transistor and one P-type transistor are used to restore the shift in two steps. When the degree of deviation of the signal waveform is small, for example, only one of N-type or P-type transistors may be used. That is, when the signal waveform is shifted to the high potential side, an N-type transistor is used, and when the signal waveform is shifted to the low potential side, a P-type transistor is used, and only one of these transistors is first Even if the configuration is such that it is connected to the input of the CMOS type inverter circuit and the second CMOS type inverter circuit is directly connected to the first CMOS type inverter circuit, it can function as the signal waveform shaping circuit of the present invention.

[0017]

According to the present invention, a circuit for lowering (or raising) the potential at which the signal amplitude is located, a first CMOS inverter circuit, and a circuit for raising (or lowering) the potential at which the signal amplitude is located, By providing a configuration in which the second CMOS inverter circuit is connected in series, it is possible to shape and propagate the waveform of an analog signal having a small amplitude and a high (or low) amplitude potential. It realizes a waveform shaping circuit.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a signal waveform shaping circuit according to an embodiment of the present invention.

FIG. 2 is a time chart of a signal waveform shaping circuit according to an embodiment of the present invention.

FIG. 3 is a block diagram of a conventional signal waveform shaping circuit.

[Explanation of symbols]

 11 N-type transistor 12 1st resistance 13 1st CMOS type inverter circuit 14 P-type transistor 15 2nd resistance 16 2nd CMOS type inverter circuit

Claims (3)

[Claims] 1. An N-type transistor, a first resistor connected to the drain of the N-type transistor, and a first CMO having an input terminal connected to the drain of the N-type transistor.
An S-type inverter, a P-type transistor whose gate is connected to the output terminal of the first CMOS-type inverter, and a second resistor connected to the drain of the P-type transistor,
A second CM connected to the drain of the P-type transistor
A signal waveform shaping circuit composed of an OS type inverter circuit. 2. A P-type transistor, a first resistor connected to the drain of the P-type transistor, and a first CMO having an input terminal connected to the drain of the P-type transistor.
An S-type inverter, an N-type transistor whose gate is connected to the output terminal of the first CMOS-type inverter, and a second resistor connected to the drain of the N-type transistor,
A second CM connected to the drain of the N-type transistor
A signal waveform shaping circuit composed of an OS type inverter circuit. 3. An N-type or P-type transistor and the N-type transistor
Resistor connected to the drain of the N-type or P-type transistor, a first CMOS type inverter having an input terminal connected to the drain of the N-type or P-type transistor, and a first CMOS type inverter connected to the output terminal of the first CMOS type inverter. A signal waveform shaping circuit composed of two CMOS inverter circuits.