JPH04255263A - Semiconductor package - Google Patents

Semiconductor package

Info

Publication number
JPH04255263A
JPH04255263A JP3816591A JP3816591A JPH04255263A JP H04255263 A JPH04255263 A JP H04255263A JP 3816591 A JP3816591 A JP 3816591A JP 3816591 A JP3816591 A JP 3816591A JP H04255263 A JPH04255263 A JP H04255263A
Authority
JP
Japan
Prior art keywords
semiconductor package
lead terminal
lead
resin
semiconductor chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3816591A
Other languages
Japanese (ja)
Inventor
Hiroki Ochi
越智　博樹
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP3816591A priority Critical patent/JPH04255263A/en
Publication of JPH04255263A publication Critical patent/JPH04255263A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item

Landscapes

  • Lead Frames For Integrated Circuits (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

PURPOSE:To prevent a lead terminal from being deformed and unfixed by a method wherein the lead terminal excluding its mounting contact area is all molded with resin. CONSTITUTION:A semiconductor chip 1 and lead terminals 4 are molded with resin 5 including a bonding wire 3 which electrically connects the semiconductor chip 1 with the lead terminals 4. Especially, the semiconductor chip 1, the lead terminals 4, and the bonding wires 3 are formed into one piece with resin including the upside 6 of the lead terminal 4 except the mounting contact area of the lead terminal 4. By this setup, the lead terminal 4 is prevented from being deformed and lifted, so that a semiconductor package of this design can be surely mounted on a printed board.

Description

【発明の詳細な説明】[Detailed description of the invention]

【０００１】0001

【技術分野】本発明は半導体パッケージに関し、特に表
面実装用の四方向フラット型パッケージに関する。TECHNICAL FIELD The present invention relates to semiconductor packages, and more particularly to four-way flat packages for surface mounting.

【０００２】0002

【従来技術】従来、この種の半導体パッケージでは、多
ピン化にともない、リード端子が曲がりやすい構造とな
っていた。その従来の半導体パッケージの断面図を図２
に示す。2. Description of the Related Art Conventionally, this type of semiconductor package has a structure in which lead terminals tend to bend as the number of pins increases. Figure 2 shows a cross-sectional view of the conventional semiconductor package.
Shown below.

【０００３】図２における半導体パッケージは、図示せ
ぬプリント基板への表面実装用のリード端子４の一端と
、アイランド２上の半導体チップ１とが樹脂５０によっ
てモールドされた構造となっている。なお、半導体チッ
プ１とリード端子４とはボンディングワイヤ３で接続さ
れている。また、リード端子４は多数本設けられている
。The semiconductor package shown in FIG. 2 has a structure in which one end of a lead terminal 4 for surface mounting on a printed circuit board (not shown) and the semiconductor chip 1 on the island 2 are molded with resin 50. Note that the semiconductor chip 1 and lead terminals 4 are connected by bonding wires 3. Further, a large number of lead terminals 4 are provided.

【０００４】しかし、上述した従来の半導体パッケージ
では、多ピン化に伴い、リード端子が細い場合には、半
導体パッケージの取扱い時にリード端子の曲がり及び浮
きが生じやすく、実装不良が発生しやすいという欠点が
あった。However, in the conventional semiconductor package described above, due to the increase in the number of pins, if the lead terminal is thin, the lead terminal tends to bend or come loose when the semiconductor package is handled, resulting in a disadvantage that mounting defects are likely to occur. was there.

【０００５】[0005]

【発明の目的】本発明は上述した従来の欠点を解決する
ためになされたものであり、その目的はリード端子の曲
がりや浮きが生じることのない半導体パッケージを提供
することである。OBJECTS OF THE INVENTION The present invention has been made to solve the above-mentioned conventional drawbacks, and its object is to provide a semiconductor package in which lead terminals do not bend or float.

【０００６】[0006]

【発明の構成】本発明による半導体パッケージは、表面
実装用のリード端子を有する半導体パッケージであって
、前記リード端子の実装接触面以外の部分すべてがモー
ルドされてなることを特徴とする。SUMMARY OF THE INVENTION A semiconductor package according to the present invention is a semiconductor package having lead terminals for surface mounting, and is characterized in that all portions other than the mounting contact surface of the lead terminals are molded.

【０００７】[0007]

【実施例】次に、本発明について図面を参照して説明す
る。DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be explained with reference to the drawings.

【０００８】図１は本発明による半導体パッケージの一
実施例の構造を示す断面図であり、図２と同等部分は同
一符号により示されている。FIG. 1 is a sectional view showing the structure of an embodiment of a semiconductor package according to the present invention, and parts equivalent to those in FIG. 2 are designated by the same reference numerals.

【０００９】図において、本実施例の半導体パッケージ
は、半導体チップ１を搭載するリードフレームのアイラ
ンド２と、半導体チップ１とリード端子４との間を電気
的に接続するボンディングワイヤ３とを含めて樹脂５に
より一体モールド化した構造となっている。このモール
ド構造において、特にリード端子４の実装接触面以外の
上面６側を全て含めて樹脂５により一体化させたことを
特徴としている。In the figure, the semiconductor package of this embodiment includes an island 2 of a lead frame on which a semiconductor chip 1 is mounted, and bonding wires 3 that electrically connect between the semiconductor chip 1 and lead terminals 4. It has a structure that is integrally molded with resin 5. This mold structure is particularly characterized in that the entire upper surface 6 of the lead terminal 4 other than the mounting contact surface is integrated with the resin 5.

【００１０】かかる構成によれば、リード端子４の曲が
りや浮きが生じなくなり、図示せぬプリント基板表面へ
の実装不良がなくなるのである。なお、四方向フラット
型パッケージに限らず、各種の表面実装部品について本
発明が適用できることは明白である。[0010] According to such a configuration, the lead terminals 4 do not bend or float, thereby eliminating mounting defects on the surface of a printed circuit board (not shown). It is clear that the present invention is applicable not only to four-way flat packages but also to various surface mount components.

【００１１】[0011]

【発明の効果】以上説明したように本発明は、表面実装
用のリード端子の実装接触面以外の上面部分を、樹脂等
により一体モールド化することにより、半導体パッケー
ジの取扱い時におけるリード端子の曲り等をなくし、実
装不良を防止できるという効果がある。As explained above, the present invention prevents the lead terminal from bending when handling the semiconductor package by integrally molding the upper surface portion of the lead terminal for surface mounting other than the mounting contact surface with resin or the like. This has the effect of eliminating problems such as problems and preventing mounting defects.

【図面の簡単な説明】[Brief explanation of the drawing]

【図１】本発明の実施例による半導体パッケージの内部
構造を示す断面図である。FIG. 1 is a cross-sectional view showing the internal structure of a semiconductor package according to an embodiment of the present invention.

【図２】従来の半導体パッケージの内部構造を示す断面
図である。FIG. 2 is a cross-sectional view showing the internal structure of a conventional semiconductor package.

【符号の説明】[Explanation of symbols]

１　　半導体チップ ２　　アイランド ３　　ボンディングワイヤ ４　　リード端子 ５　　樹脂 1 Semiconductor chip 2 Island 3 Bonding wire 4 Lead terminal 5 Resin

Claims (1)

【特許請求の範囲】[Claims] 【請求項１】　　表面実装用のリード端子を有する半導
体パッケージであって、前記リード端子の実装接触面以
外の部分すべてがモールドされてなることを特徴とする
半導体パッケージ。1. A semiconductor package having lead terminals for surface mounting, characterized in that all parts of the lead terminals other than the mounting contact surface are molded.
JP3816591A 1991-02-07 1991-02-07 Semiconductor package Pending JPH04255263A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3816591A JPH04255263A (en) 1991-02-07 1991-02-07 Semiconductor package

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3816591A JPH04255263A (en) 1991-02-07 1991-02-07 Semiconductor package

Publications (1)

Publication Number Publication Date
JPH04255263A true JPH04255263A (en) 1992-09-10

Family

ID=12517789

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3816591A Pending JPH04255263A (en) 1991-02-07 1991-02-07 Semiconductor package

Country Status (1)

Country Link
JP (1) JPH04255263A (en)

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