JP3547045B2 - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
JP3547045B2
JP3547045B2 JP11431999A JP11431999A JP3547045B2 JP 3547045 B2 JP3547045 B2 JP 3547045B2 JP 11431999 A JP11431999 A JP 11431999A JP 11431999 A JP11431999 A JP 11431999A JP 3547045 B2 JP3547045 B2 JP 3547045B2
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JP
Japan
Prior art keywords
package
lead
semiconductor chip
semiconductor device
mounting portion
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP11431999A
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Japanese (ja)
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JP2000307048A (en
Inventor
中島高士
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsui High Tech Inc
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Mitsui High Tech Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
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Priority to JP11431999A priority Critical patent/JP3547045B2/en
Publication of JP2000307048A publication Critical patent/JP2000307048A/en
Application granted granted Critical
Publication of JP3547045B2 publication Critical patent/JP3547045B2/en
Anticipated expiration legal-status Critical
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors

Landscapes

  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Description

【０００１】
【発明の属する技術分野】
本発明はプリント基板等への実装性がよく、且つ小型にできる半導体装置に関する。
【０００２】
【従来の技術】
半導体装置は高密度化とともに小型化、薄型化を要請され、入出力ピン数は多くなりリ−ド間隔、リ−ド幅とも微細になっている。
【０００３】
リードの微細化はその機械的強度を弱め、半導体装置の製造過程あるいは取扱い時においてリ−ドが変形し易くなっている。リ−ド変形はプリント基板等に実装する際、実装不良を生じさせ、また酷いときには短絡させる。
【０００４】
リ−ド変形を無くし、且つ実装面積を狭くできる半導体装置パッケージ構造として、パッケージから外方に出るリ−ドを当該パッケージの底面と同一面になるように、あるいはパッケージ底面から出ても僅かに露出させた半導体装置が提案されている。これはリ−ドがパッケージの底面と実質的に同一面にて露出し、他はパッケージ内にあるので、リ−ド変形がなく、さらにパッケージを小さくできる効果がある。反面、モ−ルド樹脂で封止しパッケージとする際、モ−ルドフラシュが生じ易く、露出したリ−ド面に付いた樹脂を除去せねばならない問題や、該パッケージをプリント基板等に前記リ−ドを接続部として実装する際に半田フィレットが形成されず実装接続強度が不十分で、その後に熱応力を繰り返して受ける際に実装箇所が剥離する等の問題が懸念される。
【０００５】
他の半導体装置パッケージとして、リ−ドを半導体装置パッケージの底面と同一面にて露出させ、該リ−ドのパッケージ外に出る延長部を折り曲げ当該パッケージの底面に前記露出したリ−ドに重ね合わせたものが提案されている。
【０００６】
【この発明が解決しようとする課題】
前記パッケージ外に出たリ−ドを折り曲げパッケージ底面に重ね合わせたものは当該パッケージ底面よりリ−ドが突出しているので、プリント基板等に実装する際に半田フィレットが形成され、実装接続強度は改善され強くなる。しかし、前記パッケージ底面と同一面に露出させたリ−ドにはモ−ルドフラッシュが付き、そのフラッシング程度にはリ−ドにより差異があり、該リ−ド面上に折り曲げて重ね合わせたリ−ドのパッケージ底面からの突出高さが個々のリ−ドによって違い、実装不良を生じるものがあったり、あるいは半田が過剰となるものがあり半田ブリッジを生じる等の問題がある。
【０００７】
また、前記パッケージの底面と同一面に露出させたリ−ドはパッケージの中間から外側まで位置しているので、パッケージの幅方向のサイズが嵩張りパッケージを小さくする上で問題である。
【０００８】
本発明は半導体装置パッケージを小さくできるとともに、プリント基板等への実装が各リ−ドとも接続不良なく且つ半田フィレットが過不足なく形成される半導体装置を得ることを目的とする。
【０００９】
【課題を解決するための手段】
本発明の要旨は、半導体チップ搭載部に半導体チップが搭載され、該半導体チップの端子と前記半導体チップ搭載部の周りに形成したリ−ドが電気的に接続され、前記半導体チップ搭載部、半導体チップ、前記リードの一部を樹脂封止しパッケージとする半導体装置において、前記リ−ドの他部はパッケージの側面下端からパッケージ外に出ているとともに折り曲げられパッケージ底面に当接して外部接続部を形成していることを特徴とする半導体装置にある。
【００１０】
【発明の実施の形態】
本発明の１実施例について図面を参照して説明する。
図面において、１は半導体チップ搭載部で、該半導体チップ搭載部１の周りにリ−ド２が複数形成されている。
【００１１】
前記半導体チップ搭載部１はディプレスされ、この実施例ではリ−ド２に対して上方に変位していて、当該半導体チップ搭載部１に接着材３を介して搭載した半導体チップ４と前記リ−ド２の上下方向の位置の差異を減らしてパッケージ５の薄型化を図るとともに、半導体チップ４とリ−ド２を電気的に接続するボンディングワイヤ−６の長さを短くし信号の高速処理ができるようにしている。
【００１２】
７は封止樹脂で、この実施例では半導体チップ搭載部１、半導体チップ４、ボンディングワイヤ−６及びリード２の一部をモ−ルドを介して封止しパッケージ５を形成している。
【００１３】
この実施例では前記パッケージ５内に半導体チップ搭載部１をすべて封止しているが、該半導体チップ搭載部１の底面はパッケージ面に露出させ、放熱性を高めるようにしてもよく、また、図２に示すように半導体チップ搭載部１の底面に放熱板８を接着材を介して接続し、該放熱板８をパッケージ面に露出させるようにしてもよい。
【００１４】
また、この実施例では半導体チップ搭載部１をリ−ド２に対して上方に変位させているが、これに限らず下方に変位させてもよい。
【００１５】
パッケージ５中のリ−ド２は図１に示すように半導体チップ搭載部１に対して傾斜させた終点部９までパッケージ底面に露出することなくパッケージ５内に位置させ、パッケージ５の側面下端から外方に出して、該出た部分でパッケージ５底面に当接するように折り曲げられ、パッケージ底面下に接して外部接続部を形成している。
【００１６】
前記のようにリ−ド２はパッケージ底面に露出することなくパッケージの側面下端から出ているので、パッケージ５から出ているリ−ド２の他部にはモ−ルドフラッシュが付かず、パッケージ５底面側に折り曲げられた各リ−ド２ともパッケージ底面に直に密接し、当該パッケージ底面からリ−ド厚み分出る突出高さは等しく、プリント基板等への実装が接続不良なく行える。
【００１７】
また、前記のようにパッケージ底面下にリ−ド２が板厚分だけ突出しているので、プリント基板等への実装に際する半田接合時に半田が吸い上げられフィレットを確実に形成し接合強度が高くなる。
【００１８】
さらに、前記パッケージ２から外方に出るリ−ド２は前記半導体チップ搭載部１に対して傾斜した終点部であるので、パッケージ２内にある部分を短くパッケージ５の平面積を小さくできる。
【００１９】
【発明の効果】
本発明は前述のようであるから、半導体装置パッケージを小さくできるとともに、プリント基板等への実装が各リ−ドとも接続不良なく行え、また半田フィレットが過不足なく形成される等の効果がある。
【図面の簡単な説明】
【図１】本発明の１実施例における半導体装置の側断面を示す図。
【図２】本発明の他の実施例における半導体装置を示す図。
【符号の説明】
１ 半導体チップ搭載部
２ リ−ド
３ 接着材
４ 半導体チップ
５ パッケージ
６ ボンディングワイヤ−
７ 封止樹脂
８ 放熱板
９ 傾斜終点部[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor device which can be easily mounted on a printed circuit board or the like and can be downsized.
[0002]
[Prior art]
Semiconductor devices are required to be smaller and thinner with higher density, and the number of input / output pins is increased, and lead intervals and lead widths are becoming finer.
[0003]
The miniaturization of the lead weakens its mechanical strength, and the lead is easily deformed during the manufacturing process or handling of the semiconductor device. The lead deformation causes a mounting failure when mounted on a printed circuit board or the like, and causes a short circuit when it is severe.
[0004]
As a semiconductor device package structure capable of eliminating the lead deformation and reducing the mounting area, the lead out of the package is flush with the bottom surface of the package, or even slightly out of the package bottom surface. An exposed semiconductor device has been proposed. This has the effect that the lead is exposed on substantially the same plane as the bottom surface of the package, and the rest is inside the package, so that the lead is not deformed and the package can be made smaller. On the other hand, when a package is formed by sealing with a mold resin, mold flash tends to occur, and the resin attached to the exposed lead surface must be removed. There is a concern that a solder fillet will not be formed when mounting the lead as a connection portion, the mounting connection strength will be insufficient, and the mounting portion will peel off when repeatedly subjected to thermal stress.
[0005]
As another semiconductor device package, a lead is exposed on the same plane as the bottom surface of the semiconductor device package, and an extension of the lead that goes out of the package is bent to overlap the exposed lead on the bottom surface of the package. A combination has been proposed.
[0006]
[Problems to be solved by the present invention]
When the lead out of the package is bent and superimposed on the bottom surface of the package, the lead protrudes from the bottom surface of the package, so that a solder fillet is formed when the lead is mounted on a printed circuit board or the like. Improved and stronger. However, a lead exposed on the same surface as the package bottom surface is provided with a mold flash, and the flushing degree differs depending on the lead. The lead is folded on the lead surface and overlapped. The protruding height of the lead from the bottom surface of the package differs depending on the individual leads, and there is a problem that there is a case where a mounting failure occurs, or there is a case where an excessive amount of solder is formed and a solder bridge is generated.
[0007]
Also, since the leads exposed on the same plane as the bottom surface of the package are located from the middle to the outside of the package, the size in the width direction of the package is a problem in reducing the bulky package.
[0008]
SUMMARY OF THE INVENTION It is an object of the present invention to provide a semiconductor device in which a semiconductor device package can be reduced in size, and which can be mounted on a printed circuit board or the like without a connection failure at each lead and a solder fillet formed without excess or shortage.
[0009]
[Means for Solving the Problems]
The gist of the present invention is that a semiconductor chip is mounted on a semiconductor chip mounting portion, and terminals of the semiconductor chip and leads formed around the semiconductor chip mounting portion are electrically connected to each other. In a semiconductor device in which a chip and a part of the lead are sealed with a resin to form a package, the other part of the lead comes out of the package from the lower end of the side surface of the package and is bent and abuts on the bottom surface of the package to form an external connection part. Is formed in the semiconductor device.
[0010]
BEST MODE FOR CARRYING OUT THE INVENTION
An embodiment of the present invention will be described with reference to the drawings.
In the drawings, reference numeral 1 denotes a semiconductor chip mounting portion, and a plurality of leads 2 are formed around the semiconductor chip mounting portion 1.
[0011]
The semiconductor chip mounting portion 1 is depressed, and in this embodiment, is displaced upward with respect to the lead 2, so that the semiconductor chip 4 mounted on the semiconductor chip mounting portion 1 with the adhesive 3 interposed therebetween. The height of the bonding wire 6 for electrically connecting the semiconductor chip 4 and the lead 2 is shortened while reducing the difference in the vertical position of the lead 2 to reduce the thickness of the package 5 and the high-speed signal processing. I can do it.
[0012]
Reference numeral 7 denotes a sealing resin. In this embodiment, a package 5 is formed by sealing a part of the semiconductor chip mounting portion 1, the semiconductor chip 4, the bonding wires 6, and the leads 2 via a mold.
[0013]
In this embodiment, the semiconductor chip mounting portion 1 is entirely sealed in the package 5, but the bottom surface of the semiconductor chip mounting portion 1 may be exposed to the package surface to enhance heat dissipation. As shown in FIG. 2, a heat radiating plate 8 may be connected to the bottom surface of the semiconductor chip mounting portion 1 via an adhesive so that the heat radiating plate 8 is exposed on the package surface.
[0014]
Further, in this embodiment, the semiconductor chip mounting portion 1 is displaced upward with respect to the lead 2, but the present invention is not limited to this, and the semiconductor chip mounting portion 1 may be displaced downward.
[0015]
The lead 2 in the package 5 is located in the package 5 without being exposed to the bottom surface of the package up to the end point 9 inclined with respect to the semiconductor chip mounting portion 1 as shown in FIG. It is bent outward so as to come into contact with the bottom surface of the package 5 at the protruding portion, and contacts the bottom of the package bottom to form an external connection portion.
[0016]
As described above, since the lead 2 protrudes from the lower end of the side surface of the package without being exposed to the bottom of the package, the other part of the lead 2 protruding from the package 5 does not have a mold flash, and 5 Each of the leads 2 bent to the bottom surface side is directly in close contact with the package bottom surface, and has the same protruding height as the lead thickness from the package bottom surface, and can be mounted on a printed circuit board or the like without connection failure.
[0017]
Also, since the leads 2 protrude below the bottom of the package by the thickness of the package as described above, the solder is sucked up at the time of soldering for mounting on a printed circuit board or the like, so that a fillet is reliably formed and the bonding strength is high. Become.
[0018]
Further, since the lead 2 extending outward from the package 2 is an end point inclined with respect to the semiconductor chip mounting portion 1, the portion inside the package 2 can be shortened and the plane area of the package 5 can be reduced.
[0019]
【The invention's effect】
Since the present invention is as described above, the semiconductor device package can be reduced in size, the mounting on a printed circuit board or the like can be performed without a connection failure with each lead, and the solder fillet can be formed without excess or shortage. .
[Brief description of the drawings]
FIG. 1 is a diagram showing a side cross section of a semiconductor device according to one embodiment of the present invention.
FIG. 2 is a diagram showing a semiconductor device according to another embodiment of the present invention.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Semiconductor chip mounting part 2 Lead 3 Adhesive 4 Semiconductor chip 5 Package 6 Bonding wire
7 sealing resin 8 heat sink 9 slope end point

Claims (2)

半導体チップ搭載部に半導体チップが搭載され、該半導体チップの端子と前記半導体チップ搭載部の周りに形成したリ−ドが電気的に接続され、前記半導体チップ搭載部、半導体チップ、前記リードの一部を樹脂封止しパッケージとした半導体装置において、前記リ−ドの他部はパッケージの側面下端からパッケージ外に出ているとともに折り曲げられパッケージ底面に当接して外部接続部を形成していることを特徴とする半導体装置。A semiconductor chip is mounted on the semiconductor chip mounting portion, and terminals of the semiconductor chip are electrically connected to leads formed around the semiconductor chip mounting portion. In the semiconductor device in which the part is sealed with a resin, the other part of the lead is out of the package from the lower end of the side surface of the package and is bent to form an external connection part in contact with the bottom of the package. A semiconductor device characterized by the above-mentioned. 前記リ−ドの一部は、半導体チップ搭載部に対して傾斜させた終点まで樹脂封止され、パッケージから出た前記リ−ドの他部は前記傾斜部以降であることを特徴とする請求項１記載の半導体装置。A part of the lead is resin-sealed to an end point inclined with respect to the semiconductor chip mounting part, and the other part of the lead coming out of the package is located after the inclined part. Item 2. The semiconductor device according to item 1.
JP11431999A 1999-04-22 1999-04-22 Semiconductor device Expired - Fee Related JP3547045B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11431999A JP3547045B2 (en) 1999-04-22 1999-04-22 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11431999A JP3547045B2 (en) 1999-04-22 1999-04-22 Semiconductor device

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Publication Number Publication Date
JP2000307048A JP2000307048A (en) 2000-11-02
JP3547045B2 true JP3547045B2 (en) 2004-07-28

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JP7479771B2 (en) * 2020-10-01 2024-05-09 三菱電機株式会社 Semiconductor device, manufacturing method thereof, and power conversion device

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