JPH04237282A - Reproduction method - Google Patents

Abstract

PURPOSE:To realize the reproduction device immune to mis-detection of a synchronizing signal while improving quality of a reproduction data. CONSTITUTION:When mis-detection of a synchronizing signal exists in the state of a mask signal, the mask signal in an erroneous timing is set and a correct synchronization detection signal cannot be read. Moreover, a symbol counter 16 is initialized by the erroneous synchronizing detection signal and the write to a memory 10 is inadequate. While the contained synchronizing signal is detected and a synchronization detection period over a prescribed period is set, a write address of a memory in which the data included in a synchronization block is initialized by synchronization detection of n (an integral number of 1 or over) times or over. Thus, the memory write address is not initialized due to erroneous synchronization detection.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a reproduction method, and more specifically to a reproduction method for reproducing data included in a data block consisting of a synchronization signal and a predetermined number of data in accordance with the synchronization signal.

0002

[Background Art] When transmitting data via a digital transmission path including an electromagnetic conversion system, a predetermined number of data is divided into blocks, a synchronization signal or code of about two symbols is added to the beginning of the block, and a predetermined error correction signal is added to the block. A transmission method is known in which a detection and correction code is added and a synchronization block formed in this manner is used as a transmission unit. For example, it is also used in recording and reproducing devices that digitally record image signals and the like using a recording medium such as a magnetic disk.

In such a synchronous block transmission system, if the synchronous signal cannot be accurately separated and detected, data cannot be reproduced accurately, so protection measures are usually taken against erroneous detection of the synchronous signal. FIG. 4 shows a schematic configuration block diagram of a circuit that separates data included in a synchronized block from an input synchronized block sequence using a synchronized signal included therein. 10 is a memory that stores data included in a synchronous block; 12 is a synchronous detection circuit that detects a synchronous signal included in the synchronous block; 14 is a synchronous detection circuit 1
This is a synchronization mask calculation logic circuit that selects one of predetermined (for example, four types) mask signals in response to a synchronization detection signal from 2 and masks the synchronization detection signal with the selected mask signal. The synchronization mask calculation logic circuit 14 determines that the synchronization detection signal while the generated synchronization mask signal is "H" is valid. 16 is a symbol counter (or address counter) that generates the lower address of the write address of the memory 10;
The counter is initialized or preset at a predetermined timing by the synchronous mask calculation logic circuit 14. Note that the address counter that generates the upper address of the write address is omitted.

FIG. 6 shows waveform diagrams of four types of mask signals generated by the synchronous mask arithmetic logic circuit 14. In the initial state, the synchronous mask arithmetic logic circuit 14 generates a mask signal M1 having a width of one data using data #4 as a timing reference. In an electromagnetic transducer system that uses a magnetic tape, a magnetic disk, etc., the synchronization signal may be delayed from the initial timing due to slippage of mechanical parts, etc., and the synchronization signal may not be detected within the mask signal M1. To cope with this, when the synchronization signal cannot be detected in the mask signal M1, the synchronization mask arithmetic logic circuit 14 generates a second mask signal M2 which is temporally wider by one data width before and after the mask signal M1. If the synchronization signal cannot be detected even with the mask signal M2, a further widened mask signal M3 is generated, and if the synchronization signal cannot be detected even with the mask signal M3, a mask signal OP that is set to "H" in the entire area is generated. . and synchronous mask calculation logic circuit 1
4, in the process of expanding the mask signal to M1, M2, M3, and OP, once a synchronization signal is detected, the mask signal M1 is output thereafter.

FIG. 2 is a timing diagram illustrating the relationship between the synchronization detection result by the synchronization detection circuit 12 and the mask signal generated by the synchronization mask arithmetic logic circuit 14. Figure 2 (1
) is the input data string, BL(n-1), BL(n)
,BL(n+1) are synchronous blocks, their SY0, SY1
is a synchronization signal, and D0, D1, D2, . . . , Dm are data. (2) is a synchronization detection signal when all synchronization signals can be detected.

[0006] (3) is a synchronization signal detection signal including synchronization signal loss, slippage, and erroneous detection, and (4) is a mask signal for the synchronization detection signal of (3). In this example, 2
The synchronization detection signal #2, which originally appears at the time, is not output, and therefore the mask signal M2 is used. Mask signal M2 makes synchronization detection signal #3 valid regardless of this third slippage of synchronization detection signal #3. As a result, the mask signal M1 is adopted, and the erroneously detected synchronization detection signal #4
is ignored, and synchronization detection signal #5 becomes valid. Further, (5) is a synchronization detection signal when no synchronization signal can be detected, and (6) is a mask signal for the synchronization detection signal of (5). As mentioned above, the mask signals are M1, M
They are expanded in order: 2, M3, OP. The mask signal M1 is selected by the synchronization detection signal enabled by the mask signal OP.

FIG. 3 shows an operation flowchart of the synchronous mask arithmetic logic circuit 14 for the cases shown in FIGS. 2(5) and 2(6). First, initialize the synchronization mask width to M1 (S1)
, if there is a synchronization detection signal from the synchronization detection circuit 12 (S2
), resets the synchronization non-detection counter that counts the number of times the synchronization signal is not detected to 0 (S3), and sets the synchronization mask width to M1.
(S4). Also, the symbol counter 16 is initialized.

If no synchronization signal is detected (S2), the synchronization non-detection counter is counted up (S5) while the symbol counter is running freely, and the count value becomes 1.
If so, set the synchronization mask width to M2 (S6, 7),
If so, set it to M3 (S6, 8), and if it is 3 or more, set it to OP (S6, 9).

[0009]

[Problems to be Solved by the Invention] However, in the conventional example described above, if the synchronization signal is erroneously detected while the mask signal OP is selected due to a burst error, etc., the write address of the memory 10 becomes inappropriate. This will result in serious malfunction. FIG. 5 is a timing chart for such a case, in which (1) shows the synchronization detection signal and (2) shows the mask signal. If there is an erroneous detection of the synchronization signal as shown at 18 in the state of the mask signal Op, this will cause the signal 22 to be detected.
As shown in FIG. 2, a mask signal M1 with an incorrect timing is set, and the correct synchronization detection signals 20 and 24 cannot be read. Furthermore, the incorrect synchronization detection signal 18 may cause the symbol counter 16 to be initialized, resulting in incorrect writing to the memory 10.

[0010] An object of the present invention is to provide a reproduction method that eliminates such inconveniences.

[0011]

[Means for Solving the Problems] A reproduction method according to the present invention is a method for reproducing data included in a synchronization block including a predetermined number of data and synchronization signals, and detects the included synchronization signals and The present invention is characterized in that, with a wide synchronization detection period set, a write address of a memory to which data included in the synchronization block is written is initialized by synchronization detection n (an integer greater than or equal to 1) times or more.

0012

[Operation] With the above means, it is possible to reduce the possibility that a memory write address is initialized due to erroneous synchronization detection. This improves the quality of reproduced data.

[0013]

Embodiments Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 shows an operation flowchart of a synchronization mask arithmetic logic circuit in an embodiment in which the present invention is applied to an image recording and reproducing apparatus. First, the synchronization mask width is initialized to M1 (S11), and the synchronization mask width is changed to M1, M2, M3, and OP according to synchronization detection and non-detection (S12) (S13 to 19), which is different from the conventional example. It's exactly the same.

In this embodiment, (S
12) and counts up the synchronization detection counter (S2
1), the count value is compared with a threshold value n (S22). The specific value of the threshold value n is determined depending on the playback mode (normal playback, special playback such as slow play, etc.). If the count value of the synchronization detection counter is n or more, the symbol counter is initialized (S23). That is, the symbol counter is initialized when the synchronization signal is properly detected to a certain extent. If it is less than n, the symbol counter is made to run freely.

If synchronization is not detected (S12), the synchronization detection counter is initialized (S24), and the symbol counter is made to run freely.

For example, in normal playback of an image recording and playback device, n=2, and in special playback, n=3. 1, the erroneously detected synchronization detection signal indicated by reference numeral 18 in FIG. 5(1) is ignored, and the symbol counter remains in a free-running state. The symbol counter uses the synchronization mask signal OP
It is initialized when a synchronization signal is detected twice in a row in this state.

In special playback (particularly search playback), burst errors or similar errors occur more frequently than in normal playback. Therefore, for example, if n=3, the mask signal O
When a synchronization signal is detected three times in succession at time P, the synchronization detection signal is made valid and the symbol counter is initialized.

In this embodiment, the protection processing for synchronization detection is adaptively changed between normal playback and special playback so that memory writing is performed under optimal conditions. This prevents image quality deterioration and ensures good playback. An image is obtained.

It goes without saying that the present invention can also be applied to recording and reproducing images, audio, and data, and to transmitting information via a transmission path.

[0021]

As can be easily understood from the above description, according to the present invention, it is possible to provide a playback device that is resistant to erroneous detection of synchronization signals.

[Brief explanation of the drawing]

FIG. 1 is an operational flowchart of main parts of an embodiment of the present invention.

FIG. 2 is a waveform diagram showing the relationship between a synchronization detection signal and a mask signal in a conventional example.

FIG. 3 is an operational flowchart of conventional synchronization detection protection processing.

FIG. 4 is a schematic block diagram of a reproducing circuit.

FIG. 5 is a timing diagram showing a memory write malfunction in a conventional example.

FIG. 6 is an explanatory diagram of four types of mask signals.

[Explanation of symbols]

10: Memory 12: Synchronization detection circuit 14: Synchronization mask operation logic circuit 16: Symbol counter 1
8: Synchronization error detection signal 20: Synchronization detection signal 22:
Synchronization mask signal M1 24: Synchronization detection signal

Claims (2)

[Claims] 1. A method for reproducing data included in a synchronization block including a predetermined number of data and a synchronization signal, the method comprising:
The included synchronization signal is detected, and a synchronization detection period wider than a predetermined period is set, and by detecting synchronization more than n times (an integer of 1 or more), the write address of the memory where the data included in the synchronization block will be written is initialized. A regeneration method characterized by: 2. The reproducing method according to claim 1, wherein n is changeable depending on a set operation mode.