JPH0421976U - - Google Patents
Info
- Publication number
- JPH0421976U JPH0421976U JP6270490U JP6270490U JPH0421976U JP H0421976 U JPH0421976 U JP H0421976U JP 6270490 U JP6270490 U JP 6270490U JP 6270490 U JP6270490 U JP 6270490U JP H0421976 U JPH0421976 U JP H0421976U
- Authority
- JP
- Japan
- Prior art keywords
- digital data
- holding
- data
- conversion
- holding means
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000001514 detection method Methods 0.000 claims description 3
- 238000006243 chemical reaction Methods 0.000 claims 4
- 238000010586 diagram Methods 0.000 description 4
Landscapes
- Measurement Of Current Or Voltage (AREA)
Description
第１図は本考案の一実施例の構成を示すブロツ
ク図。第２図は本考案の一実施例の作用の説明に
供するタイミング図。第３図は本考案の一実施例
におけるデータセレクタの入力選択を示す図。第
４図は従来例の構成を示すブロツク図。
１……Ａ／Ｄ変換器、２，３，４，１３及び１
５……ラツチ回路、５及び６……比較器、１１…
…トグルフリツプフロツプ、１２……データセレ
クタ、２０……最大値検出回路、２１……最小値
検出回路、２２……読み出し回路。
FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. FIG. 2 is a timing diagram for explaining the operation of one embodiment of the present invention. FIG. 3 is a diagram showing input selection of a data selector in an embodiment of the present invention. FIG. 4 is a block diagram showing the configuration of a conventional example. 1...A/D converter, 2, 3, 4, 13 and 1
5...Latch circuit, 5 and 6...Comparator, 11...
...Toggle flip-flop, 12...Data selector, 20...Maximum value detection circuit, 21...Minimum value detection circuit, 22...Readout circuit.
Claims (1)
換手段と、Ａ／Ｄ変換手段により変換されたデジ
タルデータ中の最大値データを検出して保持する
第１保持手段と、Ａ／Ｄ変換手段により変換され
たデジタルデータ中の最小値データを検出して保
持する第２保持手段と、第１保持手段に保持され
ているデータの読み出し、第２保持手段に保持さ
れているデータの読み出し、または所定の間隔で
第１保持手段に保持されているデータと第２保持
手段に保持されているデータとを交互に読み出し
の１つを２つの切替指示信号の組合せに伴つて選
択する選択制御手段とを備えたことを特徴とする
デジタルデータのピーク検出・読み出し回路。 A/D conversion means for converting an input signal into digital data; first holding means for detecting and holding maximum value data in the digital data converted by the A/D conversion means; and conversion by the A/D conversion means. a second holding means for detecting and holding the minimum value data in the digital data stored in the digital data; and selection control means for alternately reading data held in the first holding means and data held in the second holding means at intervals and selecting one of them in response to a combination of two switching instruction signals. A digital data peak detection/readout circuit characterized by:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6270490U JPH0733174Y2 (en) | 1990-06-15 | 1990-06-15 | Digital data peak detection / readout circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6270490U JPH0733174Y2 (en) | 1990-06-15 | 1990-06-15 | Digital data peak detection / readout circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0421976U true JPH0421976U (en) | 1992-02-24 |
| JPH0733174Y2 JPH0733174Y2 (en) | 1995-07-31 |
Family
ID=31592097
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6270490U Expired - Fee Related JPH0733174Y2 (en) | 1990-06-15 | 1990-06-15 | Digital data peak detection / readout circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0733174Y2 (en) |
-
1990
- 1990-06-15 JP JP6270490U patent/JPH0733174Y2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0733174Y2 (en) | 1995-07-31 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |