JPS63147038U - - Google Patents
Info
- Publication number
- JPS63147038U JPS63147038U JP4012887U JP4012887U JPS63147038U JP S63147038 U JPS63147038 U JP S63147038U JP 4012887 U JP4012887 U JP 4012887U JP 4012887 U JP4012887 U JP 4012887U JP S63147038 U JPS63147038 U JP S63147038U
- Authority
- JP
- Japan
- Prior art keywords
- sample
- circuit
- counter
- signal
- hold circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000006243 chemical reaction Methods 0.000 claims description 5
- 238000005070 sampling Methods 0.000 claims description 3
- 238000010586 diagram Methods 0.000 description 3
Landscapes
- Analogue/Digital Conversion (AREA)
Description
第１図は本考案の一実施例を示すブロツク図、
第２図は従来のＡ／Ｄ変換回路のブロツク図、第
３図は従来のマイクロコンピユータの動作を示す
フロー図である。
１…選択回路、２…サンプリングホールド回路
、３…Ａ／Ｄ変換部、４…Ａ／Ｄ変換回路、５…
マイクロコンピユータ、６…カウンタ、７…信号
線。
FIG. 1 is a block diagram showing an embodiment of the present invention.
FIG. 2 is a block diagram of a conventional A/D conversion circuit, and FIG. 3 is a flow diagram showing the operation of a conventional microcomputer. DESCRIPTION OF SYMBOLS 1... Selection circuit, 2... Sampling hold circuit, 3... A/D conversion part, 4... A/D conversion circuit, 5...
Microcomputer, 6...Counter, 7...Signal line.
Claims (1)
数のアナログ信号の一つを選択する選択回路と、
該選択回路によつて選択されたアナログ信号をサ
ンプリングして保持するサンプルホールド回路と
、該サンプルホールド回路のアナログ出力信号を
デイジタル信号に変換するＡ／Ｄ変換部とを有し
、前記カウンタは前記サンプルホールド回路のサ
ンプリング期間を決定するためのサンプリング信
号に応答してカウント動作を行うことを特徴とす
るＡ／Ｄ変換回路。 a counter; a selection circuit that selects one of the plurality of analog signals according to the output signal of the counter;
The counter includes a sample and hold circuit that samples and holds the analog signal selected by the selection circuit, and an A/D conversion section that converts the analog output signal of the sample and hold circuit into a digital signal. An A/D conversion circuit that performs a counting operation in response to a sampling signal for determining a sampling period of a sample-and-hold circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4012887U JPS63147038U (en) | 1987-03-18 | 1987-03-18 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4012887U JPS63147038U (en) | 1987-03-18 | 1987-03-18 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63147038U true JPS63147038U (en) | 1988-09-28 |
Family
ID=30853936
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4012887U Pending JPS63147038U (en) | 1987-03-18 | 1987-03-18 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63147038U (en) |
-
1987
- 1987-03-18 JP JP4012887U patent/JPS63147038U/ja active Pending