JPS62186017U - - Google Patents
Info
- Publication number
- JPS62186017U JPS62186017U JP7364686U JP7364686U JPS62186017U JP S62186017 U JPS62186017 U JP S62186017U JP 7364686 U JP7364686 U JP 7364686U JP 7364686 U JP7364686 U JP 7364686U JP S62186017 U JPS62186017 U JP S62186017U
- Authority
- JP
- Japan
- Prior art keywords
- converter
- channel
- recording paper
- recording
- recorder
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000005259 measurement Methods 0.000 claims description 6
- 230000015654 memory Effects 0.000 claims description 2
- 238000006243 chemical reaction Methods 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 4
- 230000006870 function Effects 0.000 description 1
- 238000000034 method Methods 0.000 description 1
Landscapes
- Recording Measured Values (AREA)
Description
第１図ないし第４図はこの考案による多チヤン
ネル記録計の実施例に係り、第１図はその機能ブ
ロツク図、第２図は回路構成を示すブロツク線図
、第３図は記録紙上における各波形データ記録位
置の説明図、第４図はマイクロコンピユータによ
る記録位置制御の手順を示すフローチヤート、第
５図は従来装置の回路構成を示すブロツク線図で
ある。
図中、１Ｓないし４Ｓは測定回路、２Ａないし
２ＤはＡ／Ｄコンバータ、３Ａないし３Ｄはスト
レージメモリ、４はマイクロコンピユータ、５は
レコーダ、６は記録紙である。
Figures 1 to 4 relate to an embodiment of the multi-channel recorder according to this invention. Figure 1 is a functional block diagram thereof, Figure 2 is a block diagram showing the circuit configuration, and Figure 3 is a diagram showing the various functions on the recording paper. FIG. 4 is a flowchart showing the procedure for controlling the recording position by a microcomputer, and FIG. 5 is a block diagram showing the circuit configuration of a conventional device. In the figure, 1S to 4S are measurement circuits, 2A to 2D are A/D converters, 3A to 3D are storage memories, 4 is a microcomputer, 5 is a recorder, and 6 is recording paper.
Claims (1)
みマイクロコンピユータにて制御される複数のチ
ヤンネル測定回路を有し、該測定回路に入力され
た信号のデイジタル変換データをレコーダに加え
て記録紙にそのアナログ波形を記録させる多チヤ
ンネル記録計において、 上記測定回路は所定チヤンネルの測定回路が他
と異なる分解能のＡ／Ｄコンバータを備えてなり
、 上記メモリから読み出された上記Ａ／Ｄコンバ
ータの波形データには上記マイクロコンピユータ
を介してチヤンネルごとに設定されたオフセツト
データが加算され、そのアナログ波形がそれぞれ
上記記録紙の所定位置に記録されるようにしたこ
とを特徴とする多チヤンネル記録計。 (2) 上記各測定回路に設けられたＡ／Ｄコンバ
ータのうち最高分解能を有するＡ／Ｄコンバータ
を介して得られる波形データが、上記記録紙の有
効記録幅全域を記録領域として記録されることを
特徴とする実用新案登録請求の範囲第１項記載の
多チヤンネル記録計。 (3) 上記各測定回路に設けられたＡ／Ｄコンバ
ータのうち上記最高分解能より低い分解能のＡ／
Ｄコンバータにて得られる波形データは、上記記
録紙の有効記録幅の１／ｎを記録領域として記録
されることを特徴とする実用新案登録請求の範囲
第１項記載の多チヤンネル記録計。[Claims for Utility Model Registration] (1) A system having a plurality of channel measurement circuits each including an A/D converter and a memory and controlled by a microcomputer, and converting digital conversion data of a signal input to the measurement circuit. In a multi-channel recorder that records analog waveforms on recording paper in addition to a recorder, the measurement circuit for a predetermined channel is equipped with an A/D converter with a different resolution from the others, Offset data set for each channel is added to the waveform data of the A/D converter via the microcomputer, and each analog waveform is recorded at a predetermined position on the recording paper. Multi-channel recorder. (2) The waveform data obtained through the A/D converter with the highest resolution among the A/D converters provided in each of the above measurement circuits is recorded over the entire effective recording width of the recording paper as a recording area. A multi-channel recorder according to claim 1, which is characterized by: (3) Among the A/D converters installed in each of the above measurement circuits, the A/D converter has a resolution lower than the maximum resolution above.
2. The multi-channel recorder according to claim 1, wherein the waveform data obtained by the D converter is recorded in a recording area of 1/n of the effective recording width of the recording paper.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7364686U JPH051773Y2 (en) | 1986-05-16 | 1986-05-16 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7364686U JPH051773Y2 (en) | 1986-05-16 | 1986-05-16 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS62186017U true JPS62186017U (en) | 1987-11-26 |
| JPH051773Y2 JPH051773Y2 (en) | 1993-01-18 |
Family
ID=30918160
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7364686U Expired - Lifetime JPH051773Y2 (en) | 1986-05-16 | 1986-05-16 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH051773Y2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02113121U (en) * | 1989-02-24 | 1990-09-11 |
-
1986
- 1986-05-16 JP JP7364686U patent/JPH051773Y2/ja not_active Expired - Lifetime
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02113121U (en) * | 1989-02-24 | 1990-09-11 |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH051773Y2 (en) | 1993-01-18 |
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