JPH04217364A - Photoelectric conversion device and manufacture thereof - Google Patents

Abstract

PURPOSE:To obtain a highly reliable photoelectric conversion element without picture element defects without reduction in the effective picture element area as much as possible by a method wherein specified masking is performed again after a upper electrode is patterned. CONSTITUTION:A lower electrode 102, a photoconductive film 106, and an upper electrode 17 are configured on a substrate 101 in that order, and the upper electrode separation pattern is designed so that it is arranged within the photoconductive film separation pattern. The upper electrode is patterned to be specified size beforehand, and the resist that has been used is removed. Then, the masking 108 is performed which is in the size where a excessive interval L ranging from the circumference of the upper electrode 107 to the circumference of the photoconductive film separation pattern is taken into consideration. Isotropic etching for one part of or all over the photoconductive film 106 is performed on the N-type or P-type upper semiconductor layer 105 where high-density impurities are added.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a photoelectric conversion element used in a long line sensor, an area sensor, etc., and particularly to a semiconductor photoelectric conversion element, and a method for manufacturing the same.

0002

[Prior Art] In recent years, facsimiles, digital copying machines,
As image information processing devices such as image readers and video cameras become more widespread, long line sensors with one-dimensional arrays of photosensors and area sensors with two-dimensional arrays are increasingly being used. became. A semiconductor photoelectric conversion element is used in this sensor for the following reason.

(1) To enable separation of functions according to the characteristics of the material,
Can be laminated.

0004 (2) It is possible to create a large area at once.

(3) It can be manufactured using a low temperature process that is not limited by the substrate.

[0006] (4) The production process is simple and costs can be reduced.

In particular, a type of photodiode that blocks injection of carriers from the electrode is most suitable for the above-mentioned photosensor because the device structure allows for high sensitivity due to a high S/N ratio.

When this photodiode is realized by laminating thin films on a substrate, electrodes are placed above and below the photoconductive film, but each pixel is When a collective sensor structure that can operate independently for each pixel is required, in order to suppress crosstalk between each pixel, in the manufacturing process, not only the lower electrode is patterned, but also the upper electrode is patterned by etching. Also, some or all of the photoconductive film is removed between pixels.

[0009]

[Problems to be Solved by the Invention] However, the above-mentioned pixel separation method has not yet been fully developed, and various problems remain. For example, when separating pixels, the relationship between the relative position and size of the separation pattern of the upper electrode and the separation pattern of the photoconductive film has not been sufficiently studied.
The effective pixel area per area or length becomes smaller,
This may cause a decrease in sensitivity, or conversely, a pixel detection defect may occur due to defects such as short circuits due to the lack of a necessary separation interval.

That is, as shown in FIG. 1, a lower electrode 102 is patterned on a substrate 101, and then, for example,
Starting from the substrate side, one semiconductor type (N type or P type)
A lower semiconductor layer 103 doped with a high concentration of impurity indicating a semiconductor type, a semiconductor layer 104 containing no impurity or only a small amount of impurity, and an upper semiconductor layer 104 doped with a high concentration of impurity indicating the other semiconductor type (P type or N type). When manufacturing a photoelectric conversion element having a photoconductive film 106 composed of a layer 105 and an upper electrode 107, the edges of the upper electrode separation pattern are To match the edges of the photoconductive film separation pattern (Figure 1
(a)), using the photoresist used to form the upper electrode during manufacturing, if isotropic etching such as wet etching or CDE is performed to remove the inter-pixel region of the photoconductive film, the upper electrode 107 and the photoconductive film 10
The difference in the material of the photoconductive film 106 causes a difference in the amount of side etching (see FIG. 1(b)), and as a result, the edge of the upper electrode 107 collapses and, for example, the upper part of the photoconductive film 106 has a high concentration. This results in contact with parts other than the impurity layer (which has been removed outside the pixel area by the etching described above) (see Figure 1).
(see (c)), a short circuit or a state close to it occurs, resulting in a pixel defect. In addition, as the above etching, R
When anisotropic etching such as IE is used, the risk of side etching as described above is eliminated, but the edge surface of the pixel area of the photoconductive film exposed by removal outside the pixel area is removed by the above etching (this is physical etching). ), the electrical resistance in this area decreases and leaks are more likely to occur. Therefore, in this case as well, pixel defects occur.

[0011]

OBJECTS OF THE INVENTION The present invention has been made based on the above-mentioned circumstances, and after patterning the upper electrode, a predetermined masking is performed again, thereby reducing the pixel area while avoiding a reduction in the effective pixel area as much as possible. The aim is to provide a highly reliable photoelectric conversion element that is free from defects.

0012

[Means for solving the problem] Therefore, in the present invention,
In a method for manufacturing a photoelectric conversion element in which a lower electrode, a photoconductive film, and an upper electrode are deposited in this order on a substrate, and then etched to form regions of the upper electrode and photoconductive film for each pixel, the upper electrode is formed in a predetermined pattern, masked to a size such that there is a predetermined surplus gap around the upper electrode during the etching, and when a region of the photoconductive film is formed by etching, the periphery of the upper electrode is A physical spacing is left on the exposed surface of the photoconductive film to maintain the electrical resistance of the photoconductive film at a predetermined value.

Furthermore, as a result of this method, a lower electrode, a photoconductive film, and an upper electrode are formed on the substrate in that order, and the regions of the upper electrode and the photoconductive film are formed separately for each pixel. In the photoelectric conversion element, the upper electrode leaves an extra gap around the upper electrode with a dimension that ensures the required electrical resistance of the photoconductive film with respect to the upper electrode, and the photoconductive film corresponds to each pixel area. It is located on the inside of the top surface.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be explained in detail below based on the illustrated embodiments. FIG. 2 illustrates the principle of the method for manufacturing the photoelectric conversion element of the present invention. That is, here, the upper electrode separation pattern is designed to be inside the photoconductive film separation pattern. In this case, the upper electrode is patterned to the required size in advance, the resist used at that time is removed, and then a pattern is formed from the periphery of the upper electrode 107 to the periphery of the photoconductive film separation pattern. Masking 108 is performed with a size that takes into consideration the extra spacing L in advance (see FIG. 2(a)), and etching a part or all of the photoconductive film 106 is performed using, for example, N-type or Isotropic etching is performed on the P-type upper semiconductor layer 105 (see FIG. 2(b)).

What must be carefully noted here is that if the size of the upper electrode separation pattern is made smaller than necessary, the effective pixel area will decrease, resulting in a decrease in sensitivity. Therefore, in the present invention, it is desirable to set the above-mentioned surplus interval L as small as possible, but it must be set to a size that satisfies the condition that the manufactured photoelectric conversion element does not generate pixel detection defects such as short circuits. must be retained.

Therefore, in the present invention, the following design considerations are made to the size of the mask for etching the photoconductive film. For example, when performing isotropic etching as shown in FIG. 2, the upper electrode 1 after pixel separation is
07 and the photoconductive film 106 as shown in FIG. 3, design values for the upper electrode separation pattern and the photoconductive film separation pattern are determined.

That is, when the etching is isotropic, the horizontal distance l between the periphery of the upper electrode 107 and the periphery of the pixel isolation region of the photoconductive film 106 is equal to Etching depth d of the sexual film 106
For E, maintain the relationship l=L-dE>0 (provided that dE or L ensures that the electrical resistance of the photoconductive film 106 to the upper electrode 107 does not cause a short circuit). Based on this, the extra interval L due to masking 108 is designed.

If the etching of the photoconductive film 106 is anisotropic, the etching depth dE of the photoconductive film 106 may have structural defects such as plasma damage there. , the electrical resistance R that should originally exist
Since it is considered that there is no dE, dE is excluded, and the above-mentioned interval l is l=L (however, depending on L, the above-mentioned upper electrode 107
The electrical resistance RL of the photoconductive film 106 with respect to
Design the extra spacing L by .

For the above reasons, it is possible to construct a collective photoelectric conversion element such as a line sensor or an area sensor that is free from pixel detection defects while avoiding a decrease in sensitivity as much as possible, and it is possible to make it highly reliable.

Next, the production of the photoelectric conversion element of the present invention will be specifically explained with reference to some examples.

[0021]

[Embodiment 1] As shown in FIG. 5, first, a quartz substrate 501
On the top, SiH4 gas was applied using the normal LP-CVD method at a flow rate of 50SCCM, a substrate temperature of 620°C, and an internal pressure of 0.3To.
The polysilicon layer 502 is formed by depositing the polysilicon layer 502 for 10 minutes under the conditions of rr. This polysilicon layer is etched into a desired shape using a normal photolithography process.

[0022] Thereafter, in an O2 atmosphere at 900°C, 2
．． Thermal oxidation is performed for 5 hours to form an oxide film 504 with a thickness of 500 Å on the surface of the polysilicon layer 502.

[0023] Next, by the usual LP-CVD method, S
iH4 gas flow rate 50SCCM, substrate temperature 620℃,
The polysilicon layer 505 is formed by depositing for 30 minutes at an internal pressure of 0.3 Torr. This polysilicon layer was implanted with normal ions at a dose of 8 x 1015 cm-2.
, B- ions were implanted into the entire surface under conditions of 60 keV,
Thereafter, annealing is performed in an N2 atmosphere at 800°C to diffuse B- ions and form the polysilicon layer 5.
05 is P type. Thereafter, the polysilicon layer 505 is etched into a desired shape by a normal photolithography process, and the M
This is used as the gate electrode of the OS transistor.

[0024] After this, P +
Ions are implanted into the entire surface, and then annealing is performed in an N2 atmosphere at 800°C to diffuse P+ ions and form the source and drain electrodes 5 of the MOS transistor.
03,503' is formed.

[0025] Subsequently, by the usual plasma CVD method,
SiH4 gas at a flow rate of 0.5SCCM, NH3 gas at a flow rate of 14.4SCCM, and H2 gas at a flow rate of 4.5S.
CCM was deposited for 160 minutes under the conditions of a substrate temperature of 200°C, RF power of 3.5 W, and internal pressure of 0.15 Torr, and the SiN layer and oxide film 504 were etched into the desired shape by a normal photolithography process to form the source electrode. Then, a hole is opened for the extraction part of the drain electrode.

[0026] On top of this, 10,000 Al was applied by sputtering.
Å is deposited and etched into a desired shape by a normal photolithography process to form a wiring electrode 507 from a MOS transistor.

[0027] Next, by the usual plasma CVD method,
SiH4 gas at a flow rate of 0.5SCCM, NH3 gas at a flow rate of 14.4SCCM, and H2 gas at a flow rate of 4.5S.
CCM is deposited for 160 minutes under the conditions of a substrate temperature of 200 DEG C., RF power of 3.5 W, and internal pressure of 0.15 Torr to form a SiN layer 508 of 8000 .ANG., which is used as a passivation film for underlying circuits such as MOS transistors. This SiN layer is etched into a desired shape by a normal photolithography process to partially expose the surface of the Al electrode.

Next, by the usual plasma CVD method, S
Deposition was performed for 140 minutes under the following conditions: i2 H6 gas flow rate 1.0 SCCM, H2 gas flow rate 48.0 SCCM, substrate temperature 300 °C, RF power - 1.0 W, internal pressure 1.15 Torr, and undoped amorphous Silicon (ia-Si:H
) A layer 509 of 8000 Å is formed, followed by 0.1 SCCM of SiH4 gas, 0.2 SCCM of B2 H6 gas diluted with 10% H2, and H2 gas 7 without breaking the vacuum.
4.5SCCM, substrate temperature 200℃, RF power -33.
Deposition was carried out for 20 minutes under the conditions of 0 W and internal pressure of 2.0 Torr, and P
A + type microcrystalline silicon (P+ -μc-Si:H) layer 510 is formed to a thickness of 1000 Å.

Thereafter, ITO is deposited to a thickness of 700 Å by sputtering and etched into a desired shape by a normal photolithography process to form the upper electrode 511 of the photodiode.
are formed separately for each pixel.

Next, according to the design, masking is performed so that the shape thereof is placed 3 μm outside the pattern of the electrode 511, and the etching of the P+-μc-Si:H layer 510 is performed by wet etching using a normal photolithography process. Do it by law.

[0031] Thereafter, by the usual plasma CVD method,
SiH4 gas at a flow rate of 0.5SCCM, NH3 gas at a flow rate of 14.4SCCM, and H2 gas at a flow rate of 4.5S.
The SiN layer 512 is deposited to a thickness of 8000 Å by CCM under the conditions of a substrate temperature of 200° C., RF power of 3.5 W, and internal pressure of 0.15 Torr for 160 minutes. This SiN layer 512
Etched into the desired shape using a normal photolithography process,
Open a hole for the upper wiring electrode to take out.

[0032] On top of this, 10,000 Al was applied by sputtering.
The film is deposited and etched into a desired shape using a normal photolithography process to form an upper wiring electrode 513 to produce a line sensor, which is a specific example of the photoelectric conversion element of the present invention.

As a result of checking the operation of the photoelectric conversion element formed by the above process, no pixel defects were detected.

[0034]

[Embodiment 2] Next, a second embodiment will be specifically explained with reference to FIG.

First, a normal LP-
Using the CVD method, SiH4 gas was supplied at a flow rate of 50SCCM.
A polysilicon layer 602 is formed by depositing for 10 minutes at a substrate temperature of 620° C. and an internal pressure of 0.3 Torr. This polysilicon layer is etched into a desired shape using a normal photolithography process.

[0036] Thereafter, in an O2 atmosphere at 900°C,
．． Thermal oxidation is performed for 5 hours to form an oxide film 604 with a thickness of 500 Å on the surface of the polysilicon layer 602.

[0037] Subsequently, by the usual LP-CVD method, S
iH4 gas flow rate 50SCCM, substrate temperature 620℃,
The polysilicon layer 605 is deposited for 30 minutes at an internal pressure of 0.3 Torr. This polysilicon layer was implanted with normal ions at a dose of 8 x 1015 cm-2.
, B- ions were implanted into the entire surface under conditions of 60 keV,
Thereafter, annealing is performed in a N2 atmosphere at 800°C to diffuse B- ions and form the polysilicon layer 6.
05 is P type. Thereafter, the polysilicon layer 605 is etched into a desired shape by a normal photolithography process, and M
This is used as the gate electrode of the OS transistor.

[0038] After this, P +
Ions are implanted into the entire surface, and then annealing is performed in a N2 atmosphere at 800°C to diffuse P+ ions and form the source and drain electrodes 6 of the MOS transistor.
03, 603' is formed.

[0039] Subsequently, by the usual plasma CVD method,
SiH4 gas at a flow rate of 0.5SCCM, NH3 gas at a flow rate of 14.4SCCM, and H2 gas at a flow rate of 4.5S.
CCM was deposited for 160 minutes under the conditions of a substrate temperature of 200°C, RF power of 3.5 W, and internal pressure of 0.15 Torr, and the SiN layer and oxide film 604 were etched into the desired shape by a normal photolithography process to form the source electrode. Then, a hole is opened for the extraction part of the drain electrode.

[0040] On top of this, 10,000 Al was applied by sputtering.
A film is deposited to form a wiring electrode 607 from a MOS transistor.

[0041] Subsequently, by the usual plasma CVD method,
SiH4 gas at a flow rate of 0.5SCCM, NH3 gas at a flow rate of 14.4SCCM, and H2 gas at a flow rate of 4.5S.
CCM was deposited for 160 minutes under the conditions of substrate temperature of 200 DEG C., RF power of 3.5 W, and internal pressure of 0.15 Torr to form a SiN layer of 8000 .ANG. to form a passivation film 608 for an underlying circuit such as a MOS transistor. This SiN layer is etched into a desired shape by a normal photolithography process to partially expose the surface of the Al electrode.

Next, by the usual plasma CVD method, S
N+ type amorphous silicon ( n+ -a-Si:H
) A layer 609 of 1000 Å was formed, and then Si2 H6 gas was applied at 1.0 SCCM and H2 gas was applied at 48.0 SCCM without breaking the vacuum, the substrate temperature was 300°C, and the RF power was -1.
．． Undoped amorphous silicon (i-μc-Si:H) was deposited for 140 minutes at 0 W and an internal pressure of 1.15 Torr.
A layer 610 was formed to a thickness of 8000 Å, and then, without breaking the vacuum, SiH4 gas was applied at 0.1 SCCM, B2 H6 gas diluted with 10% H2 at 0.2 SCCM, and H2 gas at 74.5 SCCM, the substrate temperature was 200°C, and the RF power was applied. 33
．． Deposited for 20 minutes under the conditions of 0W and internal pressure of 2.0 Torr,
P+ type microcrystalline silicon (P+ -μc-Si:H)
A layer 611 is formed to a thickness of 1000 Å.

Thereafter, ITO is deposited to a thickness of 700 Å by sputtering and etched into a desired shape by a normal photolithography process to form the upper electrode 612 of the photodiode.
are formed separately for each pixel.

Next, according to the design, masking is performed so that the shape is placed 3 μm outside the pattern of the electrode 511, and the P+-μc-Si:H layer 611, i-
μc-Si:H layer 610, n+-μc-Si:H layer 6
Etching No. 09 is performed by RIE in a normal photolithography process.

[0045] Thereafter, by ordinary plasma CVD method,
SiH4 gas at a flow rate of 0.5SCCM, NH3 gas at a flow rate of 14.4SCCM, and H2 gas at a flow rate of 4.5S.
The SiN layer 613 is deposited to a thickness of 8000 Å by depositing CCM under the conditions of a substrate temperature of 200° C., RF power of 3.5 W, and internal pressure of 0.15 Torr for 160 minutes. This SiN layer 613
Etched into the desired shape using a normal photolithography process,
Open a hole for the upper wiring electrode to take out.

[0046] On top of this, 10,000 Al was applied by sputtering.
The film is deposited and etched into a desired shape using a normal photolithography process to form an upper wiring electrode 614, thereby creating a line sensor which is one specific example of the photoelectric conversion element of the present invention.

As a result of checking the operation of the photoelectric conversion element formed by the above process, no pixel defects were detected.

[0048] In the present invention, as clarified in the above examples, the photoconductive film is doped with a high concentration impurity exhibiting one semiconductor type (N type or P type) in order from the substrate side. The lower semiconductor layer, the semiconductor layer with no or only a trace amount of impurities added, the other semiconductor type (
The photoconductive film may be composed of an upper semiconductor layer doped with a high concentration impurity exhibiting P type or N type, and the entire photoconductive film or only the upper semiconductor layer may be removed by etching in a region outside the pixel. .

[0049] In addition, the photoconductive film includes, in order from the substrate side, a semiconductor layer in which no impurity is added or only a trace amount of impurity is added, and a semiconductor layer in which one semiconductor layer is doped with a high concentration impurity indicating one semiconductor type (P type or N type). The photoconductive film may be composed of a semiconductor layer, and the entire photoconductive film or only the semiconductor layer may be removed by etching in a region outside the pixel.

[0050] The above-mentioned "microcrystal" used in the present invention refers to a structure in which minute crystal grains having a grain size of several tens of angstroms to several hundreds of angstroms are mixed in an amorphous structure. Note that the grain size of the crystal grains can be determined by X-ray diffraction, Raman spectroscopy, or the like.

[0051]

Effects of the Invention The present invention has been described in detail above, and after patterning the upper electrode, a predetermined masking is performed again, thereby preventing pixel defects while avoiding a reduction in the effective pixel area as much as possible. Therefore, it is possible to provide a highly reliable photoelectric conversion element.

[Brief explanation of the drawing]

FIGS. 1A to 1C are explanatory diagrams illustrating the manufacturing process of a photoelectric conversion element by a conventional method.

FIGS. 2(a) to 2(c) are explanatory diagrams for explaining one embodiment of the present invention.

FIG. 3 is a longitudinal sectional side view showing essential parts of the photoelectric conversion element of the present invention.

FIG. 4 is a longitudinal sectional side view showing essential parts of the photoelectric conversion element of the present invention.

FIG. 5 is a longitudinal sectional side view of a first specific example of the present invention.

FIG. 6 is a longitudinal sectional side view of a second specific example of the present invention.

[Explanation of symbols]

101　　　　Substrate 102 Lower electrode 103 Semiconductor layer 104 Semiconductor layer 105 Semiconductor layer 106 Photoconductive film 107 Upper electrode

Claims (1)

[Scope of Claims] [Claim 1] A lower electrode, a photoconductive film, and an upper electrode are deposited in this order on a substrate, and then, by etching, regions of the upper electrode and photoconductive film are formed for each pixel. In the method for manufacturing a photoelectric conversion element, the upper electrode is formed in a predetermined pattern, and during the etching, the upper electrode is masked to a size with a predetermined surplus gap around the upper electrode, and the photoconductive film is formed by etching. A photoelectric conversion element characterized in that when forming the region, a physical distance is left on the exposed surface of the photoconductive film to maintain the electrical resistance of the photoconductive film at a predetermined value with respect to the periphery of the upper electrode. manufacturing method. 2. The masking is performed to a dimension such that the extra distance L between the periphery of the upper electrode and the periphery of the photoconductive film is larger than the etching thickness dE of the photoconductive film, and the etching is uniform. 3. The method for manufacturing a photoelectric conversion element according to claim 1, characterized in that the process is performed by directional etching.Claim 3: The extra distance L between the periphery of the upper electrode and the periphery of the photoconductive film is the periphery of the upper electrode. 2. The masking is performed to a size such that the physical spacing is such that the electrical resistance of the photoconductive film can be maintained at a predetermined value, and the etching is performed by anisotropic etching. [Claim 4] A method for manufacturing a photoelectric conversion element, comprising forming a lower electrode, a photoconductive film, and an upper electrode in that order on a substrate, and forming regions of the upper electrode and the photoconductive film separately for each pixel. In the photoelectric conversion element, the upper electrode is arranged around the photoconductive film corresponding to each pixel area, leaving an extra gap around the upper electrode with a dimension that ensures the required electrical resistance of the photoconductive film with respect to the upper electrode. 5. A photoelectric conversion element, characterized in that the photoconductive film is arranged such that, in order from the substrate side, a high concentration impurity exhibiting one semiconductor type (N-type or P-type) is disposed on the inside of the upper surface of the film. A lower semiconductor layer doped with impurities, a semiconductor layer with no impurities or only a trace amount of impurities, and a semiconductor layer of the other semiconductor type (P).
5. The photoelectric conversion element according to claim 4, wherein the photoelectric conversion element is composed of an upper semiconductor layer doped with a high concentration impurity exhibiting a type (type or N type), and wherein only the upper semiconductor layer is removed by etching in a region outside the pixel. 6. The photoconductive film includes, in order from the substrate side:
A lower semiconductor layer doped with a high concentration of impurity indicating one semiconductor type (N type or P type), a semiconductor layer to which no impurity is added or only a trace amount of impurity is added, and a lower semiconductor layer indicating the other semiconductor type (P type or N type). 5. The photoelectric conversion element according to claim 4, wherein the photoelectric conversion element is composed of an upper semiconductor layer doped with a high concentration of impurity shown in FIG. The photoconductive film is sequentially formed from the substrate side,
It consists of a semiconductor layer to which no impurity is added or only a small amount of impurity is added, and an upper semiconductor layer to which a high concentration impurity indicating one semiconductor type (P type or N type) is added, and only the above semiconductor layer forms the area outside the pixel. 8. The photoelectric conversion element according to claim 4, wherein the photoconductive film is removed by etching in order from the substrate side.
It consists of a semiconductor layer to which no impurity is added or only a small amount of impurity is added, and an upper semiconductor layer to which one semiconductor type (P type or N type) is added with a high concentration impurity, and the entire photoconductive film is located outside the pixel. 4. The photoelectric conversion element according to claim 4, wherein the photoconductive film is removed by etching in the region.Claim 9: The photoconductive film is made of hydrogenated amorphous silicon. Photoelectric conversion element described in