JPH0513803A - Photoelectric transfer device - Google Patents

Abstract

PURPOSE:To obtain photoelectric transfer characteristics optimum for high density picture image reading further avoiding deterioration of the characteristics due to element isolation. CONSTITUTION:Within the title photoelectric transfer device, a photoelectric transfer element part 13 and an amplifier element part 11 amplifying signals from the element part 13 are provided on a substrate 1; the photoelectric transfer element part 13 contains a photodiode as a photoelectric transfer layer; the amplifier element part 11 is composed of a MIS type transistor while the element part 13 is arranged on the element part 11; furthermore, the gate electrode layer 103 of the MIS type transistor in the amplifier element part 11 is commonly used as the lower electrode layer 103 of the photodiode in the photoelectric transfer element part 13. At this time, a doped layer 106 extends farther than an upper electrode layer 107 seen from the normal direction to the substrate 1 surface in the photoelectric transfer element part 13. On the other hand, 110 and 111 respectively represent a source electrode layer and a drain electrode layer.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a photoelectric conversion device in which a plurality of photoelectric conversion element portions are arranged, and particularly, element separation and element effective when miniaturizing the photoelectric conversion element portion for high density image reading. Regarding configuration.

[0002]

2. Description of the Related Art A contact type line sensor for reading a normal size image such as a facsimile or an image reader is 210 mm when reading an A4 size original.
Since the above length is required, it is difficult to manufacture by the wafer process. Therefore, as the light receiving portion (photoelectric conversion element portion) of the contact type line sensor, it is preferable to use amorphous silicon which can form a film over a large area and has good photoelectric conversion characteristics.

As one of photoelectric conversion element parts using amorphous silicon, there is a pin type amorphous silicon photodiode (hereinafter referred to as "a-SiPD"). FIG. 5 is a cross-sectional view showing an example of the layer structure of the pin-type a-SiPD, in which a lower electrode layer 2, a photoelectric conversion layer, an n layer 3, an i layer 4, and a p layer 5 are provided on a substrate 1. The upper electrode layer 6 is sequentially stacked. Here, the n layer 3 and the p layer 5
Has a high conductivity due to the doping process for relaxing the potential barrier between the i layer 4 and the electrode layers 2 and 6 made of metal, and is referred to as a doping layer.

By the way, in a line sensor having a plurality of a-SiPD arrays as described above, it is necessary to separate elements between adjacent light receiving portions. In separating the elements, in general, as shown in FIG. 6, the lower wiring layer (electrode layer) 2 and the doping in contact with the lower wiring layer are taken into consideration in order to easily connect the individual signal line of each light receiving section to the next element. Layer 3 is separated for each individual element. However, since this method requires a patterning step during the formation of the photoelectric conversion layer, the doping layer 3 and i
Contamination is likely to occur at the interface with the layer 4, and the element characteristics are deteriorated due to the influence, and the layer above the doping layer 3 that is in contact with the lower wiring layer 2 due to the step between the element portion and the element portion has a uniform thickness. There were problems such as difficulty in film formation.

As shown in FIG. 7, there is a method of patterning all the layers constituting the photodiode.
The i-layer, especially the side surface of the i-layer 4 is immersed in an etchant, exposed to the atmosphere during the manufacturing process, or the like, which causes a problem of deterioration of sensor performance such as increase of leak current.

Further, as shown in FIG. 8, an upper wiring layer (electrode layer) 6 and a doping layer 5 are used for element isolation of a photodiode.
Although the process can be simplified by patterning and in the same shape, in general, the material of the doping layer 5 is more easily etched than the material of the upper wiring layer 6, and therefore, in practice, as shown in FIG. The end of the doping layer 5 below the wiring layer 6 is over-etched and the end of the metal upper wiring layer 6 is deformed, and in the worst case, it directly contacts the i layer 4 to increase the leakage current. Was present.

On the other hand, in order to read a high-density image, it is required to miniaturize each photoelectric conversion element section and increase the number of photoelectric conversion element sections arranged per unit length. When the area of each photoelectric conversion element section becomes small in this way, the output signal becomes small, so it is preferable to amplify the photoelectric conversion signal in the vicinity of the photoelectric conversion element section. FIG. 10 shows an example of a storage operation type photoelectric conversion device having an amplification function by a MIS transistor. The signal charge generated in the photodiode 23 is amplified by the MIS transistor 21, and the unnecessary signal charge is reset by the reset transistor 22 after the reading is completed.

By the way, in order to extract individual accurate photoelectric conversion signals from a large number of photoelectric conversion element sections, it is necessary to electrically separate the photodiodes for each individual photoelectric conversion element section. FIG. 11 shows a plan view of an example of a conventional line sensor. FIG. 12 is a sectional view taken along the line AA '. The photodiode 23 is separated from the photodiodes of the other photoelectric conversion element sections, and the amplification transistor 21 is located beside the photodiode 22 and is connected through a contact hole. In this way, the photodiode 23
After the film formation, the element is separated from the photodiode of the adjacent photoelectric conversion element section by a method such as etching.

However, a highly accurate etching technique is required in accordance with the miniaturization of the photoelectric conversion element portion for high-density image reading. When non-single crystal silicon such as amorphous silicon is etched to separate the elements. Have the following problems: (1) When the dry etching method is used, the etching method using plasma may damage the etching end face due to the plasma, resulting in deterioration of photoelectric conversion element characteristics such as increase in dark current. (2) 10000 for isotropic etching when using the wet etching method
Å In the case of a thick layer before and after, the effect of side etching must be taken into consideration; (3) The impurity doping layer has, for example, a pi structure or p
When the in-structure is collectively etched, it is difficult to control, and over-etching and under-etching are likely to occur; In addition, in order to improve the performance while reducing the area of the photoelectric conversion element section by increasing the density and increasing the functionality. Aperture ratio (effective area of photodiode in one photoelectric conversion element part)
It is essential to increase. In addition, the influence of resistance and stray capacitance due to the routing of the wiring before entering the amplifier circuit cannot be ignored for the photoelectric signal that has become weaker due to the higher density.

An object of the present invention is to solve the problems of the prior art as described above and to provide a photoelectric conversion device in which there is almost no characteristic deterioration due to element isolation. Further, it is an object of the present invention to provide a photoelectric conversion device which solves the above problems of the prior art and can be applied to high density image reading to obtain good photoelectric conversion characteristics. is there.

[0011]

According to the present invention, the above object is to provide a photoelectric conversion element portion having a plurality of photoelectric conversion element portions on a substrate, and the photoelectric conversion element portion includes a photodiode as a photoelectric conversion layer. In the conversion device, the lower electrode layer on the substrate and at least a part of the photoelectric conversion layer on the lower electrode layer are shared by a plurality of photoelectric conversion element parts, and the photoelectric conversion layer includes a doping layer, An upper electrode layer is formed on the doping layer, the doping layer and the upper electrode layer are individualized for each photoelectric conversion element section, and the doping layer is formed in each photoelectric conversion element section in the direction normal to the substrate surface. The photoelectric conversion device is characterized in that the photoelectric conversion device is extended to the outside of the upper electrode layer when viewed from above.

In the present invention, the photoelectric conversion layer of the photodiode is preferably made of an amorphous semiconductor such as amorphous silicon. The photodiode preferably has a pin structure.

Further, according to the present invention, the above object has a photoelectric conversion element section on a substrate and an amplification element section for amplifying a signal from the photoelectric conversion element section, and the photoelectric conversion element section is a photodiode. In a photoelectric conversion device in which the amplification element section includes a MIS transistor, and the photoelectric conversion element section is disposed on the amplification element section, and the gate of the MIS transistor of the amplification element section is included. The photoelectric conversion device is characterized in that the electrode layer and the lower electrode layer of the photodiode of the photoelectric conversion unit are commonly used.

In the present invention, a plurality of sets of the photoelectric conversion element section and the amplification element section may be provided, and the photoelectric conversion layer and the upper electrode layer of the photodiode may be shared by the plurality of photoelectric conversion element sections. The gate electrode layer of the MIS transistor is made of an n-type polycrystalline semiconductor such as n-type polysilicon, and the photoelectric conversion layer of the photodiode is an i-type non-single-crystal semiconductor layer and the i-type non-single-crystal semiconductor layer. The upper p-type non-single-crystal semiconductor layer may be included. Further, the gate electrode layer of the MIS transistor is made of a p-type polycrystalline semiconductor such as p-type polysilicon, and the photoelectric conversion layer of the photodiode is an i-type non-single-crystal semiconductor layer and the i-type non-single-crystal semiconductor layer. Upper n
And a non-single-crystal semiconductor layer.

In the present invention, the MIS of the amplification element section
Since the photodiode of the photoelectric conversion element portion is present on the gate electrode layer of the p-type transistor, the aperture ratio is improved as compared with the case where the amplification element portion is arranged beside the photoelectric conversion element portion. Since the wiring between them can be made the shortest, the influence of wiring resistance and stray capacitance can be reduced. Also, the film thickness of the gate electrode layer of the MIS transistor may be thinner than that of the photodiode layer, and the lower electrode layer of the photoelectric conversion element portion can be already separated in the step of forming this gate electrode layer, and thus the photoelectric conversion element is formed. The element can be electrically isolated without separating the photoelectric conversion layer and the upper electrode layer of the part by etching, and the adverse effect due to this etching is eliminated.

[0016]

Embodiment 1 FIG. 1 is a sectional view showing a line sensor as an example of the photoelectric conversion device of the present invention. In the figure, 1
Is an insulating substrate. Since amorphous silicon has a small dependency on the underlying substrate, glass or ceramic, for example, can be used as the substrate 1. Reference numeral 2 denotes an electrode (lower electrode layer) for applying a common electric potential to a plurality of sensors, which may be any material having a high conductivity which can be formed on the insulating substrate 1.
For example, metals such as Al and Cr and polycrystalline semiconductors (Si, S
iGe, SiC, etc.) is used. In addition, the insulating substrate 1
If a material having a high light transmittance is used as the lower electrode layer 2 and a material having a high light transmittance such as ITO, TiO ₂ , In ₂ O ₃ , SnO ₂ or CrO ₂ is used for the lower electrode layer 2, It can also be used for line sensors with a structure that receives light input. On the lower electrode layer 2, an appropriate amorphous material (Si, G
After forming the semiconductor layer 4 ′ (including the doping layer 5) and the upper electrode layer (the material is the same as the lower electrode layer) 6 having an appropriate layer structure of e, SiGe, SiC, etc., the upper electrode layer 6 is first formed. After performing the patterning process, the doping layer 5 is patterned. When performing these patterning operations, the edge portion of the upper electrode layer 6 is located inside the edge portion of the doping layer 5 by a distance L when viewed from the direction perpendicular to the substrate 1 (direction normal to the substrate surface), so that the edge is electrically connected. Individual photodiodes are separated into elements to complete a photodiode array.

[0017]

Example 1 A manufacturing example of a line sensor using a pin type a-SiPD as an example of a photoelectric conversion device according to the present invention will be described with reference to FIG. In FIG. 2, 1 is a glass substrate, 2 is a Cr lower electrode layer, 3 is an n-type semiconductor layer, 4 is an i-type semiconductor layer, 5 is a p-type semiconductor layer, and 6 is ITO. The upper electrode layer.

First, a Cr lower electrode layer 2 was formed on a # 7059 glass substrate 1 manufactured by Corning Co., Ltd. by a vapor deposition apparatus,
The patterning was performed by a photolithography method so as to form a common electrode for each photodiode. Next, the substrate 1 was attached to the anode electrode of the capacitively coupled deposition film forming apparatus, the deposition chamber was evacuated to about 10 ⁻⁶ Torr, and the substrate was heated to about 300 ° C. by a heater. The heating temperature can be in the range of 50 ° C to 600 ° C, preferably in the range of 150 ° C to 400 ° C. After the substrate reaches a predetermined temperature, 30 SC of silane gas SiH ₄ is used as a source gas for depositing the n-type semiconductor layer 3.
CM and phosphine gas PH ₃ diluted to 500 ppm with hydrogen gas H ₂ at a flow rate of ₃₀ SCCM to form the n-type semiconductor layer 3 to a thickness of 300 Å, and subsequently a source gas for depositing the i-type semiconductor layer 4. Silane gas as
The i-type semiconductor layer 4 is formed by using H ₄ at a flow rate of 30 SCCM.
Silane gas SiH ₄ is used as a source gas for depositing the p-type semiconductor layer 5 continuously to a thickness of 000Å.
SCCM and diborane gas B ₂ H ₆ diluted to 500 ppm with hydrogen gas H ₂ were used at a flow rate of 30 SCCM to obtain p.
The type semiconductor layer 5 was formed to a thickness of 200Å. Further, the substrate was placed in a vapor deposition apparatus to form an ITO film, which was then patterned into a predetermined shape by photolithography to form the upper electrode layer 6. After that, the p-type semiconductor layer 5 which is a doping layer in contact with the upper electrode layer 6 was patterned into a predetermined shape by a photolithography method so as to be separated into each photodiode. At this time, when viewed from the direction perpendicular to the substrate, the edge portion of the upper electrode layer 6 is L = 3 than the edge portion of the p-type semiconductor layer 5.
It was set so that it was only μm inside.

In each photodiode of the line sensor manufactured by such a method, since the lower electrode layer 2 is not etched for each element and is flat, the semiconductor layers 3 to 6 are films having no unevenness and a stable film thickness. The characteristics are stable, and element isolation can be performed without exposing the end surface portion of the i layer 4, so that the generation of leak current is prevented, and the reverse dark current value is reduced by about an order of magnitude compared with the conventional sensor. Further, the leakage current due to the deformation of the upper electrode layer 6 due to the side etching of the doping layer 5 could be structurally prevented. Further, there was little leakage between the output signals of the elements, and a stable output signal was obtained without providing a special light-shielding window or the like.

[0020]

Embodiment 2 FIG. 3 is a plan view of a line sensor as an example of the photoelectric conversion device of the present invention, and FIG. 4 is a sectional view taken along line AA ′. In these figures, 1 is an insulating substrate, 13 is a photoelectric conversion element section, 11 is an amplification element section, and 12 is a reset transistor. The photoelectric conversion element unit 13 includes an n-type polysilicon lower electrode layer 103, an i-type amorphous silicon layer 105, and a p-type microcrystalline silicon layer 106.
And a transparent upper electrode layer 107. In addition, the amplification element section 11 includes an n-type polysilicon gate electrode layer 103,
The source electrode layer 110 and the drain electrode layer 111 are included. In addition, 102 and 108 are insulating layers, and 104 is a conductor layer for wiring. As described above, according to the present invention, the gate electrode (n-type) 103 of the MIS-type transistor of the amplification element section is used.
In common with the lower electrode layer (n layer) 103 of the photoelectric conversion element portion. The i-type layer 105 and the p-type layer 106 formed on the lower electrode layer are shared by a plurality of photoelectric conversion element portions (one photoelectric conversion element portion is shown in FIG. 3). .

As a semiconductor material for forming the photodiode of the photoelectric conversion element portion, a non-single crystal (polycrystal, microcrystal or amorphous) semiconductor is used, and among them, a microcrystal or amorphous semiconductor is used. In some cases, a transparent electrode layer for collecting photogenerated carriers is required as an electrode (upper electrode) on the light incident side. As the kind of semiconductor material, there are polycrystalline or microcrystalline semiconductors such as Si, SiGe, and
Examples of amorphous semiconductors such as SiC include hydrogenated amorphous silicon (a-Si) alloys and chalcogenide materials. For amorphous silicon alloys, a-Si:
H, a-SiGe: H, a-SiC: H, a-SiN:
H, a-SiO: H, a-GeC: H and the like are used. The upper electrode layer of a photodiode using a polycrystalline semiconductor is a high-concentration impurity layer, and is a p-type high-concentration impurity layer in the case of electrons and an n-type high-concentration impurity layer in the case of holes depending on carriers used as signal charges. Becomes In the case of the Schottky type or MIS type, the upper electrode layer becomes a transparent electrode, and when the work function thereof is larger than the work function of the photoelectric conversion layer, electrons are used, and when the work function is smaller, holes are used as carriers for signal charges. . This is the same when the photoelectric conversion layer is a microcrystalline or amorphous semiconductor. When a microcrystalline or amorphous semiconductor is used as the photoelectric conversion layer, pin is used.
When considering a mold element, the upper electrode is composed of two layers, a high-concentration impurity layer and a transparent electrode layer. As in the case of the polycrystalline semiconductor, the high-concentration impurity layer has p when the signal carrier is an electron.
Type, n-type for holes. As a transparent electrode, I
TO, SnO ₂ , ZnO ₂ or the like is used.

A polycrystalline semiconductor can be used for the lower electrode layer of the photoelectric conversion element portion, and its type is n-type when the carriers used as signal charges are electrons and p-type when it is holes. The type of polycrystalline semiconductor material forming the lower electrode layer includes Si, SiGe, and S as semiconductors.
iC etc. are mentioned. In the present invention, since the lower electrode layer of the photoelectric conversion element part and the gate electrode layer of the MIS type transistor are commonly used, an amplification element depending on the conductivity type of the lower electrode layer of the photoelectric conversion element part. MIS
The type of transistor is determined. That is, when the lower electrode layer is n-type, it is n-MOS, and when it is p-type, it is p-MOS.

In the present invention, metal such as Al, Cr, Pt, Pd,
It is also possible to use Ni or alloys thereof.

As the semiconductor material of the active layer of the MIS transistor, a high mobility of carriers is required, so that a polycrystalline semiconductor or a single crystal semiconductor is used. The insulating film of the MIS transistor is an oxide film formed by oxidation of the semiconductor layer or Si formed by plasma CVD or sputtering.
Nx, SiOx, SiOxNy or the like is used. Also,
A MIS transistor can be used as the reset transistor, and the same material and structure as those of the amplification element portion can be adopted for this.

[0025]

[Embodiment 2] A manufacturing embodiment of the photoelectric conversion device of FIGS. 3 and 4 as an embodiment of the photoelectric conversion device according to the present invention will be described with reference to FIG.

First, a normal LP-CVD is performed on the quartz substrate 1.
Flow rate SiH ₄ 50SCCM, substrate temperature 62
Deposition was performed for 30 minutes under conditions of 0 ° C. and an internal pressure of 0.3 Torr to form a polysilicon layer 101 with a thickness of 3000 Å.
B ^- ions are implanted into the entire surface of this polysilicon layer by ordinary ion implantation under the conditions of a dose amount of 8 × 10 ¹¹ cm ^-2 and 60 keV, and then annealed at 800 ° C. in an N ₂ atmosphere to remove the B ^- ions. Diffusion was performed and the polysilicon layer 101 was made p-type. Further, the polysilicon layer 101 was patterned into a desired shape by an ordinary photolithography process. Then, normal atmospheric pressure CVD
Flow rate 10% hydrogen diluted SiH ₄ 50SCC
Deposition was carried out for 1 minute under the conditions of M, O ₂ 60 SCCM, and substrate temperature of 400 ° C. to form the SiO ₂ insulating layer 102 with a thickness of 1000 Å.

Then, again by the ordinary LP-CVD method, deposition was performed for 30 minutes under the conditions of a gas flow rate of SiH ₄ 50 SCCM, a substrate temperature of 620 ° C. and an internal pressure of 0.3 Torr to form a polysilicon layer 103 with a thickness of 3000 Å. Then, B ⁻ ions are implanted into the entire surface of the polysilicon layer 103 by a normal ion implantation under the conditions of a dose amount of 8 × 10 ¹¹ cm ⁻² and 60 keV, and then annealed at 800 ° C. in a N ₂ atmosphere to form B ⁻ ions. Diffusion was performed to make the polysilicon layer 103 a p-type. Further, the polysilicon layer 103 was etched into a desired shape by an ordinary photolithography process. Further, the SiO ₂ layer 102 is patterned into a desired shape by a normal photolithography process, and an opening for taking out an electrode is formed at a position corresponding to the source electrode layer 110 and the drain electrode layer 111 of the amplifier MOS transistor. The layer was exposed. After this, a normal dose of 5 is used for ion implantation.
By implanting P ⁺ ions on the entire surface under the conditions of × 10 ¹⁵ cm ⁻² and 160 keV, P ⁺ ions are diffused by annealing at 800 ° C. in an N ₂ atmosphere to diffuse the polysilicon layer 103 and the polysilicon layer 101. Exposed part n
⁺ Type, source electrode layer 1 of amplifier MOS transistor
10, drain electrode layer 111, and amplifier MOS
A lower electrode layer 103 of a gate electrode layer of a transistor and a photoelectric conversion element portion was formed. Successively, the thickness of 1
An Al film 104 of 0000 Å was formed and then patterned into a desired shape by a normal photolithography process to form a wiring conductor layer 104. After this, a gas flow rate of Si ₂ H ₆ 1.0SCCM, H ₂
48SCCM, substrate temperature 300 ° C, internal pressure 1.15To
Discharge was performed for 140 minutes under the conditions of rr and RF power of 1.0 W, and the undoped (i-type) a-Si: H layer 105 was heated to 80%.
The gas flow rate is SiH ₄ 0.1SCCM, H ₂ 74.5SCCM, 10
BF ₃ 0.4SCCM diluted with% hydrogen, substrate temperature 200
2 under conditions of ℃, internal pressure of 2.0 Torr and RF power of 33W
Discharging was performed for 0 minutes to form a p-type microcrystalline silicon layer 106 with a thickness of 1000 Å. Further, an ITO film 107 having a thickness of 700 Å was formed by a sputtering method, and a transparent upper common electrode layer 107 was formed by patterning it into a desired shape by an ordinary photolithography process. Further, the microcrystalline silicon layer 106 is formed by an ordinary photolithography process.
The a-Si: H layer 105 was patterned into a desired shape to form the photoelectric conversion element section 13. These ITO films 10
7. Microcrystalline silicon layer 106 and a-Si: H layer 105
The desired shape of does not mean that it is separated for each individual photoelectric conversion element portion, and as shown in FIG. 3, it extends in a direction orthogonal to the AA 'direction so as to be common to the adjacent element portions. In each element portion, the lower electrode layer 103 of the photoelectric conversion element portion is covered. As a result, the adverse effect of the etching end face can be avoided. In addition, as shown in FIG. 4, the edge of the upper electrode layer 107 is located inside the edge of the p-type microcrystalline silicon layer 106 when viewed from the direction perpendicular to the substrate 1, so that the above-described embodiment is performed. The same effect as in Example 1 can be obtained.

Finally, by a normal atmospheric pressure CVD method, a gas flow rate of 10% hydrogen diluted SiH ₄ 50SCCM, O ₂ 60SC.
Deposition is performed for 10 minutes under the conditions of CM and substrate temperature of 400 ° C. to form an SiO ₂ insulating layer 108 with a thickness of 10000Å
A photoelectric conversion device was obtained.

[0029]

As described above, according to the present invention,
It is possible to provide a photoelectric conversion device that stabilizes the thickness of each layer, prevents deformation of the upper electrode layer, and can perform element isolation without increasing leak current, and thus hardly deteriorates characteristics due to element isolation. it can.

Further, according to the present invention, it is possible to improve the aperture ratio, minimize the influence of parasitic capacitance and wiring resistance, and transmit a signal from the photoelectric conversion element section to the amplification element section. This not only makes it possible to reduce the noise, but also to speed up the line sensor.

[Brief description of drawings]

FIG. 1 is a cross-sectional view of a photoelectric conversion device according to the present invention.

FIG. 2 is a sectional view of a photoelectric conversion device according to the present invention.

FIG. 3 is a plan view of a photoelectric conversion device according to the present invention.

FIG. 4 is a cross-sectional view taken along the line A-A ′ of FIG.

FIG. 5 is a cross-sectional view of a conventional photoelectric conversion device.

FIG. 6 is a cross-sectional view of a conventional photoelectric conversion device.

FIG. 7 is a cross-sectional view of a conventional photoelectric conversion device.

FIG. 8 is a cross-sectional view of a conventional photoelectric conversion device.

FIG. 9 is a cross-sectional view of a conventional photoelectric conversion device.

FIG. 10 shows an example of a storage operation type photoelectric conversion device having an amplification function by a MIS transistor.

FIG. 11 is a plan view of a conventional photoelectric conversion device.

FIG. 12 is a cross-sectional view taken along the line A-A ′ of FIG.

[Explanation of symbols]

1 Insulation board 2 Lower electrode layer 3,5 Doping layer 4 i layer 4'semiconductor layer 6 Upper electrode layer 11,21 Amplifying element section 12,22 Reset transistor 13, 23 Photoelectric conversion element section 102, 108 insulating layer 103 Lower electrode layer (gate electrode layer) 104 wiring conductor layer 105 i layer 106 doping layer 107 transparent upper electrode layer 110 Source electrode layer 111 drain electrode layer

Claims (7)

[Claims] 1. A photoelectric conversion device having a plurality of photoelectric conversion element portions on a substrate, wherein the photoelectric conversion element portion includes a photodiode as a photoelectric conversion layer, wherein a lower electrode layer on the substrate and the lower electrode layer on the substrate. At least a part of the photoelectric conversion layer is shared by a plurality of photoelectric conversion element parts, the photoelectric conversion layer includes a doping layer, and an upper electrode layer is formed on the doping layer. And the upper electrode layer is individualized for each photoelectric conversion element portion, and in each photoelectric conversion element portion, the doping layer extends to the outside of the upper electrode layer when viewed in the normal direction to the substrate surface. And a photoelectric conversion device. 2. The photoelectric conversion device according to claim 1, wherein the photoelectric conversion layer of the photodiode is made of an amorphous semiconductor. 3. The photoelectric conversion device according to claim 1, wherein the photodiode has a pin structure. 4. A photoelectric conversion element section on a substrate, and an amplification element section for amplifying a signal from the photoelectric conversion element section, and the photoelectric conversion element section includes a photodiode as a photoelectric conversion layer. In a photoelectric conversion device having an MIS-type transistor as an element section, the photoelectric conversion element section is disposed on the amplification element section, and the MI of the amplification element section is
A photoelectric conversion device, wherein a gate electrode layer of an S-type transistor and a lower electrode layer of a photodiode of the photoelectric conversion unit are commonly used. 5. A plurality of sets of the photoelectric conversion element section and the amplification element section are provided, and the photoelectric conversion layer and the upper electrode layer of the photodiode are shared by the plurality of photoelectric conversion element sections. The photoelectric conversion device according to claim 4, which is characterized in that: 6. The gate electrode layer of the MIS transistor is made of an n-type polycrystalline semiconductor, and the photoelectric conversion layer of the photodiode is an i-type non-single-crystal semiconductor layer and a p-type on the i-type non-single-crystal semiconductor layer. The photoelectric conversion device according to claim 4, comprising a non-single crystal semiconductor layer. 7. The gate electrode layer of the MIS transistor is made of a p-type polycrystalline semiconductor, and the photoelectric conversion layer of the photodiode is an i-type non-single-crystal semiconductor layer and an n-type on the i-type non-single-crystal semiconductor layer. The photoelectric conversion device according to claim 4, comprising a non-single crystal semiconductor layer.