JPH04259257A - Photoelectric converter - Google Patents

Abstract

PURPOSE:To avoid generation of a pixel defect without reducing the area of a pixel by so disposing a pixel region to be determined by a superposition of lower and upper electrodes as to be deviated so as not to be superposed on a position of an opening of an interlayer insulating film. CONSTITUTION:A scanning integrated circuit board 701 is so formed as to output optical charge by a scanning element through a switch from photosensors arranged in one dimension state. The photosensors are provided on the board 701, and a lower electrode 709 electrically connected to the switch through an opening of an interlayer insulating film 706, a photoconductive film 711 for generating optical charge, and an upper electrode 713 are sequentially deposited in this order on the switch through the opening of the film 706. A pixel region to be decided by a superposition of the electrodes 706, 713 in this state is so disposed as to be deviated so as not to be superposed on the position of the opening of the film 706. Thus, even if it is manufactured by a simple process, a pixel defect can be eliminated without reducing the area of the pixel.

Description

[Detailed description of the invention]

0001

[Field of Industrial Application] The present invention relates to a photoelectric conversion element, and more particularly to a scanning integrated circuit board configured to extract photoelectric charges from one-dimensionally arranged photosensors by a scanning element via a switch. The present invention relates to a photoelectric conversion device in which the above photosensor is deposited and formed by a laminating means.

0002

[Prior Art] In recent years, facsimiles, digital copying machines,
With the spread of image information processing devices such as image readers and video cameras, the frequency of use of photoelectric conversion devices such as line sensors with photosensors arranged one-dimensionally and area sensors arranged two-dimensionally has increased. There is. In these image processing devices, it is important to increase the density of pixels in order to further improve the quality of images, but under design conditions such as arranging switch elements and wiring electrodes on the same substrate, pixel As area limitations increase, the first step is to develop a stacked photoelectric conversion device in which a switch element circuit is fabricated on a substrate, and then a photoconductive film and an electrode film are deposited to form a pixel region. Active.

[0003] In the above-mentioned stacked photoelectric conversion device,
The following advantages can be considered.

(1) Functions can be separated in the substrate section/laminated section according to the characteristics of the materials.

(2) Large area can be created all at once.

(3) It is a low temperature process that is not subject to substrate commitment.

(4) The production process is easy and costs can be reduced.

[0008]

However, in order to realize the above-described stacked photoelectric conversion device, a step of flattening the substrate is usually required to eliminate pixel defects such as short circuits. Various methods have been used in the past to achieve this planarization, but in order to sufficiently reduce the unevenness on the surface of the substrate, it is generally necessary to go through a complicated process. Therefore, one of the advantages of the stacked photoelectric conversion device, which is that a device with good performance can be obtained through a simple process, cannot be utilized. Particularly in the case of a one-dimensional line sensor, it is a big problem that the process becomes complicated and the cost becomes high.

[0009]

OBJECTS OF THE INVENTION The present invention solves these conventional problems, and provides a reliable system that does not reduce the pixel area even when manufactured using a simple process, and also avoids the occurrence of pixel defects. The present invention aims to provide a photoelectric conversion device with a highly flexible configuration.

0010

[Means for solving the problem] Therefore, in the present invention,
In order to configure the above-mentioned photosensor, a scanning integrated circuit board is placed on a scanning integrated circuit board configured to take out photocharges from photosensors arranged in a one-dimensional manner through a switch and a scanning element through an opening in an interlayer insulating film. In a photoelectric conversion device in which a lower electrode film electrically connected to the switch, a photoconductive film that generates photocharges, and an upper electrode are deposited in this order, the lower electrode and the upper electrode overlap. The pixel area determined by the area is shifted so as not to overlap the position of the opening in the interlayer insulating film.

[0011]

[Operation] Therefore, the planarization process can be substantially omitted, and even if manufactured using a simple process, a highly reliable photoelectric conversion device that does not reduce the pixel area or cause pixel defects can be realized. can do.

0012

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be explained in detail below with reference to illustrated embodiments.

What is shown in FIG. 1 is a typical example of a laminated substrate in a conventional solid-state imaging device, which was cited for understanding the present invention. In the figure, region (1) is an element isolation section, region (2) is a switch element section, and region (3) is an opening for connecting the switch element/photoelectric conversion element. As is clear from the figure, there is no unevenness at all in region (3). In addition, in region (2), there are irregularities of 1 μm or less mainly due to the presence of gate electrodes and wiring electrodes;
Since the insulating film having the above thickness is covered, the steepness of the steps and slopes of the unevenness can be suppressed. However, in region (3), several steps of about 1 μm overlap, resulting in a step with a thickness of several μm as a whole. Therefore, if the planarization process is not performed, the steps will be exposed as they are on the substrate surface. Therefore, if the pixel region is not set avoiding the region (3), defects such as short circuits may be induced in the photoelectric conversion section formed by stacking layers. Similarly, considering the planar structure of a stacked photoelectric conversion device, the area sensor has a two-dimensionally limited location as shown in FIG. If this is avoided, the pixel area 202 will be significantly reduced, corresponding to the area of the aperture.

Therefore, in the line sensor of the present invention, as shown in FIG. 3, by taking advantage of the advantageous condition that the location is restricted only in one dimension, pixels are placed in the connection opening. They are placed offset to either the front or back. In this way, the pixel area will not be reduced. However, in the embodiment shown in FIG. 3, wirings 303 and 304 connecting gate electrodes 305 and 306 of transistors that transfer or reset optical signal charges and a shift register (not shown) are drawn out downward. Therefore, due to the arrangement with the optical signal charge readout circuit formed below the electrode 307, the wiring may be drawn out upward in the figure as shown by reference numerals 403 and 404 in FIG. be. In particular, as the pixel density increases,
It is natural to draw the wiring upwards in the figure as shown by the symbols 503 and 504 in FIG. 5, but as a result, the ratio of the width b of the wiring 503 to the width a of one pixel increases as the density increases. Therefore, even in the case of a line sensor, the region without unevenness on the base becomes narrow, and if the sensor is arranged avoiding the unevenness on the base, the loss in pixel area cannot be ignored. Therefore,
As shown in FIG. 6, it is preferable to arrange the sensor so as to overlap the portion where the wirings 603 and 604 extend. As a result, the pixel area is greatly improved, and furthermore, pixel defects due to short circuits and the like do not occur.

[0015] For the above reasons, if the positioning of the pixel area is devised, pixel defects can be prevented without reducing the pixel area even when photosensors are layered on a substrate using a simple process. A highly reliable photoelectric conversion device that can avoid this can be realized.

[0016]

[Embodiment 1] Next, an embodiment of the present invention will be described with reference to FIG. First, a normal LP is placed on a quartz substrate 701.
-By CVD method, SiH4 gas flow rate 50SCCM,
Deposition is performed for 10 minutes at a substrate temperature of 620° C. and an internal pressure of 0.3 Torr to form a polysilicon layer 702 with a thickness of 1000 Å. This polysilicon layer is then etched into a desired shape using a normal photolithography process.

[0017] Thereafter, in an O2 atmosphere at 900°C,
．． By performing thermal oxidation for 5 hours, an oxide film 704 with a thickness of 500 Å is formed on the surface of the polysilicon layer 702. Subsequently, SiH
4 gas flow rate 50SCCM, substrate temperature 620°C, internal pressure 0.
Deposition is performed for 30 minutes at 3 Torr to form a polysilicon layer 705 with a thickness of 3000 Å. This polysilicon layer is implanted with a dose of 8x by normal ion implantation.
B- ions are implanted into the entire surface under the conditions of 1015 cm-2 and 60 keV, and then annealing is performed in a N2 atmosphere8.
By carrying out the process at 00°C, B- ions are diffused and the polysilicon layer 705 becomes P type. After this,
The polysilicon layer 705 is etched into a desired shape by a normal photolithography process, and is used as a gate electrode of a MOS transistor.

After this, P+ ions are implanted into the entire surface by normal ion implantation at a dose of 5 x 1015 cm-2 and 160 keV, and then annealing is performed with N.
2. By performing the process in an atmosphere of 800° C., P+ ions are diffused to form the source and drain electrodes 703 and 703' of the MOS transistor.

[0019] Subsequently, by the usual plasma CVD method,
SiH4 gas flow rate 0.5SCCM, NH3 14.4
SCCM, H2 4.5SCCM, substrate temperature 200℃,
Deposition was performed for 160 minutes under the conditions of RF power of 3.5 W and internal pressure of 0.15 Torr to form a SiN layer 706 with a thickness of 8000 Å.
Form to a thickness of . This SiN layer and oxide film 704 are
Etched into the desired shape using a normal photolithography process,
Open holes for the source and drain electrodes.

On top of this, an Al layer 707 is formed by sputtering.
is deposited to a thickness of 10,000 Å and etched into a desired shape using a normal photolithography process to form a wiring electrode from a MOS transistor. After this, SiH4 gas flow rate 0.5SCCM, NH3
14.4SCCM, H2 4.5SCCM, substrate temperature 2
00℃, RF power 3.5W, internal pressure 0.15Torr
The SiN layer 708 was deposited for 60 minutes under the following conditions.
The film is formed to a thickness of 0.00 Å and used as a passivation film for underlying circuits such as MOS transistors. This SiN layer 708
is etched into a desired shape using a normal photolithography process to partially expose the surface of the Al electrode 707 and form an opening for connecting the wiring from the MOS transistor to the photoelectric conversion section.

Next, a Cr layer 7 is formed by a normal sputtering method.
09 is deposited to a thickness of 3000 Å and etched into a desired shape by a normal photolithography process to form the lower electrode of the photoelectric conversion section, that is, the lower pixel electrode. Here, as shown in FIGS. 4, 7, and 8, the portion where the pixels are to be formed is designed in advance so that it is a flat area with no underlying pattern.

Next, by the usual plasma CVD method, S
i2 H6 Gas flow rate 1.0SCCM, PH3 1.0
SCCM, H248.0SCCM, substrate temperature 300℃,
1 under the conditions of RF power 1.5W and internal pressure 1.2Torr.
Deposition was performed for 0 minutes, and n+ type amorphous silicon (n+
-a-Si:H) layer 710 with a thickness of 1000 Å, followed by Si2 H6 gas flow rate 1 without breaking the vacuum.
．． 0SCCM, H2 48.0SCCM, substrate temperature 30
Deposition was performed for 140 minutes at 0° C., RF power 1.0 W, and internal pressure 1.15 Torr to form an undoped amorphous silicon (ia-a-Si:H) layer 711 with a thickness of 8000 Å. Continuously, without breaking the vacuum, SiH4 gas flow rate was 0.1SCCM, B2 H6 was 0.2SCCM,
Deposition was performed for 20 minutes under the conditions of H2 74.5SCCM, substrate temperature 200°C, RF power 33.0W, and internal pressure 2.0 Torr, and p+ type microcrystalline silicon (p+ -μ
c-Si:H) layer 712 is formed to a thickness of 1000 Å.

Thereafter, ITO 713 with a thickness of 700 Å is deposited by sputtering, and etched into a desired shape by a normal photolithography process to separate the upper electrode 713 of the photodiode for each pixel.

[0024] Next, the p+-μc-Si:H layer 712
, ia-Si:H layer 711, and n+-a-Si:H layer 710 are etched into a desired shape using a normal photolithography process to perform pixel separation.

[0025] Thereafter, by the usual plasma CVD method,
SiH4 gas flow rate 0.5SCCM, NH3 14.4
SCCM, H2 4.5SCCM, substrate temperature 200℃,
Deposition was performed for 160 minutes under the conditions of RF power of 3.5 W and internal pressure of 0.15 Torr to form a SiN layer 714 with a thickness of 8000 Å.
It was formed with a thickness of . This SiN layer 714 is etched into a desired shape by a normal photolithography process, and a hole is opened for the upper wiring electrode to be taken out.

[0026] On top of this, one layer of Al was applied by sputtering.
The film is deposited to a thickness of 0,000 Å and etched into a desired shape using a normal photolithography process to form an upper wiring electrode 715. In this way, a line sensor, which is one of the photoelectric conversion devices of the present invention, was created. The photoelectric conversion device formed by the above process was made of a-Si:H
There were almost no irregularities in the area where the photoelectric conversion section formed of layers was placed, and when the operation was checked, no defects due to short circuits were detected.

[0027]

[Embodiment 2] Further, another embodiment of the present invention will be explained based on FIG. 9. First, a normal LP-
Deposition is performed by CVD for 10 minutes under the conditions of SiH4 gas flow rate of 50 SCCM, substrate temperature of 620° C., and internal pressure of 0.3 Torr to form a polysilicon layer 902 with a thickness of 1000 Å. This polysilicon layer is etched into a desired shape using a normal photolithography process.

[0028] Thereafter, in an O2 atmosphere at 900°C, 2
．． By performing thermal oxidation for 5 hours, an oxide film 904 with a thickness of 500 Å is formed on the surface of the polysilicon layer 902. Subsequently, SiH4 was
Gas flow rate 50SCCM, substrate temperature 620°C, internal pressure 0.
Deposition is performed for 30 minutes at 3 Torr to form a polysilicon layer 905 with a thickness of 3000 Å. This polysilicon layer is implanted with a dose of 8x by normal ion implantation.
B- ions were implanted into the entire surface under the conditions of 1015 cm-2 and 60 keV, and then annealing was performed in a N2 atmosphere at 80 keV.
By carrying out the process at 0°C, B- ions are diffused and the polysilicon layer 905 becomes P type. Thereafter, the polysilicon layer 905 is etched into a desired shape by a normal photolithography process to form a gate electrode of a MOS transistor.

After this, P+ ions are implanted into the entire surface by normal ion implantation at a dose of 5 x 1015 cm-2 and 160 keV, and then annealing is performed with N.
2. By performing the process in an atmosphere of 800° C., P+ ions are diffused to form the source and drain electrodes 903 and 903' of the MOS transistor.

[0030] Subsequently, by the usual plasma CVD method,
SiH4 gas flow rate 0.5SCCM, NH3 14.4
SCCM, H2 4.5SCCM, substrate temperature 200℃,
Deposition was performed for 160 minutes under the conditions of RF power of 3.5 W and internal pressure of 0.15 Torr, and the SiN layer 906 was deposited to a thickness of 8000 Å.
Form to a thickness of . This SiN layer and oxide film 904 are
Etched into the desired shape using a normal photolithography process,
Open holes for the source and drain electrodes.

On top of this, an Al layer 907 is formed by sputtering.
is deposited to a thickness of 10,000 Å and etched into a desired shape using a normal photolithography process to form a wiring electrode from a MOS transistor.

[0032] After this, SiH4 gas flow rate 0.5SCCM, NH3 14.
4SCCM, H2 4.5SCCM, substrate temperature 200℃
, RF power of 3.5 W, internal pressure of 0.15 Torr for 60 minutes, and the SiN layer 908 was deposited to a thickness of 3000 Å.
The film is formed to a thickness of 100 mL to serve as a passivation film for underlying circuits such as MOS transistors. This SiN layer 908 is etched into a desired shape by a normal photolithography process, and A
A part of the surface of the l electrode 907 is exposed to form an opening for connecting the wiring from the MOS transistor to the photoelectric conversion section.

Next, a Cr layer 90 is formed by a normal sputtering method.
9 is deposited to a thickness of 3000 Å and etched into a desired shape by a normal photolithography process to form the lower electrode of the photoelectric conversion section, that is, the lower pixel electrode. As shown in FIG. 6, the portion where the pixel is to be formed is designed so that the patterns of wiring electrodes 603 and 604 (909 in FIG. 10) from the MOS transistors partially overlap with the underlying layer.

Next, by the usual plasma CVD method, S
i2 H6 Gas flow rate 1.0SCCM, PH3 1.0
SCCM, H248.0SCCM, substrate temperature 300℃,
1 under the conditions of RF power 1.5W and internal pressure 1.2Torr.
Deposition was performed for 0 minutes, and n+ type amorphous silicon (n+
-a-Si:H) layer 910 is formed to a thickness of 1000 Å, followed by Si2 H6 gas flow rate of 1.0 SCCM, H2 of 48.0 SCCM, and substrate temperature of 3 without breaking the vacuum.
00℃, RF power 1.0W, internal pressure 1.15Torr
An undoped amorphous silicon (ia-Si:H) layer 911 with a thickness of 8000 Å was formed by deposition for 140 minutes under the conditions of
6 Gas flow rate 0.1SCCM, B2 H6 0.2SC
CM, H2 74.5SCCM, substrate temperature 200℃, R
2 under the conditions of F power 33.0W and internal pressure 2.0Torr.
Deposition was performed for 0 minutes, and p+ type microcrystalline silicon (p+
-μc-Si:H) layer 912 is formed with a thickness of 1000 Å.

Thereafter, ITO 713 with a thickness of 700 Å is deposited by sputtering and etched into a desired shape by a normal photolithography process to separate the upper electrode 913 of the photodiode for each pixel.

[0036] Next, p + -μc-Si:H layer 712
, ia-Si:H layer 911, and n+-a-Si:H layer 910 are etched into a desired shape using a normal photolithography process to perform pixel separation.

[0037] Thereafter, by the usual plasma CVD method,
SiH4 gas flow rate 0.5SCCM, NH3 14.4
SCCM, H2 4.5SCCM, substrate temperature 200℃,
Deposition was performed for 160 minutes under the conditions of RF power of 3.5 W and internal pressure of 0.15 Torr, and the SiN layer 914 was deposited to a thickness of 8000 Å.
Form to a thickness of . This SiN layer 914 is etched into a desired shape by a normal photolithography process, and a hole is opened for the upper wiring electrode to be taken out.

On top of this, a 10% Al layer is formed by sputtering.
The upper wiring electrode 915 is deposited to a thickness of 0.000 Å and etched into a desired shape using a normal photolithography process. In this way, a line sensor, which is one of the photoelectric conversion devices of the present invention, was created. In the photoelectric conversion device formed by the above process, the unevenness existing on the substrate is about 1 μm of the wiring electrode Al. a-Si: Approximately 1 μm thicker than the H layer
However, since it is relaxed by the passivation film 908 deposited thereon, no defects due to short circuits were detected when the operation was checked.

[0039]

Effects of the Invention The present invention has been described in detail above, and the pixel area determined by the overlapping portion of the lower electrode and the upper electrode is shifted so as not to overlap the position of the opening of the interlayer insulating film. Therefore, even if manufactured using a simple process, the pixel area will not decrease.
A photoelectric conversion device with a highly reliable configuration that can avoid pixel defects can be provided.

[Brief explanation of the drawing]

FIG. 1 shows an example of a solid-state imaging device formed by a conventional method.

FIG. 2 is a conceptual diagram for explaining the effects of the present invention.

FIG. 3 is a conceptual diagram for explaining the effects of the present invention.

FIG. 4 shows one embodiment of the invention.

FIG. 5 shows one of the other embodiments of the invention.

FIG. 6 shows one of still other embodiments of the present invention.

7 is a sectional view taken along line A-A' in FIG. 4. FIG.

8 is a sectional view taken along line B-B' in FIG. 4. FIG.

9 is a sectional view taken along line C-C' in FIG. 6. FIG.

10 is a sectional view taken along line D-D' in FIG. 6;

[Explanation of symbols]

101 Semiconductor substrate 102 Field oxide film 103 Source electrode 104 of switch MOS
Switch MOS source electrode 105 Gate oxide film 106 Gate electrode 107 Passivation film 108 Buried electrode 109 Light shielding film 110 Interlayer insulating film 111 Lower electrode 112 Photoconductive film 113 Upper electrode 201, 301, 401, 501, 601 Connection opening 202 , 302, 402, 502, 602 Pixel region 303, 403, 503, 603 304, 404, 504, 604 Wiring electrode 30
5,405,505,605 306,406,506,606 Gate electrode 3
07,407,507,607 Storage capacitor electrode 7
01,901 Substrate 702,902 Polycrystalline silicon film 703,70
3', 903, 903' Source, drain 704, 904 Gate insulating film 705, 905 Gate electrode 706, 906 Interlayer insulating film 707, 907 Wiring electrode 708, 908 Passivation film 709, 9
09 Lower electrode 710, 910 Highly doped semiconductor layer 711, 911 indicating one semiconductor type Undoped semiconductor layer 712, 9
12 Highly doped semiconductor layer 713, 913 showing the other semiconductor type Upper electrode 714, 914 Passivation film 715, 9
15 Wiring electrode

Claims (3)

[Claims] 1. An interlayer insulating film is provided on a scanning integrated circuit board configured to extract photocharges from the one-dimensionally arranged photosensors via a switch and a scanning element, in order to configure the photosensors. In a photoelectric conversion device, a lower electrode film electrically connected to the switch through an opening, a photoconductive film that generates photocharges, and an upper electrode are deposited in this order. and a photoelectric conversion device, wherein a pixel region determined by an overlapping portion of the upper electrode is shifted so as not to overlap the position of the opening of the interlayer insulating film. 2. The pixel area is arranged on the scanning integrated circuit board so as to overlap with a part of the wiring electrode pattern from each switch corresponding to the one-dimensionally arranged photosensors. The photoelectric conversion device according to claim 1, characterized in that: 3. The photoelectric conversion device according to claim 1, wherein the photoelectric film is made of hydrogenated amorphous silicon.